ethernet/apple/bmac.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * mace.h - definitions for the registers in the "Big Mac"
0004  *  Ethernet controller found in PowerMac G3 models.
0005  *
0006  * Copyright (C) 1998 Randy Gobbel.
0007  */
0008
0009 /* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal"
0010  * (HME) controller.  See sunhme.h
0011  */
0012
0013
0014 /* register offsets */
0015
0016 /* global status and control */
0017 #define XIFC        0x000   /* low-level interface control */
0018 #   define  TxOutputEnable  0x0001 /* output driver enable */
0019 #   define  XIFLoopback 0x0002 /* Loopback-mode XIF enable */
0020 #   define  MIILoopback 0x0004 /* Loopback-mode MII enable */
0021 #   define  MIILoopbackBits 0x0006
0022 #   define  MIIBuffDisable  0x0008 /* MII receive buffer disable */
0023 #   define  SQETestEnable   0x0010 /* SQE test enable */
0024 #   define  SQETimeWindow   0x03e0 /* SQE time window */
0025 #   define  XIFLanceMode    0x0010 /* Lance mode enable */
0026 #   define  XIFLanceIPG0    0x03e0 /* Lance mode IPG0 */
0027 #define TXFIFOCSR   0x100   /* transmit FIFO control */
0028 #   define  TxFIFOEnable    0x0001
0029 #define TXTH        0x110   /* transmit threshold */
0030 #   define  TxThreshold 0x0004
0031 #define RXFIFOCSR   0x120   /* receive FIFO control */
0032 #   define  RxFIFOEnable    0x0001
0033 #define MEMADD      0x130   /* memory address, unknown function */
0034 #define MEMDATAHI   0x140   /* memory data high, presently unused in driver */
0035 #define MEMDATALO   0x150   /* memory data low, presently unused in driver */
0036 #define XCVRIF      0x160   /* transceiver interface control */
0037 #   define  COLActiveLow    0x0002
0038 #   define  SerialMode  0x0004
0039 #   define  ClkBit      0x0008
0040 #   define  LinkStatus  0x0100
0041 #define CHIPID          0x170   /* chip ID */
0042 #define MIFCSR      0x180   /* ??? */
0043 #define SROMCSR     0x190   /* SROM control */
0044 #   define  ChipSelect  0x0001
0045 #   define  Clk     0x0002
0046 #define TXPNTR      0x1a0   /* transmit pointer */
0047 #define RXPNTR      0x1b0   /* receive pointer */
0048 #define STATUS      0x200   /* status--reading this clears it */
0049 #define INTDISABLE  0x210   /* interrupt enable/disable control */
0050 /* bits below are the same in both STATUS and INTDISABLE registers */
0051 #   define  FrameReceived   0x00000001 /* Received a frame */
0052 #   define  RxFrameCntExp   0x00000002 /* Receive frame counter expired */
0053 #   define  RxAlignCntExp   0x00000004 /* Align-error counter expired */
0054 #   define  RxCRCCntExp 0x00000008 /* CRC-error counter expired */
0055 #   define  RxLenCntExp 0x00000010 /* Length-error counter expired */
0056 #   define  RxOverFlow  0x00000020 /* Receive FIFO overflow */
0057 #   define  RxCodeViolation 0x00000040 /* Code-violation counter expired */
0058 #   define  SQETestError    0x00000080 /* Test error in XIF for SQE */
0059 #   define  FrameSent   0x00000100 /* Transmitted a frame */
0060 #   define  TxUnderrun  0x00000200 /* Transmit FIFO underrun */
0061 #   define  TxMaxSizeError  0x00000400 /* Max-packet size error */
0062 #   define  TxNormalCollExp 0x00000800 /* Normal-collision counter expired */
0063 #   define  TxExcessCollExp 0x00001000 /* Excess-collision counter expired */
0064 #   define  TxLateCollExp   0x00002000 /* Late-collision counter expired */
0065 #   define  TxNetworkCollExp 0x00004000 /* First-collision counter expired */
0066 #   define  TxDeferTimerExp 0x00008000 /* Defer-timer expired */
0067 #   define  RxFIFOToHost    0x00010000 /* Data moved from FIFO to host */
0068 #   define  RxNoDescriptors 0x00020000 /* No more receive descriptors */
0069 #   define  RxDMAError  0x00040000 /* Error during receive DMA */
0070 #   define  RxDMALateErr    0x00080000 /* Receive DMA, data late */
0071 #   define  RxParityErr 0x00100000 /* Parity error during receive DMA */
0072 #   define  RxTagError  0x00200000 /* Tag error during receive DMA */
0073 #   define  TxEOPError  0x00400000 /* Tx descriptor did not have EOP set */
0074 #   define  MIFIntrEvent    0x00800000 /* MIF is signaling an interrupt */
0075 #   define  TxHostToFIFO    0x01000000 /* Data moved from host to FIFO  */
0076 #   define  TxFIFOAllSent   0x02000000 /* Transmitted all packets in FIFO */
0077 #   define  TxDMAError  0x04000000 /* Error during transmit DMA */
0078 #   define  TxDMALateError  0x08000000 /* Late error during transmit DMA */
0079 #   define  TxParityError   0x10000000 /* Parity error during transmit DMA */
0080 #   define  TxTagError  0x20000000 /* Tag error during transmit DMA */
0081 #   define  PIOError    0x40000000 /* PIO access got an error */
0082 #   define  PIOParityError  0x80000000 /* PIO access got a parity error  */
0083 #   define  DisableAll  0xffffffff
0084 #   define  EnableAll   0x00000000
0085 /* #    define  NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */
0086 #   define  EnableNormal    ~(FrameReceived | FrameSent)
0087 #   define  EnableErrors    (FrameReceived | FrameSent)
0088 #   define  RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \
0089                  RxLenCntExp | RxOverFlow | RxCodeViolation)
0090 #   define  TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \
0091                  TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp)
0092
0093 /* transmit control */
0094 #define TXRST       0x420   /* transmit reset */
0095 #   define  TxResetBit  0x0001
0096 #define TXCFG       0x430   /* transmit configuration control*/
0097 #   define  TxMACEnable 0x0001 /* output driver enable */
0098 #   define  TxSlowMode  0x0020 /* enable slow mode */
0099 #   define  TxIgnoreColl    0x0040 /* ignore transmit collisions */
0100 #   define  TxNoFCS     0x0080 /* do not emit FCS */
0101 #   define  TxNoBackoff 0x0100 /* no backoff in case of collisions */
0102 #   define  TxFullDuplex    0x0200 /* enable full-duplex */
0103 #   define  TxNeverGiveUp   0x0400 /* don't give up on transmits */
0104 #define IPG1        0x440   /* Inter-packet gap 1 */
0105 #define IPG2        0x450   /* Inter-packet gap 2 */
0106 #define ALIMIT      0x460   /* Transmit attempt limit */
0107 #define SLOT        0x470   /* Transmit slot time */
0108 #define PALEN       0x480   /* Size of transmit preamble */
0109 #define PAPAT       0x490   /* Pattern for transmit preamble */
0110 #define TXSFD       0x4a0   /* Transmit frame delimiter */
0111 #define JAM     0x4b0   /* Jam size */
0112 #define TXMAX       0x4c0   /* Transmit max pkt size */
0113 #define TXMIN       0x4d0   /* Transmit min pkt size */
0114 #define PAREG       0x4e0   /* Count of transmit peak attempts */
0115 #define DCNT        0x4f0   /* Transmit defer timer */
0116 #define NCCNT       0x500   /* Transmit normal-collision counter */
0117 #define NTCNT       0x510   /* Transmit first-collision counter */
0118 #define EXCNT       0x520   /* Transmit excess-collision counter */
0119 #define LTCNT       0x530   /* Transmit late-collision counter */
0120 #define RSEED       0x540   /* Transmit random number seed */
0121 #define TXSM        0x550   /* Transmit state machine */
0122
0123 /* receive control */
0124 #define RXRST       0x620   /* receive reset */
0125 #   define  RxResetValue    0x0000
0126 #define RXCFG       0x630   /* receive configuration control */
0127 #   define  RxMACEnable 0x0001 /* receiver overall enable */
0128 #   define  RxCFGReserved   0x0004
0129 #   define  RxPadStripEnab  0x0020 /* enable pad byte stripping */
0130 #   define  RxPromiscEnable 0x0040 /* turn on promiscuous mode */
0131 #   define  RxNoErrCheck    0x0080 /* disable receive error checking */
0132 #   define  RxCRCNoStrip    0x0100 /* disable auto-CRC-stripping */
0133 #   define  RxRejectOwnPackets 0x0200 /* don't receive our own packets */
0134 #   define  RxGrpPromisck   0x0400 /* enable group promiscuous mode */
0135 #   define  RxHashFilterEnable 0x0800 /* enable hash filter */
0136 #   define  RxAddrFilterEnable 0x1000 /* enable address filter */
0137 #define RXMAX       0x640   /* Max receive packet size */
0138 #define RXMIN       0x650   /* Min receive packet size */
0139 #define MADD2       0x660   /* our enet address, high part */
0140 #define MADD1       0x670   /* our enet address, middle part */
0141 #define MADD0       0x680   /* our enet address, low part */
0142 #define FRCNT       0x690   /* receive frame counter */
0143 #define LECNT       0x6a0   /* Receive excess length error counter */
0144 #define AECNT       0x6b0   /* Receive misaligned error counter */
0145 #define FECNT       0x6c0   /* Receive CRC error counter */
0146 #define RXSM        0x6d0   /* Receive state machine */
0147 #define RXCV        0x6e0   /* Receive code violation */
0148
0149 #define BHASH3      0x700   /* multicast hash register */
0150 #define BHASH2      0x710   /* multicast hash register */
0151 #define BHASH1      0x720   /* multicast hash register */
0152 #define BHASH0      0x730   /* multicast hash register */
0153
0154 #define AFR2        0x740   /* address filtering setup? */
0155 #define AFR1        0x750   /* address filtering setup? */
0156 #define AFR0        0x760   /* address filtering setup? */
0157 #define AFCR        0x770   /* address filter compare register? */
0158 #   define  EnableAllCompares 0x0fff
0159
0160 /* bits in XIFC */