apm/xgene/xgene_enet_xgmac.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Applied Micro X-Gene SoC Ethernet Driver
0003  *
0004  * Copyright (c) 2014, Applied Micro Circuits Corporation
0005  * Authors: Iyappan Subramanian <isubramanian@apm.com>
0006  *      Keyur Chudgar <kchudgar@apm.com>
0007  */
0008
0009 #ifndef __XGENE_ENET_XGMAC_H__
0010 #define __XGENE_ENET_XGMAC_H__
0011
0012 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
0013 #define BLOCK_AXG_MAC_OFFSET        0x0800
0014 #define BLOCK_AXG_STATS_OFFSET      0x0800
0015 #define BLOCK_AXG_MAC_CSR_OFFSET    0x2000
0016 #define BLOCK_PCS_OFFSET        0x3800
0017
0018 #define XGENET_CONFIG_REG_ADDR      0x20
0019 #define XGENET_SRST_ADDR        0x00
0020 #define XGENET_CLKEN_ADDR       0x08
0021
0022 #define CSR_CLK     BIT(0)
0023 #define XGENET_CLK  BIT(1)
0024 #define PCS_CLK     BIT(3)
0025 #define AN_REF_CLK  BIT(4)
0026 #define AN_CLK      BIT(5)
0027 #define AD_CLK      BIT(6)
0028
0029 #define CSR_RST     BIT(0)
0030 #define XGENET_RST  BIT(1)
0031 #define PCS_RST     BIT(3)
0032 #define AN_REF_RST  BIT(4)
0033 #define AN_RST      BIT(5)
0034 #define AD_RST      BIT(6)
0035
0036 #define AXGMAC_CONFIG_0         0x0000
0037 #define AXGMAC_CONFIG_1         0x0004
0038 #define HSTMACRST           BIT(31)
0039 #define HSTTCTLEN           BIT(31)
0040 #define HSTTFEN             BIT(30)
0041 #define HSTRCTLEN           BIT(29)
0042 #define HSTRFEN             BIT(28)
0043 #define HSTPPEN             BIT(7)
0044 #define HSTDRPLT64          BIT(5)
0045 #define HSTLENCHK           BIT(3)
0046 #define HSTMACADR_LSW_ADDR      0x0010
0047 #define HSTMACADR_MSW_ADDR      0x0014
0048 #define HSTMAXFRAME_LENGTH_ADDR     0x0020
0049
0050 #define XG_MCX_RX_DV_GATE_REG_0_ADDR    0x0004
0051 #define XG_MCX_ECM_CFG_0_ADDR       0x0074
0052 #define XG_MCX_MULTI_DPF0_ADDR      0x007c
0053 #define XG_MCX_MULTI_DPF1_ADDR      0x0080
0054 #define XG_DEF_PAUSE_THRES      0x390
0055 #define XG_DEF_PAUSE_OFF_THRES      0x2c0
0056 #define XG_RSIF_CONFIG_REG_ADDR     0x00a0
0057 #define XG_RSIF_CLE_BUFF_THRESH                0x3
0058 #define RSIF_CLE_BUFF_THRESH_SET(dst, val)     xgene_set_bits(dst, val, 0, 3)
0059 #define XG_RSIF_CONFIG1_REG_ADDR       0x00b8
0060 #define XG_RSIF_PLC_CLE_BUFF_THRESH    0x1
0061 #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
0062 #define XG_MCX_ECM_CONFIG0_REG_0_ADDR          0x0070
0063 #define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR    0x0124
0064 #define XCLE_BYPASS_REG0_ADDR           0x0160
0065 #define XCLE_BYPASS_REG1_ADDR           0x0164
0066 #define XG_CFG_BYPASS_ADDR      0x0204
0067 #define XG_CFG_LINK_AGGR_RESUME_0_ADDR  0x0214
0068 #define XG_LINK_STATUS_ADDR     0x0228
0069 #define XG_TSIF_MSS_REG0_ADDR       0x02a4
0070 #define XG_DEBUG_REG_ADDR       0x0400
0071 #define XG_ENET_SPARE_CFG_REG_ADDR  0x040c
0072 #define XG_ENET_SPARE_CFG_REG_1_ADDR    0x0410
0073 #define XGENET_RX_DV_GATE_REG_0_ADDR    0x0804
0074 #define XGENET_ECM_CONFIG0_REG_0    0x0870
0075 #define XGENET_ICM_ECM_DROP_COUNT_REG0  0x0924
0076 #define XGENET_CSR_ECM_CFG_0_ADDR   0x0880
0077 #define XGENET_CSR_MULTI_DPF0_ADDR  0x0888
0078 #define XGENET_CSR_MULTI_DPF1_ADDR  0x088c
0079 #define XG_RXBUF_PAUSE_THRESH       0x0020
0080 #define XG_MCX_ICM_CONFIG0_REG_0_ADDR   0x00e0
0081 #define XG_MCX_ICM_CONFIG2_REG_0_ADDR   0x00e8
0082
0083 #define PCS_CONTROL_1           0x0000
0084 #define PCS_CTRL_PCS_RST        BIT(15)
0085
0086 extern const struct xgene_mac_ops xgene_xgmac_ops;
0087 extern const struct xgene_port_ops xgene_xgport_ops;
0088
0089 #endif /* __XGENE_ENET_XGMAC_H__ */