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0009 #ifndef __XGENE_ENET_SGMAC_H__
0010 #define __XGENE_ENET_SGMAC_H__
0011
0012 #define PHY_ADDR(src) (((src)<<8) & GENMASK(12, 8))
0013 #define REG_ADDR(src) ((src) & GENMASK(4, 0))
0014 #define PHY_CONTROL(src) ((src) & GENMASK(15, 0))
0015 #define LINK_SPEED(src) (((src) & GENMASK(11, 10)) >> 10)
0016 #define INT_PHY_ADDR 0x1e
0017 #define SGMII_TBI_CONTROL_ADDR 0x44
0018 #define SGMII_CONTROL_ADDR 0x00
0019 #define SGMII_STATUS_ADDR 0x04
0020 #define SGMII_BASE_PAGE_ABILITY_ADDR 0x14
0021 #define AUTO_NEG_COMPLETE BIT(5)
0022 #define LINK_STATUS BIT(2)
0023 #define LINK_UP BIT(15)
0024 #define MPA_IDLE_WITH_QMI_EMPTY BIT(12)
0025 #define SG_RX_DV_GATE_REG_0_ADDR 0x05fc
0026 #define SGMII_EN 0x1
0027
0028 enum xgene_phy_speed {
0029 PHY_SPEED_10,
0030 PHY_SPEED_100,
0031 PHY_SPEED_1000
0032 };
0033
0034 extern const struct xgene_mac_ops xgene_sgmac_ops;
0035 extern const struct xgene_port_ops xgene_sgport_ops;
0036
0037 #endif