apm/xgene/xgene_enet_main.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Applied Micro X-Gene SoC Ethernet Driver
0003  *
0004  * Copyright (c) 2014, Applied Micro Circuits Corporation
0005  * Authors: Iyappan Subramanian <isubramanian@apm.com>
0006  *      Ravi Patel <rapatel@apm.com>
0007  *      Keyur Chudgar <kchudgar@apm.com>
0008  */
0009
0010 #ifndef __XGENE_ENET_MAIN_H__
0011 #define __XGENE_ENET_MAIN_H__
0012
0013 #include <linux/acpi.h>
0014 #include <linux/clk.h>
0015 #include <linux/efi.h>
0016 #include <linux/irq.h>
0017 #include <linux/io.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/of_net.h>
0020 #include <linux/of_mdio.h>
0021 #include <linux/mdio/mdio-xgene.h>
0022 #include <linux/module.h>
0023 #include <net/ip.h>
0024 #include <linux/prefetch.h>
0025 #include <linux/if_vlan.h>
0026 #include <linux/phy.h>
0027 #include "xgene_enet_hw.h"
0028 #include "xgene_enet_cle.h"
0029 #include "xgene_enet_ring2.h"
0030
0031 #define ETHER_MIN_PACKET    64
0032 #define ETHER_STD_PACKET    1518
0033 #define XGENE_ENET_STD_MTU  1536
0034 #define XGENE_ENET_MAX_MTU  9600
0035 #define SKB_BUFFER_SIZE     (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
0036
0037 #define BUFLEN_16K  (16 * 1024)
0038 #define NUM_PKT_BUF 1024
0039 #define NUM_BUFPOOL 32
0040 #define NUM_NXTBUFPOOL  8
0041 #define MAX_EXP_BUFFS   256
0042 #define NUM_MSS_REG 4
0043 #define XGENE_MIN_ENET_FRAME_SIZE   60
0044
0045 #define XGENE_MAX_ENET_IRQ  16
0046 #define XGENE_NUM_RX_RING   8
0047 #define XGENE_NUM_TX_RING   8
0048 #define XGENE_NUM_TXC_RING  8
0049
0050 #define START_CPU_BUFNUM_0  0
0051 #define START_ETH_BUFNUM_0  2
0052 #define START_BP_BUFNUM_0   0x22
0053 #define START_RING_NUM_0    8
0054 #define START_CPU_BUFNUM_1  12
0055 #define START_ETH_BUFNUM_1  10
0056 #define START_BP_BUFNUM_1   0x2A
0057 #define START_RING_NUM_1    264
0058
0059 #define XG_START_CPU_BUFNUM_1   12
0060 #define XG_START_ETH_BUFNUM_1   2
0061 #define XG_START_BP_BUFNUM_1    0x22
0062 #define XG_START_RING_NUM_1 264
0063
0064 #define X2_START_CPU_BUFNUM_0   0
0065 #define X2_START_ETH_BUFNUM_0   0
0066 #define X2_START_BP_BUFNUM_0    0x20
0067 #define X2_START_RING_NUM_0 0
0068 #define X2_START_CPU_BUFNUM_1   0xc
0069 #define X2_START_ETH_BUFNUM_1   0
0070 #define X2_START_BP_BUFNUM_1    0x20
0071 #define X2_START_RING_NUM_1 256
0072
0073 #define IRQ_ID_SIZE     16
0074
0075 #define PHY_POLL_LINK_ON    (10 * HZ)
0076 #define PHY_POLL_LINK_OFF   (PHY_POLL_LINK_ON / 5)
0077
0078 enum xgene_enet_id {
0079     XGENE_ENET1 = 1,
0080     XGENE_ENET2
0081 };
0082
0083 enum xgene_enet_buf_len {
0084     SIZE_2K = 2048,
0085     SIZE_4K = 4096,
0086     SIZE_16K = 16384
0087 };
0088
0089 /* software context of a descriptor ring */
0090 struct xgene_enet_desc_ring {
0091     struct net_device *ndev;
0092     u16 id;
0093     u16 num;
0094     u16 head;
0095     u16 tail;
0096     u16 exp_buf_tail;
0097     u16 slots;
0098     u16 irq;
0099     char irq_name[IRQ_ID_SIZE];
0100     u32 size;
0101     u32 state[X2_NUM_RING_CONFIG];
0102     void __iomem *cmd_base;
0103     void __iomem *cmd;
0104     dma_addr_t dma;
0105     dma_addr_t irq_mbox_dma;
0106     void *irq_mbox_addr;
0107     u16 dst_ring_num;
0108     u16 nbufpool;
0109     int npagepool;
0110     u8 index;
0111     u32 flags;
0112     struct sk_buff *(*rx_skb);
0113     struct sk_buff *(*cp_skb);
0114     dma_addr_t *frag_dma_addr;
0115     struct page *(*frag_page);
0116     enum xgene_enet_ring_cfgsize cfgsize;
0117     struct xgene_enet_desc_ring *cp_ring;
0118     struct xgene_enet_desc_ring *buf_pool;
0119     struct xgene_enet_desc_ring *page_pool;
0120     struct napi_struct napi;
0121     union {
0122         void *desc_addr;
0123         struct xgene_enet_raw_desc *raw_desc;
0124         struct xgene_enet_raw_desc16 *raw_desc16;
0125     };
0126     __le64 *exp_bufs;
0127     u64 tx_packets;
0128     u64 tx_bytes;
0129     u64 tx_dropped;
0130     u64 tx_errors;
0131     u64 rx_packets;
0132     u64 rx_bytes;
0133     u64 rx_dropped;
0134     u64 rx_errors;
0135     u64 rx_length_errors;
0136     u64 rx_crc_errors;
0137     u64 rx_frame_errors;
0138     u64 rx_fifo_errors;
0139 };
0140
0141 struct xgene_mac_ops {
0142     void (*init)(struct xgene_enet_pdata *pdata);
0143     void (*reset)(struct xgene_enet_pdata *pdata);
0144     void (*tx_enable)(struct xgene_enet_pdata *pdata);
0145     void (*rx_enable)(struct xgene_enet_pdata *pdata);
0146     void (*tx_disable)(struct xgene_enet_pdata *pdata);
0147     void (*rx_disable)(struct xgene_enet_pdata *pdata);
0148     void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx);
0149     void (*set_speed)(struct xgene_enet_pdata *pdata);
0150     void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
0151     void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
0152     void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
0153     void (*link_state)(struct work_struct *work);
0154     void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable);
0155     void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable);
0156     void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable);
0157 };
0158
0159 struct xgene_port_ops {
0160     int (*reset)(struct xgene_enet_pdata *pdata);
0161     void (*clear)(struct xgene_enet_pdata *pdata,
0162               struct xgene_enet_desc_ring *ring);
0163     void (*cle_bypass)(struct xgene_enet_pdata *pdata,
0164                u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
0165     void (*shutdown)(struct xgene_enet_pdata *pdata);
0166 };
0167
0168 struct xgene_ring_ops {
0169     u8 num_ring_config;
0170     u8 num_ring_id_shift;
0171     struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
0172     void (*clear)(struct xgene_enet_desc_ring *);
0173     void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
0174     u32 (*len)(struct xgene_enet_desc_ring *);
0175     void (*coalesce)(struct xgene_enet_desc_ring *);
0176 };
0177
0178 struct xgene_cle_ops {
0179     int (*cle_init)(struct xgene_enet_pdata *pdata);
0180 };
0181
0182 /* ethernet private data */
0183 struct xgene_enet_pdata {
0184     struct net_device *ndev;
0185     struct mii_bus *mdio_bus;
0186     int phy_speed;
0187     struct clk *clk;
0188     struct platform_device *pdev;
0189     enum xgene_enet_id enet_id;
0190     struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
0191     struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
0192     u16 tx_level[XGENE_NUM_TX_RING];
0193     u16 txc_level[XGENE_NUM_TX_RING];
0194     char *dev_name;
0195     u32 rx_buff_cnt;
0196     u32 tx_qcnt_hi;
0197     u32 irqs[XGENE_MAX_ENET_IRQ];
0198     u8 rxq_cnt;
0199     u8 txq_cnt;
0200     u8 cq_cnt;
0201     void __iomem *eth_csr_addr;
0202     void __iomem *eth_ring_if_addr;
0203     void __iomem *eth_diag_csr_addr;
0204     void __iomem *mcx_mac_addr;
0205     void __iomem *mcx_mac_csr_addr;
0206     void __iomem *mcx_stats_addr;
0207     void __iomem *base_addr;
0208     void __iomem *pcs_addr;
0209     void __iomem *ring_csr_addr;
0210     void __iomem *ring_cmd_addr;
0211     int phy_mode;
0212     enum xgene_enet_rm rm;
0213     struct xgene_enet_cle cle;
0214     u64 *extd_stats;
0215     u64 false_rflr;
0216     u64 vlan_rjbr;
0217     spinlock_t stats_lock; /* statistics lock */
0218     const struct xgene_mac_ops *mac_ops;
0219     spinlock_t mac_lock; /* mac lock */
0220     const struct xgene_port_ops *port_ops;
0221     struct xgene_ring_ops *ring_ops;
0222     const struct xgene_cle_ops *cle_ops;
0223     struct delayed_work link_work;
0224     u32 port_id;
0225     u8 cpu_bufnum;
0226     u8 eth_bufnum;
0227     u8 bp_bufnum;
0228     u16 ring_num;
0229     u32 mss[NUM_MSS_REG];
0230     u32 mss_refcnt[NUM_MSS_REG];
0231     spinlock_t mss_lock;  /* mss lock */
0232     u8 tx_delay;
0233     u8 rx_delay;
0234     bool mdio_driver;
0235     struct gpio_desc *sfp_rdy;
0236     bool sfp_gpio_en;
0237     u32 pause_autoneg;
0238     bool tx_pause;
0239     bool rx_pause;
0240 };
0241
0242 struct xgene_indirect_ctl {
0243     void __iomem *addr;
0244     void __iomem *ctl;
0245     void __iomem *cmd;
0246     void __iomem *cmd_done;
0247 };
0248
0249 static inline struct device *ndev_to_dev(struct net_device *ndev)
0250 {
0251     return ndev->dev.parent;
0252 }
0253
0254 static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
0255 {
0256     struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
0257
0258     return ((u16)pdata->rm << 10) | ring->num;
0259 }
0260
0261 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
0262 int xgene_extd_stats_init(struct xgene_enet_pdata *pdata);
0263
0264 #endif /* __XGENE_ENET_MAIN_H__ */