apm/xgene/xgene_enet_cle.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Applied Micro X-Gene SoC Ethernet Classifier structures
0003  *
0004  * Copyright (c) 2016, Applied Micro Circuits Corporation
0005  * Authors: Khuong Dinh <kdinh@apm.com>
0006  *          Tanmay Inamdar <tinamdar@apm.com>
0007  *          Iyappan Subramanian <isubramanian@apm.com>
0008  */
0009
0010 #ifndef __XGENE_ENET_CLE_H__
0011 #define __XGENE_ENET_CLE_H__
0012
0013 #include <linux/io.h>
0014 #include <linux/random.h>
0015
0016 /* Register offsets */
0017 #define INDADDR         0x04
0018 #define INDCMD          0x08
0019 #define INDCMD_STATUS       0x0c
0020 #define DATA_RAM0       0x10
0021 #define SNPTR0          0x0100
0022 #define SPPTR0          0x0104
0023 #define DFCLSRESDBPTR0      0x0108
0024 #define DFCLSRESDB00        0x010c
0025 #define RSS_CTRL0       0x0000013c
0026
0027 #define CLE_CMD_TO      10  /* ms */
0028 #define CLE_PKTRAM_SIZE     256 /* bytes */
0029 #define CLE_PORT_OFFSET     0x200
0030 #define CLE_DRAM_REGS       17
0031
0032 #define CLE_DN_TYPE_LEN     2
0033 #define CLE_DN_TYPE_POS     0
0034 #define CLE_DN_LASTN_LEN    1
0035 #define CLE_DN_LASTN_POS    2
0036 #define CLE_DN_HLS_LEN      1
0037 #define CLE_DN_HLS_POS      3
0038 #define CLE_DN_EXT_LEN      2
0039 #define CLE_DN_EXT_POS      4
0040 #define CLE_DN_BSTOR_LEN    2
0041 #define CLE_DN_BSTOR_POS    6
0042 #define CLE_DN_SBSTOR_LEN   2
0043 #define CLE_DN_SBSTOR_POS   8
0044 #define CLE_DN_RPTR_LEN     12
0045 #define CLE_DN_RPTR_POS     12
0046
0047 #define CLE_BR_VALID_LEN    1
0048 #define CLE_BR_VALID_POS    0
0049 #define CLE_BR_NPPTR_LEN    9
0050 #define CLE_BR_NPPTR_POS    1
0051 #define CLE_BR_JB_LEN       1
0052 #define CLE_BR_JB_POS       10
0053 #define CLE_BR_JR_LEN       1
0054 #define CLE_BR_JR_POS       11
0055 #define CLE_BR_OP_LEN       3
0056 #define CLE_BR_OP_POS       12
0057 #define CLE_BR_NNODE_LEN    9
0058 #define CLE_BR_NNODE_POS    15
0059 #define CLE_BR_NBR_LEN      5
0060 #define CLE_BR_NBR_POS      24
0061
0062 #define CLE_BR_DATA_LEN     16
0063 #define CLE_BR_DATA_POS     0
0064 #define CLE_BR_MASK_LEN     16
0065 #define CLE_BR_MASK_POS     16
0066
0067 #define CLE_KN_PRIO_POS     0
0068 #define CLE_KN_PRIO_LEN     3
0069 #define CLE_KN_RPTR_POS     3
0070 #define CLE_KN_RPTR_LEN     10
0071 #define CLE_TYPE_POS        0
0072 #define CLE_TYPE_LEN        2
0073
0074 #define CLE_DROP_POS        28
0075 #define CLE_DROP_LEN        1
0076 #define CLE_DSTQIDL_POS     25
0077 #define CLE_DSTQIDL_LEN     7
0078 #define CLE_DSTQIDH_POS     0
0079 #define CLE_DSTQIDH_LEN     5
0080 #define CLE_FPSEL_POS       21
0081 #define CLE_FPSEL_LEN       4
0082 #define CLE_NFPSEL_POS      17
0083 #define CLE_NFPSEL_LEN      4
0084 #define CLE_PRIORITY_POS    5
0085 #define CLE_PRIORITY_LEN    3
0086
0087 #define JMP_ABS         0
0088 #define JMP_REL         1
0089 #define JMP_FW          0
0090 #define JMP_BW          1
0091
0092 enum xgene_cle_ptree_nodes {
0093     PKT_TYPE_NODE,
0094     PKT_PROT_NODE,
0095     RSS_IPV4_TCP_NODE,
0096     RSS_IPV4_UDP_NODE,
0097     RSS_IPV4_OTHERS_NODE,
0098     LAST_NODE,
0099     MAX_NODES
0100 };
0101
0102 enum xgene_cle_byte_store {
0103     NO_BYTE,
0104     FIRST_BYTE,
0105     SECOND_BYTE,
0106     BOTH_BYTES
0107 };
0108
0109 /* Preclassification operation types */
0110 enum xgene_cle_node_type {
0111     INV,
0112     KN,
0113     EWDN,
0114     RES_NODE
0115 };
0116
0117 /* Preclassification operation types */
0118 enum xgene_cle_op_type {
0119     EQT,
0120     NEQT,
0121     LTEQT,
0122     GTEQT,
0123     AND,
0124     NAND
0125 };
0126
0127 enum xgene_cle_parser {
0128     PARSER0,
0129     PARSER1,
0130     PARSER2,
0131     PARSER_ALL
0132 };
0133
0134 #define XGENE_CLE_DRAM(type)    (((type) & 0xf) << 28)
0135 enum xgene_cle_dram_type {
0136     PKT_RAM,
0137     RSS_IDT,
0138     RSS_IPV4_HASH_SKEY,
0139     PTREE_RAM = 0xc,
0140     AVL_RAM,
0141     DB_RAM
0142 };
0143
0144 enum xgene_cle_cmd_type {
0145     CLE_CMD_WR = 1,
0146     CLE_CMD_RD = 2,
0147     CLE_CMD_AVL_ADD = 8,
0148     CLE_CMD_AVL_DEL = 16,
0149     CLE_CMD_AVL_SRCH = 32
0150 };
0151
0152 enum xgene_cle_ipv4_rss_hashtype {
0153     RSS_IPV4_8B,
0154     RSS_IPV4_12B,
0155 };
0156
0157 enum xgene_cle_prot_type {
0158     XGENE_CLE_TCP,
0159     XGENE_CLE_UDP,
0160     XGENE_CLE_ESP,
0161     XGENE_CLE_OTHER
0162 };
0163
0164 enum xgene_cle_prot_version {
0165     XGENE_CLE_IPV4,
0166 };
0167
0168 enum xgene_cle_ptree_dbptrs {
0169     DB_RES_DROP,
0170     DB_RES_DEF,
0171     DB_RES_ACCEPT,
0172     DB_MAX_PTRS
0173 };
0174
0175 /* RSS sideband signal info */
0176 #define SB_IPFRAG_POS   0
0177 #define SB_IPFRAG_LEN   1
0178 #define SB_IPPROT_POS   1
0179 #define SB_IPPROT_LEN   2
0180 #define SB_IPVER_POS    3
0181 #define SB_IPVER_LEN    1
0182 #define SB_HDRLEN_POS   4
0183 #define SB_HDRLEN_LEN   12
0184
0185 /* RSS indirection table */
0186 #define XGENE_CLE_IDT_ENTRIES   128
0187 #define IDT_DSTQID_POS      0
0188 #define IDT_DSTQID_LEN      12
0189 #define IDT_FPSEL_POS       12
0190 #define IDT_FPSEL_LEN       5
0191 #define IDT_NFPSEL_POS      17
0192 #define IDT_NFPSEL_LEN      5
0193 #define IDT_FPSEL1_POS      12
0194 #define IDT_FPSEL1_LEN      4
0195 #define IDT_NFPSEL1_POS     16
0196 #define IDT_NFPSEL1_LEN     4
0197
0198 struct xgene_cle_ptree_branch {
0199     bool valid;
0200     u16 next_packet_pointer;
0201     bool jump_bw;
0202     bool jump_rel;
0203     u8 operation;
0204     u16 next_node;
0205     u8 next_branch;
0206     u16 data;
0207     u16 mask;
0208 };
0209
0210 struct xgene_cle_ptree_ewdn {
0211     u8 node_type;
0212     bool last_node;
0213     bool hdr_len_store;
0214     u8 hdr_extn;
0215     u8 byte_store;
0216     u8 search_byte_store;
0217     u16 result_pointer;
0218     u8 num_branches;
0219     struct xgene_cle_ptree_branch branch[6];
0220 };
0221
0222 struct xgene_cle_ptree_key {
0223     u8 priority;
0224     u16 result_pointer;
0225 };
0226
0227 struct xgene_cle_ptree_kn {
0228     u8 node_type;
0229     u8 num_keys;
0230     struct xgene_cle_ptree_key key[32];
0231 };
0232
0233 struct xgene_cle_dbptr {
0234     u8 split_boundary;
0235     u8 mirror_nxtfpsel;
0236     u8 mirror_fpsel;
0237     u16 mirror_dstqid;
0238     u8 drop;
0239     u8 mirror;
0240     u8 hdr_data_split;
0241     u64 hopinfomsbs;
0242     u8 DR;
0243     u8 HR;
0244     u64 hopinfomlsbs;
0245     u16 h0enq_num;
0246     u8 h0fpsel;
0247     u8 nxtfpsel;
0248     u8 fpsel;
0249     u16 dstqid;
0250     u8 cle_priority;
0251     u8 cle_flowgroup;
0252     u8 cle_perflow;
0253     u8 cle_insert_timestamp;
0254     u8 stash;
0255     u8 in;
0256     u8 perprioen;
0257     u8 perflowgroupen;
0258     u8 perflowen;
0259     u8 selhash;
0260     u8 selhdrext;
0261     u8 mirror_nxtfpsel_msb;
0262     u8 mirror_fpsel_msb;
0263     u8 hfpsel_msb;
0264     u8 nxtfpsel_msb;
0265     u8 fpsel_msb;
0266 };
0267
0268 struct xgene_cle_ptree {
0269     struct xgene_cle_ptree_kn *kn;
0270     struct xgene_cle_dbptr *dbptr;
0271     u32 num_kn;
0272     u32 num_dbptr;
0273     u32 start_node;
0274     u32 start_pkt;
0275     u32 start_dbptr;
0276 };
0277
0278 struct xgene_enet_cle {
0279     void __iomem *base;
0280     struct xgene_cle_ptree ptree;
0281     enum xgene_cle_parser active_parser;
0282     u32 parsers;
0283     u32 max_nodes;
0284     u32 max_dbptrs;
0285     u32 jump_bytes;
0286 };
0287
0288 extern const struct xgene_cle_ops xgene_cle3in_ops;
0289
0290 #endif /* __XGENE_ENET_CLE_H__ */