apm/xgene-v2/ring.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Applied Micro X-Gene SoC Ethernet v2 Driver
0004  *
0005  * Copyright (c) 2017, Applied Micro Circuits Corporation
0006  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
0007  *        Keyur Chudgar <kchudgar@apm.com>
0008  */
0009
0010 #ifndef __XGENE_ENET_V2_RING_H__
0011 #define __XGENE_ENET_V2_RING_H__
0012
0013 #define XGENE_ENET_DESC_SIZE    64
0014 #define XGENE_ENET_NUM_DESC 256
0015 #define NUM_BUFS        8
0016 #define SLOT_EMPTY      0xfff
0017
0018 #define DMATXCTRL       0xa180
0019 #define DMATXDESCL      0xa184
0020 #define DMATXDESCH      0xa1a0
0021 #define DMATXSTATUS     0xa188
0022 #define DMARXCTRL       0xa18c
0023 #define DMARXDESCL      0xa190
0024 #define DMARXDESCH      0xa1a4
0025 #define DMARXSTATUS     0xa194
0026 #define DMAINTRMASK     0xa198
0027 #define DMAINTERRUPT        0xa19c
0028
0029 #define D_POS           62
0030 #define D_LEN           2
0031 #define E_POS           63
0032 #define E_LEN           1
0033 #define PKT_ADDRL_POS       0
0034 #define PKT_ADDRL_LEN       32
0035 #define PKT_ADDRH_POS       32
0036 #define PKT_ADDRH_LEN       10
0037 #define PKT_SIZE_POS        32
0038 #define PKT_SIZE_LEN        12
0039 #define NEXT_DESC_ADDRL_POS 0
0040 #define NEXT_DESC_ADDRL_LEN 32
0041 #define NEXT_DESC_ADDRH_POS 48
0042 #define NEXT_DESC_ADDRH_LEN 10
0043
0044 #define TXPKTCOUNT_POS      16
0045 #define TXPKTCOUNT_LEN      8
0046 #define RXPKTCOUNT_POS      16
0047 #define RXPKTCOUNT_LEN      8
0048
0049 #define TX_PKT_SENT     BIT(0)
0050 #define TX_BUS_ERROR        BIT(3)
0051 #define RX_PKT_RCVD     BIT(4)
0052 #define RX_BUS_ERROR        BIT(7)
0053 #define RXSTATUS_RXPKTRCVD  BIT(0)
0054
0055 struct xge_raw_desc {
0056     __le64 m0;
0057     __le64 m1;
0058     __le64 m2;
0059     __le64 m3;
0060     __le64 m4;
0061     __le64 m5;
0062     __le64 m6;
0063     __le64 m7;
0064 };
0065
0066 struct pkt_info {
0067     struct sk_buff *skb;
0068     dma_addr_t dma_addr;
0069     void *pkt_buf;
0070 };
0071
0072 /* software context of a descriptor ring */
0073 struct xge_desc_ring {
0074     struct net_device *ndev;
0075     dma_addr_t dma_addr;
0076     u8 head;
0077     u8 tail;
0078     union {
0079         void *desc_addr;
0080         struct xge_raw_desc *raw_desc;
0081     };
0082     struct pkt_info (*pkt_info);
0083 };
0084
0085 static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
0086 {
0087     return (val & ((1ULL << len) - 1)) << pos;
0088 }
0089
0090 static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
0091 {
0092     return (src >> pos) & ((1ULL << len) - 1);
0093 }
0094
0095 #define SET_BITS(field, val) \
0096         xge_set_desc_bits(field ## _POS, field ## _LEN, val)
0097
0098 #define GET_BITS(field, src) \
0099         xge_get_desc_bits(field ## _POS, field ## _LEN, src)
0100
0101 void xge_setup_desc(struct xge_desc_ring *ring);
0102 void xge_update_tx_desc_addr(struct xge_pdata *pdata);
0103 void xge_update_rx_desc_addr(struct xge_pdata *pdata);
0104 void xge_intr_enable(struct xge_pdata *pdata);
0105 void xge_intr_disable(struct xge_pdata *pdata);
0106
0107 #endif  /* __XGENE_ENET_V2_RING_H__ */