apm/xgene-v2/mac.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Applied Micro X-Gene SoC Ethernet v2 Driver
0004  *
0005  * Copyright (c) 2017, Applied Micro Circuits Corporation
0006  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
0007  *        Keyur Chudgar <kchudgar@apm.com>
0008  */
0009
0010 #ifndef __XGENE_ENET_V2_MAC_H__
0011 #define __XGENE_ENET_V2_MAC_H__
0012
0013 /* Register offsets */
0014 #define MAC_CONFIG_1        0xa000
0015 #define MAC_CONFIG_2        0xa004
0016 #define MII_MGMT_CONFIG     0xa020
0017 #define MII_MGMT_COMMAND    0xa024
0018 #define MII_MGMT_ADDRESS    0xa028
0019 #define MII_MGMT_CONTROL    0xa02c
0020 #define MII_MGMT_STATUS     0xa030
0021 #define MII_MGMT_INDICATORS 0xa034
0022 #define INTERFACE_CONTROL   0xa038
0023 #define STATION_ADDR0       0xa040
0024 #define STATION_ADDR1       0xa044
0025
0026 #define RGMII_REG_0     0x27e0
0027 #define ICM_CONFIG0_REG_0   0x2c00
0028 #define ICM_CONFIG2_REG_0   0x2c08
0029 #define ECM_CONFIG0_REG_0   0x2d00
0030
0031 /* Register fields */
0032 #define SOFT_RESET      BIT(31)
0033 #define TX_EN           BIT(0)
0034 #define RX_EN           BIT(2)
0035 #define PAD_CRC         BIT(2)
0036 #define CRC_EN          BIT(1)
0037 #define FULL_DUPLEX     BIT(0)
0038
0039 #define INTF_MODE_POS       8
0040 #define INTF_MODE_LEN       2
0041 #define HD_MODE_POS     25
0042 #define HD_MODE_LEN     2
0043 #define CFG_MACMODE_POS     18
0044 #define CFG_MACMODE_LEN     2
0045 #define CFG_WAITASYNCRD_POS 0
0046 #define CFG_WAITASYNCRD_LEN 16
0047 #define CFG_SPEED_125_POS   24
0048 #define CFG_WFIFOFULLTHR_POS    0
0049 #define CFG_WFIFOFULLTHR_LEN    7
0050 #define MGMT_CLOCK_SEL_POS  0
0051 #define MGMT_CLOCK_SEL_LEN  3
0052 #define PHY_ADDR_POS        8
0053 #define PHY_ADDR_LEN        5
0054 #define REG_ADDR_POS        0
0055 #define REG_ADDR_LEN        5
0056 #define MII_MGMT_BUSY       BIT(0)
0057 #define MII_READ_CYCLE      BIT(0)
0058 #define CFG_WAITASYNCRD_EN  BIT(16)
0059
0060 static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
0061 {
0062     u32 mask = GENMASK(pos + len, pos);
0063
0064     *var &= ~mask;
0065     *var |= ((val << pos) & mask);
0066 }
0067
0068 static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
0069 {
0070     u32 mask = GENMASK(pos + len, pos);
0071
0072     return (var & mask) >> pos;
0073 }
0074
0075 #define SET_REG_BITS(var, field, val)                   \
0076     xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
0077
0078 #define SET_REG_BIT(var, field, val)                    \
0079     xgene_set_reg_bits(var, field ## _POS, 1, val)
0080
0081 #define GET_REG_BITS(var, field)                    \
0082     xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
0083
0084 #define GET_REG_BIT(var, field)     ((var) & (field))
0085
0086 struct xge_pdata;
0087
0088 void xge_mac_reset(struct xge_pdata *pdata);
0089 void xge_mac_set_speed(struct xge_pdata *pdata);
0090 void xge_mac_enable(struct xge_pdata *pdata);
0091 void xge_mac_disable(struct xge_pdata *pdata);
0092 void xge_mac_init(struct xge_pdata *pdata);
0093 void xge_mac_set_station_addr(struct xge_pdata *pdata);
0094
0095 #endif /* __XGENE_ENET_V2_MAC_H__ */