apm/xgene-v2/mac.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Applied Micro X-Gene SoC Ethernet v2 Driver
0004  *
0005  * Copyright (c) 2017, Applied Micro Circuits Corporation
0006  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
0007  *        Keyur Chudgar <kchudgar@apm.com>
0008  */
0009
0010 #include "main.h"
0011
0012 void xge_mac_reset(struct xge_pdata *pdata)
0013 {
0014     xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET);
0015     xge_wr_csr(pdata, MAC_CONFIG_1, 0);
0016 }
0017
0018 void xge_mac_set_speed(struct xge_pdata *pdata)
0019 {
0020     u32 icm0, icm2, ecm0, mc2;
0021     u32 intf_ctrl, rgmii;
0022
0023     icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
0024     icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
0025     ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
0026     rgmii = xge_rd_csr(pdata, RGMII_REG_0);
0027     mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
0028     intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
0029     icm2 |= CFG_WAITASYNCRD_EN;
0030
0031     switch (pdata->phy_speed) {
0032     case SPEED_10:
0033         SET_REG_BITS(&mc2, INTF_MODE, 1);
0034         SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
0035         SET_REG_BITS(&icm0, CFG_MACMODE, 0);
0036         SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
0037         SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
0038         break;
0039     case SPEED_100:
0040         SET_REG_BITS(&mc2, INTF_MODE, 1);
0041         SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
0042         SET_REG_BITS(&icm0, CFG_MACMODE, 1);
0043         SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
0044         SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
0045         break;
0046     default:
0047         SET_REG_BITS(&mc2, INTF_MODE, 2);
0048         SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
0049         SET_REG_BITS(&icm0, CFG_MACMODE, 2);
0050         SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
0051         SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
0052         break;
0053     }
0054
0055     mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
0056     SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
0057
0058     xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
0059     xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
0060     xge_wr_csr(pdata, RGMII_REG_0, rgmii);
0061     xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
0062     xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
0063     xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
0064 }
0065
0066 void xge_mac_set_station_addr(struct xge_pdata *pdata)
0067 {
0068     const u8 *dev_addr = pdata->ndev->dev_addr;
0069     u32 addr0, addr1;
0070
0071     addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
0072         (dev_addr[1] << 8) | dev_addr[0];
0073     addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
0074
0075     xge_wr_csr(pdata, STATION_ADDR0, addr0);
0076     xge_wr_csr(pdata, STATION_ADDR1, addr1);
0077 }
0078
0079 void xge_mac_init(struct xge_pdata *pdata)
0080 {
0081     xge_mac_reset(pdata);
0082     xge_mac_set_speed(pdata);
0083     xge_mac_set_station_addr(pdata);
0084 }
0085
0086 void xge_mac_enable(struct xge_pdata *pdata)
0087 {
0088     u32 data;
0089
0090     data = xge_rd_csr(pdata, MAC_CONFIG_1);
0091     data |= TX_EN | RX_EN;
0092     xge_wr_csr(pdata, MAC_CONFIG_1, data);
0093
0094     data = xge_rd_csr(pdata, MAC_CONFIG_1);
0095 }
0096
0097 void xge_mac_disable(struct xge_pdata *pdata)
0098 {
0099     u32 data;
0100
0101     data = xge_rd_csr(pdata, MAC_CONFIG_1);
0102     data &= ~(TX_EN | RX_EN);
0103     xge_wr_csr(pdata, MAC_CONFIG_1, data);
0104 }