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0010 #include "main.h"
0011
0012 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val)
0013 {
0014 void __iomem *addr = pdata->resources.base_addr + offset;
0015
0016 iowrite32(val, addr);
0017 }
0018
0019 u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset)
0020 {
0021 void __iomem *addr = pdata->resources.base_addr + offset;
0022
0023 return ioread32(addr);
0024 }
0025
0026 int xge_port_reset(struct net_device *ndev)
0027 {
0028 struct xge_pdata *pdata = netdev_priv(ndev);
0029 struct device *dev = &pdata->pdev->dev;
0030 u32 data, wait = 10;
0031
0032 xge_wr_csr(pdata, ENET_CLKEN, 0x3);
0033 xge_wr_csr(pdata, ENET_SRST, 0xf);
0034 xge_wr_csr(pdata, ENET_SRST, 0);
0035 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 1);
0036 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 0);
0037
0038 do {
0039 usleep_range(100, 110);
0040 data = xge_rd_csr(pdata, BLOCK_MEM_RDY);
0041 } while (data != MEM_RDY && wait--);
0042
0043 if (data != MEM_RDY) {
0044 dev_err(dev, "ECC init failed: %x\n", data);
0045 return -ETIMEDOUT;
0046 }
0047
0048 xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH);
0049
0050 return 0;
0051 }
0052
0053 static void xge_traffic_resume(struct net_device *ndev)
0054 {
0055 struct xge_pdata *pdata = netdev_priv(ndev);
0056
0057 xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1);
0058 xge_wr_csr(pdata, FORCE_LINK_STATUS, 1);
0059
0060 xge_wr_csr(pdata, CFG_LINK_AGGR_RESUME, 1);
0061 xge_wr_csr(pdata, RX_DV_GATE_REG, 1);
0062 }
0063
0064 void xge_port_init(struct net_device *ndev)
0065 {
0066 struct xge_pdata *pdata = netdev_priv(ndev);
0067
0068 pdata->phy_speed = SPEED_1000;
0069 xge_mac_init(pdata);
0070 xge_traffic_resume(ndev);
0071 }