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0001 /*
0002  * AMD 10Gb Ethernet driver
0003  *
0004  * This file is available to you under your choice of the following two
0005  * licenses:
0006  *
0007  * License 1: GPLv2
0008  *
0009  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
0010  *
0011  * This file is free software; you may copy, redistribute and/or modify
0012  * it under the terms of the GNU General Public License as published by
0013  * the Free Software Foundation, either version 2 of the License, or (at
0014  * your option) any later version.
0015  *
0016  * This file is distributed in the hope that it will be useful, but
0017  * WITHOUT ANY WARRANTY; without even the implied warranty of
0018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
0019  * General Public License for more details.
0020  *
0021  * You should have received a copy of the GNU General Public License
0022  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
0023  *
0024  * This file incorporates work covered by the following copyright and
0025  * permission notice:
0026  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
0027  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
0028  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
0029  *     and you.
0030  *
0031  *     The Software IS NOT an item of Licensed Software or Licensed Product
0032  *     under any End User Software License Agreement or Agreement for Licensed
0033  *     Product with Synopsys or any supplement thereto.  Permission is hereby
0034  *     granted, free of charge, to any person obtaining a copy of this software
0035  *     annotated with this license and the Software, to deal in the Software
0036  *     without restriction, including without limitation the rights to use,
0037  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
0038  *     of the Software, and to permit persons to whom the Software is furnished
0039  *     to do so, subject to the following conditions:
0040  *
0041  *     The above copyright notice and this permission notice shall be included
0042  *     in all copies or substantial portions of the Software.
0043  *
0044  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
0045  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0046  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0047  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
0048  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0049  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0050  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0051  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0052  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0053  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
0054  *     THE POSSIBILITY OF SUCH DAMAGE.
0055  *
0056  *
0057  * License 2: Modified BSD
0058  *
0059  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
0060  * All rights reserved.
0061  *
0062  * Redistribution and use in source and binary forms, with or without
0063  * modification, are permitted provided that the following conditions are met:
0064  *     * Redistributions of source code must retain the above copyright
0065  *       notice, this list of conditions and the following disclaimer.
0066  *     * Redistributions in binary form must reproduce the above copyright
0067  *       notice, this list of conditions and the following disclaimer in the
0068  *       documentation and/or other materials provided with the distribution.
0069  *     * Neither the name of Advanced Micro Devices, Inc. nor the
0070  *       names of its contributors may be used to endorse or promote products
0071  *       derived from this software without specific prior written permission.
0072  *
0073  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0074  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0075  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0076  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
0077  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0078  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0079  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0080  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0081  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0082  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0083  *
0084  * This file incorporates work covered by the following copyright and
0085  * permission notice:
0086  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
0087  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
0088  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
0089  *     and you.
0090  *
0091  *     The Software IS NOT an item of Licensed Software or Licensed Product
0092  *     under any End User Software License Agreement or Agreement for Licensed
0093  *     Product with Synopsys or any supplement thereto.  Permission is hereby
0094  *     granted, free of charge, to any person obtaining a copy of this software
0095  *     annotated with this license and the Software, to deal in the Software
0096  *     without restriction, including without limitation the rights to use,
0097  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
0098  *     of the Software, and to permit persons to whom the Software is furnished
0099  *     to do so, subject to the following conditions:
0100  *
0101  *     The above copyright notice and this permission notice shall be included
0102  *     in all copies or substantial portions of the Software.
0103  *
0104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
0105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
0108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
0114  *     THE POSSIBILITY OF SUCH DAMAGE.
0115  */
0116 
0117 #include <linux/interrupt.h>
0118 #include <linux/module.h>
0119 #include <linux/kmod.h>
0120 #include <linux/mdio.h>
0121 #include <linux/phy.h>
0122 #include <linux/of.h>
0123 #include <linux/bitops.h>
0124 #include <linux/jiffies.h>
0125 
0126 #include "xgbe.h"
0127 #include "xgbe-common.h"
0128 
0129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
0130                   struct ethtool_eeprom *eeprom, u8 *data)
0131 {
0132     if (!pdata->phy_if.phy_impl.module_eeprom)
0133         return -ENXIO;
0134 
0135     return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
0136 }
0137 
0138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
0139                 struct ethtool_modinfo *modinfo)
0140 {
0141     if (!pdata->phy_if.phy_impl.module_info)
0142         return -ENXIO;
0143 
0144     return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
0145 }
0146 
0147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
0148 {
0149     int reg;
0150 
0151     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
0152     reg &= ~XGBE_AN_CL37_INT_MASK;
0153     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
0154 }
0155 
0156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
0157 {
0158     int reg;
0159 
0160     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
0161     reg &= ~XGBE_AN_CL37_INT_MASK;
0162     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
0163 
0164     reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
0165     reg &= ~XGBE_PCS_CL37_BP;
0166     XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
0167 }
0168 
0169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
0170 {
0171     int reg;
0172 
0173     reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
0174     reg |= XGBE_PCS_CL37_BP;
0175     XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
0176 
0177     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
0178     reg |= XGBE_AN_CL37_INT_MASK;
0179     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
0180 }
0181 
0182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
0183 {
0184     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
0185 }
0186 
0187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
0188 {
0189     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
0190 }
0191 
0192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
0193 {
0194     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
0195 }
0196 
0197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
0198 {
0199     switch (pdata->an_mode) {
0200     case XGBE_AN_MODE_CL73:
0201     case XGBE_AN_MODE_CL73_REDRV:
0202         xgbe_an73_enable_interrupts(pdata);
0203         break;
0204     case XGBE_AN_MODE_CL37:
0205     case XGBE_AN_MODE_CL37_SGMII:
0206         xgbe_an37_enable_interrupts(pdata);
0207         break;
0208     default:
0209         break;
0210     }
0211 }
0212 
0213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
0214 {
0215     xgbe_an73_clear_interrupts(pdata);
0216     xgbe_an37_clear_interrupts(pdata);
0217 }
0218 
0219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
0220 {
0221     /* Set MAC to 10G speed */
0222     pdata->hw_if.set_speed(pdata, SPEED_10000);
0223 
0224     /* Call PHY implementation support to complete rate change */
0225     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
0226 }
0227 
0228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
0229 {
0230     /* Set MAC to 2.5G speed */
0231     pdata->hw_if.set_speed(pdata, SPEED_2500);
0232 
0233     /* Call PHY implementation support to complete rate change */
0234     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
0235 }
0236 
0237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
0238 {
0239     /* Set MAC to 1G speed */
0240     pdata->hw_if.set_speed(pdata, SPEED_1000);
0241 
0242     /* Call PHY implementation support to complete rate change */
0243     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
0244 }
0245 
0246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
0247 {
0248     /* If a KR re-driver is present, change to KR mode instead */
0249     if (pdata->kr_redrv)
0250         return xgbe_kr_mode(pdata);
0251 
0252     /* Set MAC to 10G speed */
0253     pdata->hw_if.set_speed(pdata, SPEED_10000);
0254 
0255     /* Call PHY implementation support to complete rate change */
0256     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
0257 }
0258 
0259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
0260 {
0261     /* Set MAC to 1G speed */
0262     pdata->hw_if.set_speed(pdata, SPEED_1000);
0263 
0264     /* Call PHY implementation support to complete rate change */
0265     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
0266 }
0267 
0268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
0269 {
0270     /* Set MAC to 1G speed */
0271     pdata->hw_if.set_speed(pdata, SPEED_1000);
0272 
0273     /* Call PHY implementation support to complete rate change */
0274     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
0275 }
0276 
0277 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
0278 {
0279     /* Set MAC to 1G speed */
0280     pdata->hw_if.set_speed(pdata, SPEED_1000);
0281 
0282     /* Call PHY implementation support to complete rate change */
0283     pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
0284 }
0285 
0286 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
0287 {
0288     return pdata->phy_if.phy_impl.cur_mode(pdata);
0289 }
0290 
0291 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
0292 {
0293     return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
0294 }
0295 
0296 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
0297                  enum xgbe_mode mode)
0298 {
0299     switch (mode) {
0300     case XGBE_MODE_KX_1000:
0301         xgbe_kx_1000_mode(pdata);
0302         break;
0303     case XGBE_MODE_KX_2500:
0304         xgbe_kx_2500_mode(pdata);
0305         break;
0306     case XGBE_MODE_KR:
0307         xgbe_kr_mode(pdata);
0308         break;
0309     case XGBE_MODE_SGMII_100:
0310         xgbe_sgmii_100_mode(pdata);
0311         break;
0312     case XGBE_MODE_SGMII_1000:
0313         xgbe_sgmii_1000_mode(pdata);
0314         break;
0315     case XGBE_MODE_X:
0316         xgbe_x_mode(pdata);
0317         break;
0318     case XGBE_MODE_SFI:
0319         xgbe_sfi_mode(pdata);
0320         break;
0321     case XGBE_MODE_UNKNOWN:
0322         break;
0323     default:
0324         netif_dbg(pdata, link, pdata->netdev,
0325               "invalid operation mode requested (%u)\n", mode);
0326     }
0327 }
0328 
0329 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
0330 {
0331     xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
0332 }
0333 
0334 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
0335               enum xgbe_mode mode)
0336 {
0337     if (mode == xgbe_cur_mode(pdata))
0338         return false;
0339 
0340     xgbe_change_mode(pdata, mode);
0341 
0342     return true;
0343 }
0344 
0345 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
0346               enum xgbe_mode mode)
0347 {
0348     return pdata->phy_if.phy_impl.use_mode(pdata, mode);
0349 }
0350 
0351 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
0352               bool restart)
0353 {
0354     unsigned int reg;
0355 
0356     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
0357     reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
0358 
0359     if (enable)
0360         reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
0361 
0362     if (restart)
0363         reg |= MDIO_VEND2_CTRL1_AN_RESTART;
0364 
0365     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
0366 }
0367 
0368 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
0369 {
0370     xgbe_an37_enable_interrupts(pdata);
0371     xgbe_an37_set(pdata, true, true);
0372 
0373     netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
0374 }
0375 
0376 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
0377 {
0378     xgbe_an37_set(pdata, false, false);
0379     xgbe_an37_disable_interrupts(pdata);
0380 
0381     netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
0382 }
0383 
0384 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
0385               bool restart)
0386 {
0387     unsigned int reg;
0388 
0389     /* Disable KR training for now */
0390     reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
0391     reg &= ~XGBE_KR_TRAINING_ENABLE;
0392     XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
0393 
0394     /* Update AN settings */
0395     reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
0396     reg &= ~MDIO_AN_CTRL1_ENABLE;
0397 
0398     if (enable)
0399         reg |= MDIO_AN_CTRL1_ENABLE;
0400 
0401     if (restart)
0402         reg |= MDIO_AN_CTRL1_RESTART;
0403 
0404     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
0405 }
0406 
0407 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
0408 {
0409     xgbe_an73_enable_interrupts(pdata);
0410     xgbe_an73_set(pdata, true, true);
0411 
0412     netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
0413 }
0414 
0415 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
0416 {
0417     xgbe_an73_set(pdata, false, false);
0418     xgbe_an73_disable_interrupts(pdata);
0419 
0420     pdata->an_start = 0;
0421 
0422     netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
0423 }
0424 
0425 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
0426 {
0427     if (pdata->phy_if.phy_impl.an_pre)
0428         pdata->phy_if.phy_impl.an_pre(pdata);
0429 
0430     switch (pdata->an_mode) {
0431     case XGBE_AN_MODE_CL73:
0432     case XGBE_AN_MODE_CL73_REDRV:
0433         xgbe_an73_restart(pdata);
0434         break;
0435     case XGBE_AN_MODE_CL37:
0436     case XGBE_AN_MODE_CL37_SGMII:
0437         xgbe_an37_restart(pdata);
0438         break;
0439     default:
0440         break;
0441     }
0442 }
0443 
0444 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
0445 {
0446     if (pdata->phy_if.phy_impl.an_post)
0447         pdata->phy_if.phy_impl.an_post(pdata);
0448 
0449     switch (pdata->an_mode) {
0450     case XGBE_AN_MODE_CL73:
0451     case XGBE_AN_MODE_CL73_REDRV:
0452         xgbe_an73_disable(pdata);
0453         break;
0454     case XGBE_AN_MODE_CL37:
0455     case XGBE_AN_MODE_CL37_SGMII:
0456         xgbe_an37_disable(pdata);
0457         break;
0458     default:
0459         break;
0460     }
0461 }
0462 
0463 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
0464 {
0465     xgbe_an73_disable(pdata);
0466     xgbe_an37_disable(pdata);
0467 }
0468 
0469 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
0470                       enum xgbe_rx *state)
0471 {
0472     unsigned int ad_reg, lp_reg, reg;
0473 
0474     *state = XGBE_RX_COMPLETE;
0475 
0476     /* If we're not in KR mode then we're done */
0477     if (!xgbe_in_kr_mode(pdata))
0478         return XGBE_AN_PAGE_RECEIVED;
0479 
0480     /* Enable/Disable FEC */
0481     ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
0482     lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
0483 
0484     reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
0485     reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
0486     if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
0487         reg |= pdata->fec_ability;
0488 
0489     XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
0490 
0491     /* Start KR training */
0492     if (pdata->phy_if.phy_impl.kr_training_pre)
0493         pdata->phy_if.phy_impl.kr_training_pre(pdata);
0494 
0495     reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
0496     reg |= XGBE_KR_TRAINING_ENABLE;
0497     reg |= XGBE_KR_TRAINING_START;
0498     XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
0499 
0500     netif_dbg(pdata, link, pdata->netdev,
0501           "KR training initiated\n");
0502 
0503     if (pdata->phy_if.phy_impl.kr_training_post)
0504         pdata->phy_if.phy_impl.kr_training_post(pdata);
0505 
0506     return XGBE_AN_PAGE_RECEIVED;
0507 }
0508 
0509 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
0510                      enum xgbe_rx *state)
0511 {
0512     u16 msg;
0513 
0514     *state = XGBE_RX_XNP;
0515 
0516     msg = XGBE_XNP_MCF_NULL_MESSAGE;
0517     msg |= XGBE_XNP_MP_FORMATTED;
0518 
0519     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
0520     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
0521     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
0522 
0523     return XGBE_AN_PAGE_RECEIVED;
0524 }
0525 
0526 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
0527                      enum xgbe_rx *state)
0528 {
0529     unsigned int link_support;
0530     unsigned int reg, ad_reg, lp_reg;
0531 
0532     /* Read Base Ability register 2 first */
0533     reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
0534 
0535     /* Check for a supported mode, otherwise restart in a different one */
0536     link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
0537     if (!(reg & link_support))
0538         return XGBE_AN_INCOMPAT_LINK;
0539 
0540     /* Check Extended Next Page support */
0541     ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
0542     lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
0543 
0544     return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
0545         (lp_reg & XGBE_XNP_NP_EXCHANGE))
0546            ? xgbe_an73_tx_xnp(pdata, state)
0547            : xgbe_an73_tx_training(pdata, state);
0548 }
0549 
0550 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
0551                      enum xgbe_rx *state)
0552 {
0553     unsigned int ad_reg, lp_reg;
0554 
0555     /* Check Extended Next Page support */
0556     ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
0557     lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
0558 
0559     return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
0560         (lp_reg & XGBE_XNP_NP_EXCHANGE))
0561            ? xgbe_an73_tx_xnp(pdata, state)
0562            : xgbe_an73_tx_training(pdata, state);
0563 }
0564 
0565 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
0566 {
0567     enum xgbe_rx *state;
0568     unsigned long an_timeout;
0569     enum xgbe_an ret;
0570 
0571     if (!pdata->an_start) {
0572         pdata->an_start = jiffies;
0573     } else {
0574         an_timeout = pdata->an_start +
0575                  msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
0576         if (time_after(jiffies, an_timeout)) {
0577             /* Auto-negotiation timed out, reset state */
0578             pdata->kr_state = XGBE_RX_BPA;
0579             pdata->kx_state = XGBE_RX_BPA;
0580 
0581             pdata->an_start = jiffies;
0582 
0583             netif_dbg(pdata, link, pdata->netdev,
0584                   "CL73 AN timed out, resetting state\n");
0585         }
0586     }
0587 
0588     state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
0589                        : &pdata->kx_state;
0590 
0591     switch (*state) {
0592     case XGBE_RX_BPA:
0593         ret = xgbe_an73_rx_bpa(pdata, state);
0594         break;
0595 
0596     case XGBE_RX_XNP:
0597         ret = xgbe_an73_rx_xnp(pdata, state);
0598         break;
0599 
0600     default:
0601         ret = XGBE_AN_ERROR;
0602     }
0603 
0604     return ret;
0605 }
0606 
0607 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
0608 {
0609     struct ethtool_link_ksettings *lks = &pdata->phy.lks;
0610 
0611     /* Be sure we aren't looping trying to negotiate */
0612     if (xgbe_in_kr_mode(pdata)) {
0613         pdata->kr_state = XGBE_RX_ERROR;
0614 
0615         if (!XGBE_ADV(lks, 1000baseKX_Full) &&
0616             !XGBE_ADV(lks, 2500baseX_Full))
0617             return XGBE_AN_NO_LINK;
0618 
0619         if (pdata->kx_state != XGBE_RX_BPA)
0620             return XGBE_AN_NO_LINK;
0621     } else {
0622         pdata->kx_state = XGBE_RX_ERROR;
0623 
0624         if (!XGBE_ADV(lks, 10000baseKR_Full))
0625             return XGBE_AN_NO_LINK;
0626 
0627         if (pdata->kr_state != XGBE_RX_BPA)
0628             return XGBE_AN_NO_LINK;
0629     }
0630 
0631     xgbe_an_disable(pdata);
0632 
0633     xgbe_switch_mode(pdata);
0634 
0635     xgbe_an_restart(pdata);
0636 
0637     return XGBE_AN_INCOMPAT_LINK;
0638 }
0639 
0640 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
0641 {
0642     unsigned int reg;
0643 
0644     /* Disable AN interrupts */
0645     xgbe_an37_disable_interrupts(pdata);
0646 
0647     /* Save the interrupt(s) that fired */
0648     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
0649     pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
0650     pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
0651 
0652     if (pdata->an_int) {
0653         /* Clear the interrupt(s) that fired and process them */
0654         reg &= ~XGBE_AN_CL37_INT_MASK;
0655         XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
0656 
0657         queue_work(pdata->an_workqueue, &pdata->an_irq_work);
0658     } else {
0659         /* Enable AN interrupts */
0660         xgbe_an37_enable_interrupts(pdata);
0661 
0662         /* Reissue interrupt if status is not clear */
0663         if (pdata->vdata->irq_reissue_support)
0664             XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
0665     }
0666 }
0667 
0668 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
0669 {
0670     /* Disable AN interrupts */
0671     xgbe_an73_disable_interrupts(pdata);
0672 
0673     /* Save the interrupt(s) that fired */
0674     pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
0675 
0676     if (pdata->an_int) {
0677         /* Clear the interrupt(s) that fired and process them */
0678         XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
0679 
0680         queue_work(pdata->an_workqueue, &pdata->an_irq_work);
0681     } else {
0682         /* Enable AN interrupts */
0683         xgbe_an73_enable_interrupts(pdata);
0684 
0685         /* Reissue interrupt if status is not clear */
0686         if (pdata->vdata->irq_reissue_support)
0687             XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
0688     }
0689 }
0690 
0691 static void xgbe_an_isr_task(struct tasklet_struct *t)
0692 {
0693     struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an);
0694 
0695     netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
0696 
0697     switch (pdata->an_mode) {
0698     case XGBE_AN_MODE_CL73:
0699     case XGBE_AN_MODE_CL73_REDRV:
0700         xgbe_an73_isr(pdata);
0701         break;
0702     case XGBE_AN_MODE_CL37:
0703     case XGBE_AN_MODE_CL37_SGMII:
0704         xgbe_an37_isr(pdata);
0705         break;
0706     default:
0707         break;
0708     }
0709 }
0710 
0711 static irqreturn_t xgbe_an_isr(int irq, void *data)
0712 {
0713     struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
0714 
0715     if (pdata->isr_as_tasklet)
0716         tasklet_schedule(&pdata->tasklet_an);
0717     else
0718         xgbe_an_isr_task(&pdata->tasklet_an);
0719 
0720     return IRQ_HANDLED;
0721 }
0722 
0723 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
0724 {
0725     xgbe_an_isr_task(&pdata->tasklet_an);
0726 
0727     return IRQ_HANDLED;
0728 }
0729 
0730 static void xgbe_an_irq_work(struct work_struct *work)
0731 {
0732     struct xgbe_prv_data *pdata = container_of(work,
0733                            struct xgbe_prv_data,
0734                            an_irq_work);
0735 
0736     /* Avoid a race between enabling the IRQ and exiting the work by
0737      * waiting for the work to finish and then queueing it
0738      */
0739     flush_work(&pdata->an_work);
0740     queue_work(pdata->an_workqueue, &pdata->an_work);
0741 }
0742 
0743 static const char *xgbe_state_as_string(enum xgbe_an state)
0744 {
0745     switch (state) {
0746     case XGBE_AN_READY:
0747         return "Ready";
0748     case XGBE_AN_PAGE_RECEIVED:
0749         return "Page-Received";
0750     case XGBE_AN_INCOMPAT_LINK:
0751         return "Incompatible-Link";
0752     case XGBE_AN_COMPLETE:
0753         return "Complete";
0754     case XGBE_AN_NO_LINK:
0755         return "No-Link";
0756     case XGBE_AN_ERROR:
0757         return "Error";
0758     default:
0759         return "Undefined";
0760     }
0761 }
0762 
0763 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
0764 {
0765     enum xgbe_an cur_state = pdata->an_state;
0766 
0767     if (!pdata->an_int)
0768         return;
0769 
0770     if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
0771         pdata->an_state = XGBE_AN_COMPLETE;
0772         pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
0773 
0774         /* If SGMII is enabled, check the link status */
0775         if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
0776             !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
0777             pdata->an_state = XGBE_AN_NO_LINK;
0778     }
0779 
0780     netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
0781           xgbe_state_as_string(pdata->an_state));
0782 
0783     cur_state = pdata->an_state;
0784 
0785     switch (pdata->an_state) {
0786     case XGBE_AN_READY:
0787         break;
0788 
0789     case XGBE_AN_COMPLETE:
0790         netif_dbg(pdata, link, pdata->netdev,
0791               "Auto negotiation successful\n");
0792         break;
0793 
0794     case XGBE_AN_NO_LINK:
0795         break;
0796 
0797     default:
0798         pdata->an_state = XGBE_AN_ERROR;
0799     }
0800 
0801     if (pdata->an_state == XGBE_AN_ERROR) {
0802         netdev_err(pdata->netdev,
0803                "error during auto-negotiation, state=%u\n",
0804                cur_state);
0805 
0806         pdata->an_int = 0;
0807         xgbe_an37_clear_interrupts(pdata);
0808     }
0809 
0810     if (pdata->an_state >= XGBE_AN_COMPLETE) {
0811         pdata->an_result = pdata->an_state;
0812         pdata->an_state = XGBE_AN_READY;
0813 
0814         if (pdata->phy_if.phy_impl.an_post)
0815             pdata->phy_if.phy_impl.an_post(pdata);
0816 
0817         netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
0818               xgbe_state_as_string(pdata->an_result));
0819     }
0820 
0821     xgbe_an37_enable_interrupts(pdata);
0822 }
0823 
0824 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
0825 {
0826     enum xgbe_an cur_state = pdata->an_state;
0827 
0828     if (!pdata->an_int)
0829         return;
0830 
0831 next_int:
0832     if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
0833         pdata->an_state = XGBE_AN_PAGE_RECEIVED;
0834         pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
0835     } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
0836         pdata->an_state = XGBE_AN_INCOMPAT_LINK;
0837         pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
0838     } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
0839         pdata->an_state = XGBE_AN_COMPLETE;
0840         pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
0841     } else {
0842         pdata->an_state = XGBE_AN_ERROR;
0843     }
0844 
0845 again:
0846     netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
0847           xgbe_state_as_string(pdata->an_state));
0848 
0849     cur_state = pdata->an_state;
0850 
0851     switch (pdata->an_state) {
0852     case XGBE_AN_READY:
0853         pdata->an_supported = 0;
0854         break;
0855 
0856     case XGBE_AN_PAGE_RECEIVED:
0857         pdata->an_state = xgbe_an73_page_received(pdata);
0858         pdata->an_supported++;
0859         break;
0860 
0861     case XGBE_AN_INCOMPAT_LINK:
0862         pdata->an_supported = 0;
0863         pdata->parallel_detect = 0;
0864         pdata->an_state = xgbe_an73_incompat_link(pdata);
0865         break;
0866 
0867     case XGBE_AN_COMPLETE:
0868         pdata->parallel_detect = pdata->an_supported ? 0 : 1;
0869         netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
0870               pdata->an_supported ? "Auto negotiation"
0871                           : "Parallel detection");
0872         break;
0873 
0874     case XGBE_AN_NO_LINK:
0875         break;
0876 
0877     default:
0878         pdata->an_state = XGBE_AN_ERROR;
0879     }
0880 
0881     if (pdata->an_state == XGBE_AN_NO_LINK) {
0882         pdata->an_int = 0;
0883         xgbe_an73_clear_interrupts(pdata);
0884     } else if (pdata->an_state == XGBE_AN_ERROR) {
0885         netdev_err(pdata->netdev,
0886                "error during auto-negotiation, state=%u\n",
0887                cur_state);
0888 
0889         pdata->an_int = 0;
0890         xgbe_an73_clear_interrupts(pdata);
0891     }
0892 
0893     if (pdata->an_state >= XGBE_AN_COMPLETE) {
0894         pdata->an_result = pdata->an_state;
0895         pdata->an_state = XGBE_AN_READY;
0896         pdata->kr_state = XGBE_RX_BPA;
0897         pdata->kx_state = XGBE_RX_BPA;
0898         pdata->an_start = 0;
0899 
0900         if (pdata->phy_if.phy_impl.an_post)
0901             pdata->phy_if.phy_impl.an_post(pdata);
0902 
0903         netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
0904               xgbe_state_as_string(pdata->an_result));
0905     }
0906 
0907     if (cur_state != pdata->an_state)
0908         goto again;
0909 
0910     if (pdata->an_int)
0911         goto next_int;
0912 
0913     xgbe_an73_enable_interrupts(pdata);
0914 }
0915 
0916 static void xgbe_an_state_machine(struct work_struct *work)
0917 {
0918     struct xgbe_prv_data *pdata = container_of(work,
0919                            struct xgbe_prv_data,
0920                            an_work);
0921 
0922     mutex_lock(&pdata->an_mutex);
0923 
0924     switch (pdata->an_mode) {
0925     case XGBE_AN_MODE_CL73:
0926     case XGBE_AN_MODE_CL73_REDRV:
0927         xgbe_an73_state_machine(pdata);
0928         break;
0929     case XGBE_AN_MODE_CL37:
0930     case XGBE_AN_MODE_CL37_SGMII:
0931         xgbe_an37_state_machine(pdata);
0932         break;
0933     default:
0934         break;
0935     }
0936 
0937     /* Reissue interrupt if status is not clear */
0938     if (pdata->vdata->irq_reissue_support)
0939         XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
0940 
0941     mutex_unlock(&pdata->an_mutex);
0942 }
0943 
0944 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
0945 {
0946     struct ethtool_link_ksettings lks;
0947     unsigned int reg;
0948 
0949     pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
0950 
0951     /* Set up Advertisement register */
0952     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
0953     if (XGBE_ADV(&lks, Pause))
0954         reg |= 0x100;
0955     else
0956         reg &= ~0x100;
0957 
0958     if (XGBE_ADV(&lks, Asym_Pause))
0959         reg |= 0x80;
0960     else
0961         reg &= ~0x80;
0962 
0963     /* Full duplex, but not half */
0964     reg |= XGBE_AN_CL37_FD_MASK;
0965     reg &= ~XGBE_AN_CL37_HD_MASK;
0966 
0967     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
0968 
0969     /* Set up the Control register */
0970     reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
0971     reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
0972     reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
0973 
0974     switch (pdata->an_mode) {
0975     case XGBE_AN_MODE_CL37:
0976         reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
0977         break;
0978     case XGBE_AN_MODE_CL37_SGMII:
0979         reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
0980         break;
0981     default:
0982         break;
0983     }
0984 
0985     reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
0986 
0987     XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
0988 
0989     netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
0990           (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
0991 }
0992 
0993 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
0994 {
0995     struct ethtool_link_ksettings lks;
0996     unsigned int reg;
0997 
0998     pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
0999 
1000     /* Set up Advertisement register 3 first */
1001     reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1002     if (XGBE_ADV(&lks, 10000baseR_FEC))
1003         reg |= 0xc000;
1004     else
1005         reg &= ~0xc000;
1006 
1007     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1008 
1009     /* Set up Advertisement register 2 next */
1010     reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1011     if (XGBE_ADV(&lks, 10000baseKR_Full))
1012         reg |= 0x80;
1013     else
1014         reg &= ~0x80;
1015 
1016     if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1017         XGBE_ADV(&lks, 2500baseX_Full))
1018         reg |= 0x20;
1019     else
1020         reg &= ~0x20;
1021 
1022     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1023 
1024     /* Set up Advertisement register 1 last */
1025     reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1026     if (XGBE_ADV(&lks, Pause))
1027         reg |= 0x400;
1028     else
1029         reg &= ~0x400;
1030 
1031     if (XGBE_ADV(&lks, Asym_Pause))
1032         reg |= 0x800;
1033     else
1034         reg &= ~0x800;
1035 
1036     /* We don't intend to perform XNP */
1037     reg &= ~XGBE_XNP_NP_EXCHANGE;
1038 
1039     XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1040 
1041     netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1042 }
1043 
1044 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1045 {
1046     /* Set up advertisement registers based on current settings */
1047     pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1048     switch (pdata->an_mode) {
1049     case XGBE_AN_MODE_CL73:
1050     case XGBE_AN_MODE_CL73_REDRV:
1051         xgbe_an73_init(pdata);
1052         break;
1053     case XGBE_AN_MODE_CL37:
1054     case XGBE_AN_MODE_CL37_SGMII:
1055         xgbe_an37_init(pdata);
1056         break;
1057     default:
1058         break;
1059     }
1060 }
1061 
1062 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1063 {
1064     if (pdata->tx_pause && pdata->rx_pause)
1065         return "rx/tx";
1066     else if (pdata->rx_pause)
1067         return "rx";
1068     else if (pdata->tx_pause)
1069         return "tx";
1070     else
1071         return "off";
1072 }
1073 
1074 static const char *xgbe_phy_speed_string(int speed)
1075 {
1076     switch (speed) {
1077     case SPEED_100:
1078         return "100Mbps";
1079     case SPEED_1000:
1080         return "1Gbps";
1081     case SPEED_2500:
1082         return "2.5Gbps";
1083     case SPEED_10000:
1084         return "10Gbps";
1085     case SPEED_UNKNOWN:
1086         return "Unknown";
1087     default:
1088         return "Unsupported";
1089     }
1090 }
1091 
1092 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1093 {
1094     if (pdata->phy.link)
1095         netdev_info(pdata->netdev,
1096                 "Link is Up - %s/%s - flow control %s\n",
1097                 xgbe_phy_speed_string(pdata->phy.speed),
1098                 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1099                 xgbe_phy_fc_string(pdata));
1100     else
1101         netdev_info(pdata->netdev, "Link is Down\n");
1102 }
1103 
1104 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1105 {
1106     int new_state = 0;
1107 
1108     if (pdata->phy.link) {
1109         /* Flow control support */
1110         pdata->pause_autoneg = pdata->phy.pause_autoneg;
1111 
1112         if (pdata->tx_pause != pdata->phy.tx_pause) {
1113             new_state = 1;
1114             pdata->tx_pause = pdata->phy.tx_pause;
1115             pdata->hw_if.config_tx_flow_control(pdata);
1116         }
1117 
1118         if (pdata->rx_pause != pdata->phy.rx_pause) {
1119             new_state = 1;
1120             pdata->rx_pause = pdata->phy.rx_pause;
1121             pdata->hw_if.config_rx_flow_control(pdata);
1122         }
1123 
1124         /* Speed support */
1125         if (pdata->phy_speed != pdata->phy.speed) {
1126             new_state = 1;
1127             pdata->phy_speed = pdata->phy.speed;
1128         }
1129 
1130         if (pdata->phy_link != pdata->phy.link) {
1131             new_state = 1;
1132             pdata->phy_link = pdata->phy.link;
1133         }
1134     } else if (pdata->phy_link) {
1135         new_state = 1;
1136         pdata->phy_link = 0;
1137         pdata->phy_speed = SPEED_UNKNOWN;
1138     }
1139 
1140     if (new_state && netif_msg_link(pdata))
1141         xgbe_phy_print_status(pdata);
1142 }
1143 
1144 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1145 {
1146     return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1147 }
1148 
1149 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1150 {
1151     enum xgbe_mode mode;
1152 
1153     netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1154 
1155     /* Disable auto-negotiation */
1156     xgbe_an_disable(pdata);
1157 
1158     /* Set specified mode for specified speed */
1159     mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1160     switch (mode) {
1161     case XGBE_MODE_KX_1000:
1162     case XGBE_MODE_KX_2500:
1163     case XGBE_MODE_KR:
1164     case XGBE_MODE_SGMII_100:
1165     case XGBE_MODE_SGMII_1000:
1166     case XGBE_MODE_X:
1167     case XGBE_MODE_SFI:
1168         break;
1169     case XGBE_MODE_UNKNOWN:
1170     default:
1171         return -EINVAL;
1172     }
1173 
1174     /* Validate duplex mode */
1175     if (pdata->phy.duplex != DUPLEX_FULL)
1176         return -EINVAL;
1177 
1178     xgbe_set_mode(pdata, mode);
1179 
1180     return 0;
1181 }
1182 
1183 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1184 {
1185     int ret;
1186 
1187     mutex_lock(&pdata->an_mutex);
1188 
1189     set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1190     pdata->link_check = jiffies;
1191 
1192     ret = pdata->phy_if.phy_impl.an_config(pdata);
1193     if (ret)
1194         goto out;
1195 
1196     if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1197         ret = xgbe_phy_config_fixed(pdata);
1198         if (ret || !pdata->kr_redrv)
1199             goto out;
1200 
1201         netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1202     } else {
1203         netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1204     }
1205 
1206     /* Disable auto-negotiation interrupt */
1207     disable_irq(pdata->an_irq);
1208 
1209     if (set_mode) {
1210         /* Start auto-negotiation in a supported mode */
1211         if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1212             xgbe_set_mode(pdata, XGBE_MODE_KR);
1213         } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1214             xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1215         } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1216             xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1217         } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1218             xgbe_set_mode(pdata, XGBE_MODE_SFI);
1219         } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1220             xgbe_set_mode(pdata, XGBE_MODE_X);
1221         } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1222             xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1223         } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1224             xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1225         } else {
1226             enable_irq(pdata->an_irq);
1227             ret = -EINVAL;
1228             goto out;
1229         }
1230     }
1231 
1232     /* Disable and stop any in progress auto-negotiation */
1233     xgbe_an_disable_all(pdata);
1234 
1235     /* Clear any auto-negotitation interrupts */
1236     xgbe_an_clear_interrupts_all(pdata);
1237 
1238     pdata->an_result = XGBE_AN_READY;
1239     pdata->an_state = XGBE_AN_READY;
1240     pdata->kr_state = XGBE_RX_BPA;
1241     pdata->kx_state = XGBE_RX_BPA;
1242 
1243     /* Re-enable auto-negotiation interrupt */
1244     enable_irq(pdata->an_irq);
1245 
1246     xgbe_an_init(pdata);
1247     xgbe_an_restart(pdata);
1248 
1249 out:
1250     if (ret)
1251         set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1252     else
1253         clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1254 
1255     mutex_unlock(&pdata->an_mutex);
1256 
1257     return ret;
1258 }
1259 
1260 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1261 {
1262     return __xgbe_phy_config_aneg(pdata, true);
1263 }
1264 
1265 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1266 {
1267     return __xgbe_phy_config_aneg(pdata, false);
1268 }
1269 
1270 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1271 {
1272     return (pdata->an_result == XGBE_AN_COMPLETE);
1273 }
1274 
1275 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1276 {
1277     unsigned long link_timeout;
1278 
1279     link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1280     if (time_after(jiffies, link_timeout)) {
1281         netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1282         xgbe_phy_config_aneg(pdata);
1283     }
1284 }
1285 
1286 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1287 {
1288     return pdata->phy_if.phy_impl.an_outcome(pdata);
1289 }
1290 
1291 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1292 {
1293     struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1294     enum xgbe_mode mode;
1295 
1296     XGBE_ZERO_LP_ADV(lks);
1297 
1298     if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1299         mode = xgbe_cur_mode(pdata);
1300     else
1301         mode = xgbe_phy_status_aneg(pdata);
1302 
1303     switch (mode) {
1304     case XGBE_MODE_SGMII_100:
1305         pdata->phy.speed = SPEED_100;
1306         break;
1307     case XGBE_MODE_X:
1308     case XGBE_MODE_KX_1000:
1309     case XGBE_MODE_SGMII_1000:
1310         pdata->phy.speed = SPEED_1000;
1311         break;
1312     case XGBE_MODE_KX_2500:
1313         pdata->phy.speed = SPEED_2500;
1314         break;
1315     case XGBE_MODE_KR:
1316     case XGBE_MODE_SFI:
1317         pdata->phy.speed = SPEED_10000;
1318         break;
1319     case XGBE_MODE_UNKNOWN:
1320     default:
1321         pdata->phy.speed = SPEED_UNKNOWN;
1322     }
1323 
1324     pdata->phy.duplex = DUPLEX_FULL;
1325 
1326     if (xgbe_set_mode(pdata, mode) && pdata->an_again)
1327         xgbe_phy_reconfig_aneg(pdata);
1328 }
1329 
1330 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1331 {
1332     unsigned int link_aneg;
1333     int an_restart;
1334 
1335     if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1336         netif_carrier_off(pdata->netdev);
1337 
1338         pdata->phy.link = 0;
1339         goto adjust_link;
1340     }
1341 
1342     link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1343 
1344     pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1345                                  &an_restart);
1346     if (an_restart) {
1347         xgbe_phy_config_aneg(pdata);
1348         goto adjust_link;
1349     }
1350 
1351     if (pdata->phy.link) {
1352         if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1353             xgbe_check_link_timeout(pdata);
1354             return;
1355         }
1356 
1357         xgbe_phy_status_result(pdata);
1358 
1359         if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1360             clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1361 
1362         netif_carrier_on(pdata->netdev);
1363     } else {
1364         if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1365             xgbe_check_link_timeout(pdata);
1366 
1367             if (link_aneg)
1368                 return;
1369         }
1370 
1371         xgbe_phy_status_result(pdata);
1372 
1373         netif_carrier_off(pdata->netdev);
1374     }
1375 
1376 adjust_link:
1377     xgbe_phy_adjust_link(pdata);
1378 }
1379 
1380 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1381 {
1382     netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1383 
1384     if (!pdata->phy_started)
1385         return;
1386 
1387     /* Indicate the PHY is down */
1388     pdata->phy_started = 0;
1389 
1390     /* Disable auto-negotiation */
1391     xgbe_an_disable_all(pdata);
1392 
1393     if (pdata->dev_irq != pdata->an_irq)
1394         devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1395 
1396     pdata->phy_if.phy_impl.stop(pdata);
1397 
1398     pdata->phy.link = 0;
1399 
1400     xgbe_phy_adjust_link(pdata);
1401 }
1402 
1403 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1404 {
1405     struct net_device *netdev = pdata->netdev;
1406     int ret;
1407 
1408     netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1409 
1410     ret = pdata->phy_if.phy_impl.start(pdata);
1411     if (ret)
1412         return ret;
1413 
1414     /* If we have a separate AN irq, enable it */
1415     if (pdata->dev_irq != pdata->an_irq) {
1416         tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task);
1417 
1418         ret = devm_request_irq(pdata->dev, pdata->an_irq,
1419                        xgbe_an_isr, 0, pdata->an_name,
1420                        pdata);
1421         if (ret) {
1422             netdev_err(netdev, "phy irq request failed\n");
1423             goto err_stop;
1424         }
1425     }
1426 
1427     /* Set initial mode - call the mode setting routines
1428      * directly to insure we are properly configured
1429      */
1430     if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1431         xgbe_kr_mode(pdata);
1432     } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1433         xgbe_kx_2500_mode(pdata);
1434     } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1435         xgbe_kx_1000_mode(pdata);
1436     } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1437         xgbe_sfi_mode(pdata);
1438     } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1439         xgbe_x_mode(pdata);
1440     } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1441         xgbe_sgmii_1000_mode(pdata);
1442     } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1443         xgbe_sgmii_100_mode(pdata);
1444     } else {
1445         ret = -EINVAL;
1446         goto err_irq;
1447     }
1448 
1449     /* Indicate the PHY is up and running */
1450     pdata->phy_started = 1;
1451 
1452     xgbe_an_init(pdata);
1453     xgbe_an_enable_interrupts(pdata);
1454 
1455     return xgbe_phy_config_aneg(pdata);
1456 
1457 err_irq:
1458     if (pdata->dev_irq != pdata->an_irq)
1459         devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1460 
1461 err_stop:
1462     pdata->phy_if.phy_impl.stop(pdata);
1463 
1464     return ret;
1465 }
1466 
1467 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1468 {
1469     int ret;
1470 
1471     ret = pdata->phy_if.phy_impl.reset(pdata);
1472     if (ret)
1473         return ret;
1474 
1475     /* Disable auto-negotiation for now */
1476     xgbe_an_disable_all(pdata);
1477 
1478     /* Clear auto-negotiation interrupts */
1479     xgbe_an_clear_interrupts_all(pdata);
1480 
1481     return 0;
1482 }
1483 
1484 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1485 {
1486     struct device *dev = pdata->dev;
1487 
1488     dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1489 
1490     dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1491         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1492     dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1493         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1494     dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1495         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1496     dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1497         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1498     dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1499         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1500     dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1501         XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1502 
1503     dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1504         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1505     dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1506         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1507     dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1508         MDIO_AN_ADVERTISE,
1509         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1510     dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1511         MDIO_AN_ADVERTISE + 1,
1512         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1513     dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1514         MDIO_AN_ADVERTISE + 2,
1515         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1516     dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1517         MDIO_AN_COMP_STAT,
1518         XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1519 
1520     dev_dbg(dev, "\n*************************************************\n");
1521 }
1522 
1523 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1524 {
1525     struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1526 
1527     if (XGBE_ADV(lks, 10000baseKR_Full))
1528         return SPEED_10000;
1529     else if (XGBE_ADV(lks, 10000baseT_Full))
1530         return SPEED_10000;
1531     else if (XGBE_ADV(lks, 2500baseX_Full))
1532         return SPEED_2500;
1533     else if (XGBE_ADV(lks, 2500baseT_Full))
1534         return SPEED_2500;
1535     else if (XGBE_ADV(lks, 1000baseKX_Full))
1536         return SPEED_1000;
1537     else if (XGBE_ADV(lks, 1000baseT_Full))
1538         return SPEED_1000;
1539     else if (XGBE_ADV(lks, 100baseT_Full))
1540         return SPEED_100;
1541 
1542     return SPEED_UNKNOWN;
1543 }
1544 
1545 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1546 {
1547     pdata->phy_if.phy_impl.exit(pdata);
1548 }
1549 
1550 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1551 {
1552     struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1553     int ret;
1554 
1555     mutex_init(&pdata->an_mutex);
1556     INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1557     INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1558     pdata->mdio_mmd = MDIO_MMD_PCS;
1559 
1560     /* Check for FEC support */
1561     pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1562                     MDIO_PMA_10GBR_FECABLE);
1563     pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1564                    MDIO_PMA_10GBR_FECABLE_ERRABLE);
1565 
1566     /* Setup the phy (including supported features) */
1567     ret = pdata->phy_if.phy_impl.init(pdata);
1568     if (ret)
1569         return ret;
1570 
1571     /* Copy supported link modes to advertising link modes */
1572     XGBE_LM_COPY(lks, advertising, lks, supported);
1573 
1574     pdata->phy.address = 0;
1575 
1576     if (XGBE_ADV(lks, Autoneg)) {
1577         pdata->phy.autoneg = AUTONEG_ENABLE;
1578         pdata->phy.speed = SPEED_UNKNOWN;
1579         pdata->phy.duplex = DUPLEX_UNKNOWN;
1580     } else {
1581         pdata->phy.autoneg = AUTONEG_DISABLE;
1582         pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1583         pdata->phy.duplex = DUPLEX_FULL;
1584     }
1585 
1586     pdata->phy.link = 0;
1587 
1588     pdata->phy.pause_autoneg = pdata->pause_autoneg;
1589     pdata->phy.tx_pause = pdata->tx_pause;
1590     pdata->phy.rx_pause = pdata->rx_pause;
1591 
1592     /* Fix up Flow Control advertising */
1593     XGBE_CLR_ADV(lks, Pause);
1594     XGBE_CLR_ADV(lks, Asym_Pause);
1595 
1596     if (pdata->rx_pause) {
1597         XGBE_SET_ADV(lks, Pause);
1598         XGBE_SET_ADV(lks, Asym_Pause);
1599     }
1600 
1601     if (pdata->tx_pause) {
1602         /* Equivalent to XOR of Asym_Pause */
1603         if (XGBE_ADV(lks, Asym_Pause))
1604             XGBE_CLR_ADV(lks, Asym_Pause);
1605         else
1606             XGBE_SET_ADV(lks, Asym_Pause);
1607     }
1608 
1609     if (netif_msg_drv(pdata))
1610         xgbe_dump_phy_registers(pdata);
1611 
1612     return 0;
1613 }
1614 
1615 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1616 {
1617     phy_if->phy_init        = xgbe_phy_init;
1618     phy_if->phy_exit        = xgbe_phy_exit;
1619 
1620     phy_if->phy_reset       = xgbe_phy_reset;
1621     phy_if->phy_start       = xgbe_phy_start;
1622     phy_if->phy_stop        = xgbe_phy_stop;
1623 
1624     phy_if->phy_status      = xgbe_phy_status;
1625     phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1626 
1627     phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1628 
1629     phy_if->an_isr          = xgbe_an_combined_isr;
1630 
1631     phy_if->module_info     = xgbe_phy_module_info;
1632     phy_if->module_eeprom   = xgbe_phy_module_eeprom;
1633 }
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