amd/xgbe/xgbe-i2c.c

0001 /*
0002  * AMD 10Gb Ethernet driver
0003  *
0004  * This file is available to you under your choice of the following two
0005  * licenses:
0006  *
0007  * License 1: GPLv2
0008  *
0009  * Copyright (c) 2016 Advanced Micro Devices, Inc.
0010  *
0011  * This file is free software; you may copy, redistribute and/or modify
0012  * it under the terms of the GNU General Public License as published by
0013  * the Free Software Foundation, either version 2 of the License, or (at
0014  * your option) any later version.
0015  *
0016  * This file is distributed in the hope that it will be useful, but
0017  * WITHOUT ANY WARRANTY; without even the implied warranty of
0018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
0019  * General Public License for more details.
0020  *
0021  * You should have received a copy of the GNU General Public License
0022  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
0023  *
0024  * This file incorporates work covered by the following copyright and
0025  * permission notice:
0026  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
0027  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
0028  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
0029  *     and you.
0030  *
0031  *     The Software IS NOT an item of Licensed Software or Licensed Product
0032  *     under any End User Software License Agreement or Agreement for Licensed
0033  *     Product with Synopsys or any supplement thereto.  Permission is hereby
0034  *     granted, free of charge, to any person obtaining a copy of this software
0035  *     annotated with this license and the Software, to deal in the Software
0036  *     without restriction, including without limitation the rights to use,
0037  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
0038  *     of the Software, and to permit persons to whom the Software is furnished
0039  *     to do so, subject to the following conditions:
0040  *
0041  *     The above copyright notice and this permission notice shall be included
0042  *     in all copies or substantial portions of the Software.
0043  *
0044  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
0045  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0046  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0047  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
0048  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0049  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0050  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0051  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0052  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0053  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
0054  *     THE POSSIBILITY OF SUCH DAMAGE.
0055  *
0056  *
0057  * License 2: Modified BSD
0058  *
0059  * Copyright (c) 2016 Advanced Micro Devices, Inc.
0060  * All rights reserved.
0061  *
0062  * Redistribution and use in source and binary forms, with or without
0063  * modification, are permitted provided that the following conditions are met:
0064  *     * Redistributions of source code must retain the above copyright
0065  *       notice, this list of conditions and the following disclaimer.
0066  *     * Redistributions in binary form must reproduce the above copyright
0067  *       notice, this list of conditions and the following disclaimer in the
0068  *       documentation and/or other materials provided with the distribution.
0069  *     * Neither the name of Advanced Micro Devices, Inc. nor the
0070  *       names of its contributors may be used to endorse or promote products
0071  *       derived from this software without specific prior written permission.
0072  *
0073  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0074  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0075  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0076  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
0077  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0078  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0079  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0080  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0081  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0082  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0083  *
0084  * This file incorporates work covered by the following copyright and
0085  * permission notice:
0086  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
0087  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
0088  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
0089  *     and you.
0090  *
0091  *     The Software IS NOT an item of Licensed Software or Licensed Product
0092  *     under any End User Software License Agreement or Agreement for Licensed
0093  *     Product with Synopsys or any supplement thereto.  Permission is hereby
0094  *     granted, free of charge, to any person obtaining a copy of this software
0095  *     annotated with this license and the Software, to deal in the Software
0096  *     without restriction, including without limitation the rights to use,
0097  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
0098  *     of the Software, and to permit persons to whom the Software is furnished
0099  *     to do so, subject to the following conditions:
0100  *
0101  *     The above copyright notice and this permission notice shall be included
0102  *     in all copies or substantial portions of the Software.
0103  *
0104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
0105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
0108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
0114  *     THE POSSIBILITY OF SUCH DAMAGE.
0115  */
0116
0117 #include <linux/module.h>
0118 #include <linux/interrupt.h>
0119 #include <linux/kmod.h>
0120 #include <linux/delay.h>
0121 #include <linux/completion.h>
0122 #include <linux/mutex.h>
0123
0124 #include "xgbe.h"
0125 #include "xgbe-common.h"
0126
0127 #define XGBE_ABORT_COUNT    500
0128 #define XGBE_DISABLE_COUNT  1000
0129
0130 #define XGBE_STD_SPEED      1
0131
0132 #define XGBE_INTR_RX_FULL   BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
0133 #define XGBE_INTR_TX_EMPTY  BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
0134 #define XGBE_INTR_TX_ABRT   BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
0135 #define XGBE_INTR_STOP_DET  BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
0136 #define XGBE_DEFAULT_INT_MASK   (XGBE_INTR_RX_FULL  |   \
0137                  XGBE_INTR_TX_EMPTY |   \
0138                  XGBE_INTR_TX_ABRT  |   \
0139                  XGBE_INTR_STOP_DET)
0140
0141 #define XGBE_I2C_READ       BIT(8)
0142 #define XGBE_I2C_STOP       BIT(9)
0143
0144 static int xgbe_i2c_abort(struct xgbe_prv_data *pdata)
0145 {
0146     unsigned int wait = XGBE_ABORT_COUNT;
0147
0148     /* Must be enabled to recognize the abort request */
0149     XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
0150
0151     /* Issue the abort */
0152     XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
0153
0154     while (wait--) {
0155         if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
0156             return 0;
0157
0158         usleep_range(500, 600);
0159     }
0160
0161     return -EBUSY;
0162 }
0163
0164 static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
0165 {
0166     unsigned int wait = XGBE_DISABLE_COUNT;
0167     unsigned int mode = enable ? 1 : 0;
0168
0169     while (wait--) {
0170         XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
0171         if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
0172             return 0;
0173
0174         usleep_range(100, 110);
0175     }
0176
0177     return -EBUSY;
0178 }
0179
0180 static int xgbe_i2c_disable(struct xgbe_prv_data *pdata)
0181 {
0182     unsigned int ret;
0183
0184     ret = xgbe_i2c_set_enable(pdata, false);
0185     if (ret) {
0186         /* Disable failed, try an abort */
0187         ret = xgbe_i2c_abort(pdata);
0188         if (ret)
0189             return ret;
0190
0191         /* Abort succeeded, try to disable again */
0192         ret = xgbe_i2c_set_enable(pdata, false);
0193     }
0194
0195     return ret;
0196 }
0197
0198 static int xgbe_i2c_enable(struct xgbe_prv_data *pdata)
0199 {
0200     return xgbe_i2c_set_enable(pdata, true);
0201 }
0202
0203 static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
0204 {
0205     XI2C_IOREAD(pdata, IC_CLR_INTR);
0206 }
0207
0208 static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
0209 {
0210     XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
0211 }
0212
0213 static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
0214 {
0215     XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
0216 }
0217
0218 static void xgbe_i2c_write(struct xgbe_prv_data *pdata)
0219 {
0220     struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
0221     unsigned int tx_slots;
0222     unsigned int cmd;
0223
0224     /* Configured to never receive Rx overflows, so fill up Tx fifo */
0225     tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
0226     while (tx_slots && state->tx_len) {
0227         if (state->op->cmd == XGBE_I2C_CMD_READ)
0228             cmd = XGBE_I2C_READ;
0229         else
0230             cmd = *state->tx_buf++;
0231
0232         if (state->tx_len == 1)
0233             XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
0234
0235         XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
0236
0237         tx_slots--;
0238         state->tx_len--;
0239     }
0240
0241     /* No more Tx operations, so ignore TX_EMPTY and return */
0242     if (!state->tx_len)
0243         XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
0244 }
0245
0246 static void xgbe_i2c_read(struct xgbe_prv_data *pdata)
0247 {
0248     struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
0249     unsigned int rx_slots;
0250
0251     /* Anything to be read? */
0252     if (state->op->cmd != XGBE_I2C_CMD_READ)
0253         return;
0254
0255     rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
0256     while (rx_slots && state->rx_len) {
0257         *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
0258         state->rx_len--;
0259         rx_slots--;
0260     }
0261 }
0262
0263 static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata,
0264                       unsigned int isr)
0265 {
0266     struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
0267
0268     if (isr & XGBE_INTR_TX_ABRT) {
0269         state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
0270         XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
0271     }
0272
0273     if (isr & XGBE_INTR_STOP_DET)
0274         XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
0275 }
0276
0277 static void xgbe_i2c_isr_task(struct tasklet_struct *t)
0278 {
0279     struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_i2c);
0280     struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
0281     unsigned int isr;
0282
0283     isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
0284     if (!isr)
0285         goto reissue_check;
0286
0287     netif_dbg(pdata, intr, pdata->netdev,
0288           "I2C interrupt received: status=%#010x\n", isr);
0289
0290     xgbe_i2c_clear_isr_interrupts(pdata, isr);
0291
0292     if (isr & XGBE_INTR_TX_ABRT) {
0293         netif_dbg(pdata, link, pdata->netdev,
0294               "I2C TX_ABRT received (%#010x) for target %#04x\n",
0295               state->tx_abort_source, state->op->target);
0296
0297         xgbe_i2c_disable_interrupts(pdata);
0298
0299         state->ret = -EIO;
0300         goto out;
0301     }
0302
0303     /* Check for data in the Rx fifo */
0304     xgbe_i2c_read(pdata);
0305
0306     /* Fill up the Tx fifo next */
0307     xgbe_i2c_write(pdata);
0308
0309 out:
0310     /* Complete on an error or STOP condition */
0311     if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
0312         complete(&pdata->i2c_complete);
0313
0314 reissue_check:
0315     /* Reissue interrupt if status is not clear */
0316     if (pdata->vdata->irq_reissue_support)
0317         XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);
0318 }
0319
0320 static irqreturn_t xgbe_i2c_isr(int irq, void *data)
0321 {
0322     struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
0323
0324     if (pdata->isr_as_tasklet)
0325         tasklet_schedule(&pdata->tasklet_i2c);
0326     else
0327         xgbe_i2c_isr_task(&pdata->tasklet_i2c);
0328
0329     return IRQ_HANDLED;
0330 }
0331
0332 static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
0333 {
0334     unsigned int reg;
0335
0336     reg = XI2C_IOREAD(pdata, IC_CON);
0337     XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
0338     XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
0339     XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
0340     XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
0341     XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
0342     XI2C_IOWRITE(pdata, IC_CON, reg);
0343 }
0344
0345 static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
0346 {
0347     struct xgbe_i2c *i2c = &pdata->i2c;
0348     unsigned int reg;
0349
0350     reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
0351     i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
0352                         MAX_SPEED_MODE);
0353     i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
0354                       RX_BUFFER_DEPTH);
0355     i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
0356                       TX_BUFFER_DEPTH);
0357
0358     if (netif_msg_probe(pdata))
0359         dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n",
0360             "MAX_SPEED_MODE", i2c->max_speed_mode,
0361             "RX_BUFFER_DEPTH", i2c->rx_fifo_size,
0362             "TX_BUFFER_DEPTH", i2c->tx_fifo_size);
0363 }
0364
0365 static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
0366 {
0367     XI2C_IOWRITE(pdata, IC_TAR, addr);
0368 }
0369
0370 static irqreturn_t xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)
0371 {
0372     xgbe_i2c_isr_task(&pdata->tasklet_i2c);
0373
0374     return IRQ_HANDLED;
0375 }
0376
0377 static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
0378 {
0379     struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
0380     int ret;
0381
0382     mutex_lock(&pdata->i2c_mutex);
0383
0384     reinit_completion(&pdata->i2c_complete);
0385
0386     ret = xgbe_i2c_disable(pdata);
0387     if (ret) {
0388         netdev_err(pdata->netdev, "failed to disable i2c master\n");
0389         goto unlock;
0390     }
0391
0392     xgbe_i2c_set_target(pdata, op->target);
0393
0394     memset(state, 0, sizeof(*state));
0395     state->op = op;
0396     state->tx_len = op->len;
0397     state->tx_buf = op->buf;
0398     state->rx_len = op->len;
0399     state->rx_buf = op->buf;
0400
0401     xgbe_i2c_clear_all_interrupts(pdata);
0402     ret = xgbe_i2c_enable(pdata);
0403     if (ret) {
0404         netdev_err(pdata->netdev, "failed to enable i2c master\n");
0405         goto unlock;
0406     }
0407
0408     /* Enabling the interrupts will cause the TX FIFO empty interrupt to
0409      * fire and begin to process the command via the ISR.
0410      */
0411     xgbe_i2c_enable_interrupts(pdata);
0412
0413     if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) {
0414         netdev_err(pdata->netdev, "i2c operation timed out\n");
0415         ret = -ETIMEDOUT;
0416         goto disable;
0417     }
0418
0419     ret = state->ret;
0420     if (ret) {
0421         if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
0422             ret = -ENOTCONN;
0423         else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
0424             ret = -EAGAIN;
0425     }
0426
0427 disable:
0428     xgbe_i2c_disable_interrupts(pdata);
0429     xgbe_i2c_disable(pdata);
0430
0431 unlock:
0432     mutex_unlock(&pdata->i2c_mutex);
0433
0434     return ret;
0435 }
0436
0437 static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
0438 {
0439     if (!pdata->i2c.started)
0440         return;
0441
0442     netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n");
0443
0444     pdata->i2c.started = 0;
0445
0446     xgbe_i2c_disable_interrupts(pdata);
0447     xgbe_i2c_disable(pdata);
0448     xgbe_i2c_clear_all_interrupts(pdata);
0449
0450     if (pdata->dev_irq != pdata->i2c_irq)
0451         devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
0452 }
0453
0454 static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
0455 {
0456     int ret;
0457
0458     if (pdata->i2c.started)
0459         return 0;
0460
0461     netif_dbg(pdata, link, pdata->netdev, "starting I2C\n");
0462
0463     /* If we have a separate I2C irq, enable it */
0464     if (pdata->dev_irq != pdata->i2c_irq) {
0465         tasklet_setup(&pdata->tasklet_i2c, xgbe_i2c_isr_task);
0466
0467         ret = devm_request_irq(pdata->dev, pdata->i2c_irq,
0468                        xgbe_i2c_isr, 0, pdata->i2c_name,
0469                        pdata);
0470         if (ret) {
0471             netdev_err(pdata->netdev, "i2c irq request failed\n");
0472             return ret;
0473         }
0474     }
0475
0476     pdata->i2c.started = 1;
0477
0478     return 0;
0479 }
0480
0481 static int xgbe_i2c_init(struct xgbe_prv_data *pdata)
0482 {
0483     int ret;
0484
0485     xgbe_i2c_disable_interrupts(pdata);
0486
0487     ret = xgbe_i2c_disable(pdata);
0488     if (ret) {
0489         dev_err(pdata->dev, "failed to disable i2c master\n");
0490         return ret;
0491     }
0492
0493     xgbe_i2c_get_features(pdata);
0494
0495     xgbe_i2c_set_mode(pdata);
0496
0497     xgbe_i2c_clear_all_interrupts(pdata);
0498
0499     return 0;
0500 }
0501
0502 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
0503 {
0504     i2c_if->i2c_init        = xgbe_i2c_init;
0505
0506     i2c_if->i2c_start       = xgbe_i2c_start;
0507     i2c_if->i2c_stop        = xgbe_i2c_stop;
0508
0509     i2c_if->i2c_xfer        = xgbe_i2c_xfer;
0510
0511     i2c_if->i2c_isr         = xgbe_i2c_combined_isr;
0512 }