ethernet/amd/sun3lance.c

0001 /* sun3lance.c: Ethernet driver for SUN3 Lance chip */
0002 /*
0003
0004   Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net).
0005   This driver is a part of the linux kernel, and is thus distributed
0006   under the GNU General Public License.
0007
0008   The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically
0009   true for the correct IRQ and address of the lance registers.  They
0010   have not been widely tested, however.  What we probably need is a
0011   "proper" way to search for a device in the sun3's prom, but, alas,
0012   linux has no such thing.
0013
0014   This driver is largely based on atarilance.c, by Roman Hodek.  Other
0015   sources of inspiration were the NetBSD sun3 am7990 driver, and the
0016   linux sparc lance driver (sunlance.c).
0017
0018   There are more assumptions made throughout this driver, it almost
0019   certainly still needs work, but it does work at least for RARP/BOOTP and
0020   mounting the root NFS filesystem.
0021
0022 */
0023
0024 static const char version[] =
0025 "sun3lance.c: v1.2 1/12/2001  Sam Creasey (sammy@sammy.net)\n";
0026
0027 #include <linux/module.h>
0028 #include <linux/stddef.h>
0029 #include <linux/kernel.h>
0030 #include <linux/string.h>
0031 #include <linux/errno.h>
0032 #include <linux/interrupt.h>
0033 #include <linux/init.h>
0034 #include <linux/ioport.h>
0035 #include <linux/delay.h>
0036 #include <linux/netdevice.h>
0037 #include <linux/etherdevice.h>
0038 #include <linux/skbuff.h>
0039 #include <linux/bitops.h>
0040 #include <linux/pgtable.h>
0041
0042 #include <asm/cacheflush.h>
0043 #include <asm/setup.h>
0044 #include <asm/irq.h>
0045 #include <asm/io.h>
0046 #include <asm/dvma.h>
0047 #include <asm/idprom.h>
0048 #include <asm/machines.h>
0049
0050 #ifdef CONFIG_SUN3
0051 #include <asm/sun3mmu.h>
0052 #else
0053 #include <asm/sun3xprom.h>
0054 #endif
0055
0056 /* sun3/60 addr/irq for the lance chip.  If your sun is different,
0057    change this. */
0058 #define LANCE_OBIO 0x120000
0059 #define LANCE_IRQ IRQ_AUTO_3
0060
0061 /* Debug level:
0062  *  0 = silent, print only serious errors
0063  *  1 = normal, print error messages
0064  *  2 = debug, print debug infos
0065  *  3 = debug, print even more debug infos (packet data)
0066  */
0067
0068 #define LANCE_DEBUG 0
0069
0070 #ifdef LANCE_DEBUG
0071 static int lance_debug = LANCE_DEBUG;
0072 #else
0073 static int lance_debug = 1;
0074 #endif
0075 module_param(lance_debug, int, 0);
0076 MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
0077 MODULE_LICENSE("GPL");
0078
0079 #define DPRINTK(n,a) \
0080     do {  \
0081         if (lance_debug >= n)  \
0082             printk a; \
0083     } while( 0 )
0084
0085
0086 /* we're only using 32k of memory, so we use 4 TX
0087    buffers and 16 RX buffers.  These values are expressed as log2. */
0088
0089 #define TX_LOG_RING_SIZE            3
0090 #define RX_LOG_RING_SIZE            5
0091
0092 /* These are the derived values */
0093
0094 #define TX_RING_SIZE            (1 << TX_LOG_RING_SIZE)
0095 #define TX_RING_LEN_BITS        (TX_LOG_RING_SIZE << 5)
0096 #define TX_RING_MOD_MASK        (TX_RING_SIZE - 1)
0097
0098 #define RX_RING_SIZE            (1 << RX_LOG_RING_SIZE)
0099 #define RX_RING_LEN_BITS        (RX_LOG_RING_SIZE << 5)
0100 #define RX_RING_MOD_MASK        (RX_RING_SIZE - 1)
0101
0102 /* Definitions for packet buffer access: */
0103 #define PKT_BUF_SZ      1544
0104
0105 /* Get the address of a packet buffer corresponding to a given buffer head */
0106 #define PKTBUF_ADDR(head)   (void *)((unsigned long)(MEM) | (head)->base)
0107
0108
0109 /* The LANCE Rx and Tx ring descriptors. */
0110 struct lance_rx_head {
0111     unsigned short  base;       /* Low word of base addr */
0112     volatile unsigned char  flag;
0113     unsigned char  base_hi; /* High word of base addr (unused) */
0114     short buf_length;   /* This length is 2s complement! */
0115     volatile short msg_length;  /* This length is "normal". */
0116 };
0117
0118 struct lance_tx_head {
0119     unsigned short base;        /* Low word of base addr */
0120     volatile unsigned char  flag;
0121     unsigned char base_hi;  /* High word of base addr (unused) */
0122     short length;       /* Length is 2s complement! */
0123     volatile short misc;
0124 };
0125
0126 /* The LANCE initialization block, described in databook. */
0127 struct lance_init_block {
0128     unsigned short  mode;       /* Pre-set mode */
0129     unsigned char   hwaddr[6];  /* Physical ethernet address */
0130     unsigned int    filter[2];  /* Multicast filter (unused). */
0131     /* Receive and transmit ring base, along with length bits. */
0132     unsigned short rdra;
0133     unsigned short rlen;
0134     unsigned short tdra;
0135     unsigned short tlen;
0136     unsigned short pad[4]; /* is thie needed? */
0137 };
0138
0139 /* The whole layout of the Lance shared memory */
0140 struct lance_memory {
0141     struct lance_init_block init;
0142     struct lance_tx_head    tx_head[TX_RING_SIZE];
0143     struct lance_rx_head    rx_head[RX_RING_SIZE];
0144     char   rx_data[RX_RING_SIZE][PKT_BUF_SZ];
0145     char   tx_data[TX_RING_SIZE][PKT_BUF_SZ];
0146 };
0147
0148 /* The driver's private device structure */
0149
0150 struct lance_private {
0151     volatile unsigned short *iobase;
0152     struct lance_memory *mem;
0153     int new_rx, new_tx; /* The next free ring entry */
0154     int old_tx, old_rx;     /* ring entry to be processed */
0155 /* These two must be longs for set_bit() */
0156     long        tx_full;
0157     long        lock;
0158 };
0159
0160 /* I/O register access macros */
0161
0162 #define MEM lp->mem
0163 #define DREG    lp->iobase[0]
0164 #define AREG    lp->iobase[1]
0165 #define REGA(a) (*( AREG = (a), &DREG ))
0166
0167 /* Definitions for the Lance */
0168
0169 /* tx_head flags */
0170 #define TMD1_ENP        0x01    /* end of packet */
0171 #define TMD1_STP        0x02    /* start of packet */
0172 #define TMD1_DEF        0x04    /* deferred */
0173 #define TMD1_ONE        0x08    /* one retry needed */
0174 #define TMD1_MORE       0x10    /* more than one retry needed */
0175 #define TMD1_ERR        0x40    /* error summary */
0176 #define TMD1_OWN        0x80    /* ownership (set: chip owns) */
0177
0178 #define TMD1_OWN_CHIP   TMD1_OWN
0179 #define TMD1_OWN_HOST   0
0180
0181 /* tx_head misc field */
0182 #define TMD3_TDR        0x03FF  /* Time Domain Reflectometry counter */
0183 #define TMD3_RTRY       0x0400  /* failed after 16 retries */
0184 #define TMD3_LCAR       0x0800  /* carrier lost */
0185 #define TMD3_LCOL       0x1000  /* late collision */
0186 #define TMD3_UFLO       0x4000  /* underflow (late memory) */
0187 #define TMD3_BUFF       0x8000  /* buffering error (no ENP) */
0188
0189 /* rx_head flags */
0190 #define RMD1_ENP        0x01    /* end of packet */
0191 #define RMD1_STP        0x02    /* start of packet */
0192 #define RMD1_BUFF       0x04    /* buffer error */
0193 #define RMD1_CRC        0x08    /* CRC error */
0194 #define RMD1_OFLO       0x10    /* overflow */
0195 #define RMD1_FRAM       0x20    /* framing error */
0196 #define RMD1_ERR        0x40    /* error summary */
0197 #define RMD1_OWN        0x80    /* ownership (set: ship owns) */
0198
0199 #define RMD1_OWN_CHIP   RMD1_OWN
0200 #define RMD1_OWN_HOST   0
0201
0202 /* register names */
0203 #define CSR0    0       /* mode/status */
0204 #define CSR1    1       /* init block addr (low) */
0205 #define CSR2    2       /* init block addr (high) */
0206 #define CSR3    3       /* misc */
0207 #define CSR8    8       /* address filter */
0208 #define CSR15   15      /* promiscuous mode */
0209
0210 /* CSR0 */
0211 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
0212 #define CSR0_INIT   0x0001      /* initialize (RS) */
0213 #define CSR0_STRT   0x0002      /* start (RS) */
0214 #define CSR0_STOP   0x0004      /* stop (RS) */
0215 #define CSR0_TDMD   0x0008      /* transmit demand (RS) */
0216 #define CSR0_TXON   0x0010      /* transmitter on (R) */
0217 #define CSR0_RXON   0x0020      /* receiver on (R) */
0218 #define CSR0_INEA   0x0040      /* interrupt enable (RW) */
0219 #define CSR0_INTR   0x0080      /* interrupt active (R) */
0220 #define CSR0_IDON   0x0100      /* initialization done (RC) */
0221 #define CSR0_TINT   0x0200      /* transmitter interrupt (RC) */
0222 #define CSR0_RINT   0x0400      /* receiver interrupt (RC) */
0223 #define CSR0_MERR   0x0800      /* memory error (RC) */
0224 #define CSR0_MISS   0x1000      /* missed frame (RC) */
0225 #define CSR0_CERR   0x2000      /* carrier error (no heartbeat :-) (RC) */
0226 #define CSR0_BABL   0x4000      /* babble: tx-ed too many bits (RC) */
0227 #define CSR0_ERR    0x8000      /* error (RC) */
0228
0229 /* CSR3 */
0230 #define CSR3_BCON   0x0001      /* byte control */
0231 #define CSR3_ACON   0x0002      /* ALE control */
0232 #define CSR3_BSWP   0x0004      /* byte swap (1=big endian) */
0233
0234 /***************************** Prototypes *****************************/
0235
0236 static int lance_probe( struct net_device *dev);
0237 static int lance_open( struct net_device *dev );
0238 static void lance_init_ring( struct net_device *dev );
0239 static netdev_tx_t lance_start_xmit(struct sk_buff *skb,
0240                     struct net_device *dev);
0241 static irqreturn_t lance_interrupt( int irq, void *dev_id);
0242 static int lance_rx( struct net_device *dev );
0243 static int lance_close( struct net_device *dev );
0244 static void set_multicast_list( struct net_device *dev );
0245
0246 /************************* End of Prototypes **************************/
0247
0248 static struct net_device * __init sun3lance_probe(void)
0249 {
0250     struct net_device *dev;
0251     static int found;
0252     int err = -ENODEV;
0253
0254     if (!MACH_IS_SUN3 && !MACH_IS_SUN3X)
0255         return ERR_PTR(-ENODEV);
0256
0257     /* check that this machine has an onboard lance */
0258     switch(idprom->id_machtype) {
0259     case SM_SUN3|SM_3_50:
0260     case SM_SUN3|SM_3_60:
0261     case SM_SUN3X|SM_3_80:
0262         /* these machines have lance */
0263         break;
0264
0265     default:
0266         return ERR_PTR(-ENODEV);
0267     }
0268
0269     if (found)
0270         return ERR_PTR(-ENODEV);
0271
0272     dev = alloc_etherdev(sizeof(struct lance_private));
0273     if (!dev)
0274         return ERR_PTR(-ENOMEM);
0275
0276     if (!lance_probe(dev))
0277         goto out;
0278
0279     err = register_netdev(dev);
0280     if (err)
0281         goto out1;
0282     found = 1;
0283     return dev;
0284
0285 out1:
0286 #ifdef CONFIG_SUN3
0287     iounmap((void __iomem *)dev->base_addr);
0288 #endif
0289 out:
0290     free_netdev(dev);
0291     return ERR_PTR(err);
0292 }
0293
0294 static const struct net_device_ops lance_netdev_ops = {
0295     .ndo_open       = lance_open,
0296     .ndo_stop       = lance_close,
0297     .ndo_start_xmit     = lance_start_xmit,
0298     .ndo_set_rx_mode    = set_multicast_list,
0299     .ndo_set_mac_address    = NULL,
0300     .ndo_validate_addr  = eth_validate_addr,
0301 };
0302
0303 static int __init lance_probe( struct net_device *dev)
0304 {
0305     unsigned long ioaddr;
0306
0307     struct lance_private    *lp;
0308     static int      did_version;
0309     volatile unsigned short *ioaddr_probe;
0310     unsigned short tmp1, tmp2;
0311
0312 #ifdef CONFIG_SUN3
0313     ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE);
0314     if (!ioaddr)
0315         return 0;
0316 #else
0317     ioaddr = SUN3X_LANCE;
0318 #endif
0319
0320     /* test to see if there's really a lance here */
0321     /* (CSRO_INIT shouldn't be readable) */
0322
0323     ioaddr_probe = (volatile unsigned short *)ioaddr;
0324     tmp1 = ioaddr_probe[0];
0325     tmp2 = ioaddr_probe[1];
0326
0327     ioaddr_probe[1] = CSR0;
0328     ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;
0329
0330     if(ioaddr_probe[0] != CSR0_STOP) {
0331         ioaddr_probe[0] = tmp1;
0332         ioaddr_probe[1] = tmp2;
0333
0334 #ifdef CONFIG_SUN3
0335         iounmap((void __iomem *)ioaddr);
0336 #endif
0337         return 0;
0338     }
0339
0340     lp = netdev_priv(dev);
0341
0342     /* XXX - leak? */
0343     MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);
0344     if (MEM == NULL) {
0345 #ifdef CONFIG_SUN3
0346         iounmap((void __iomem *)ioaddr);
0347 #endif
0348         printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n");
0349         return 0;
0350     }
0351
0352     lp->iobase = (volatile unsigned short *)ioaddr;
0353     dev->base_addr = (unsigned long)ioaddr; /* informational only */
0354
0355     REGA(CSR0) = CSR0_STOP;
0356
0357     if (request_irq(LANCE_IRQ, lance_interrupt, 0, "SUN3 Lance", dev) < 0) {
0358 #ifdef CONFIG_SUN3
0359         iounmap((void __iomem *)ioaddr);
0360 #endif
0361         dvma_free((void *)MEM);
0362         printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n");
0363         return 0;
0364     }
0365     dev->irq = (unsigned short)LANCE_IRQ;
0366
0367
0368     printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ",
0369            dev->name,
0370            (unsigned long)ioaddr,
0371            (unsigned long)MEM,
0372            dev->irq);
0373
0374     /* copy in the ethernet address from the prom */
0375     eth_hw_addr_set(dev, idprom->id_ethaddr);
0376
0377     /* tell the card it's ether address, bytes swapped */
0378     MEM->init.hwaddr[0] = dev->dev_addr[1];
0379     MEM->init.hwaddr[1] = dev->dev_addr[0];
0380     MEM->init.hwaddr[2] = dev->dev_addr[3];
0381     MEM->init.hwaddr[3] = dev->dev_addr[2];
0382     MEM->init.hwaddr[4] = dev->dev_addr[5];
0383     MEM->init.hwaddr[5] = dev->dev_addr[4];
0384
0385     printk("%pM\n", dev->dev_addr);
0386
0387     MEM->init.mode = 0x0000;
0388     MEM->init.filter[0] = 0x00000000;
0389     MEM->init.filter[1] = 0x00000000;
0390     MEM->init.rdra = dvma_vtob(MEM->rx_head);
0391     MEM->init.rlen    = (RX_LOG_RING_SIZE << 13) |
0392         (dvma_vtob(MEM->rx_head) >> 16);
0393     MEM->init.tdra = dvma_vtob(MEM->tx_head);
0394     MEM->init.tlen    = (TX_LOG_RING_SIZE << 13) |
0395         (dvma_vtob(MEM->tx_head) >> 16);
0396
0397     DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n",
0398            dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head),
0399            (dvma_vtob(MEM->tx_head))));
0400
0401     if (did_version++ == 0)
0402         printk( version );
0403
0404     dev->netdev_ops = &lance_netdev_ops;
0405 //  KLUDGE -- REMOVE ME
0406     set_bit(__LINK_STATE_PRESENT, &dev->state);
0407
0408
0409     return 1;
0410 }
0411
0412 static int lance_open( struct net_device *dev )
0413 {
0414     struct lance_private *lp = netdev_priv(dev);
0415     int i;
0416
0417     DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
0418
0419     REGA(CSR0) = CSR0_STOP;
0420
0421     lance_init_ring(dev);
0422
0423     /* From now on, AREG is kept to point to CSR0 */
0424     REGA(CSR0) = CSR0_INIT;
0425
0426     i = 1000000;
0427     while (--i > 0)
0428         if (DREG & CSR0_IDON)
0429             break;
0430     if (i <= 0 || (DREG & CSR0_ERR)) {
0431         DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
0432                       dev->name, i, DREG ));
0433         DREG = CSR0_STOP;
0434         return -EIO;
0435     }
0436
0437     DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA;
0438
0439     netif_start_queue(dev);
0440
0441     DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
0442
0443     return 0;
0444 }
0445
0446
0447 /* Initialize the LANCE Rx and Tx rings. */
0448
0449 static void lance_init_ring( struct net_device *dev )
0450 {
0451     struct lance_private *lp = netdev_priv(dev);
0452     int i;
0453
0454     lp->lock = 0;
0455     lp->tx_full = 0;
0456     lp->new_rx = lp->new_tx = 0;
0457     lp->old_rx = lp->old_tx = 0;
0458
0459     for( i = 0; i < TX_RING_SIZE; i++ ) {
0460         MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]);
0461         MEM->tx_head[i].flag = 0;
0462         MEM->tx_head[i].base_hi =
0463             (dvma_vtob(MEM->tx_data[i])) >>16;
0464         MEM->tx_head[i].length = 0;
0465         MEM->tx_head[i].misc = 0;
0466     }
0467
0468     for( i = 0; i < RX_RING_SIZE; i++ ) {
0469         MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]);
0470         MEM->rx_head[i].flag = RMD1_OWN_CHIP;
0471         MEM->rx_head[i].base_hi =
0472             (dvma_vtob(MEM->rx_data[i])) >> 16;
0473         MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;
0474         MEM->rx_head[i].msg_length = 0;
0475     }
0476
0477     /* tell the card it's ether address, bytes swapped */
0478     MEM->init.hwaddr[0] = dev->dev_addr[1];
0479     MEM->init.hwaddr[1] = dev->dev_addr[0];
0480     MEM->init.hwaddr[2] = dev->dev_addr[3];
0481     MEM->init.hwaddr[3] = dev->dev_addr[2];
0482     MEM->init.hwaddr[4] = dev->dev_addr[5];
0483     MEM->init.hwaddr[5] = dev->dev_addr[4];
0484
0485     MEM->init.mode = 0x0000;
0486     MEM->init.filter[0] = 0x00000000;
0487     MEM->init.filter[1] = 0x00000000;
0488     MEM->init.rdra = dvma_vtob(MEM->rx_head);
0489     MEM->init.rlen    = (RX_LOG_RING_SIZE << 13) |
0490         (dvma_vtob(MEM->rx_head) >> 16);
0491     MEM->init.tdra = dvma_vtob(MEM->tx_head);
0492     MEM->init.tlen    = (TX_LOG_RING_SIZE << 13) |
0493         (dvma_vtob(MEM->tx_head) >> 16);
0494
0495
0496     /* tell the lance the address of its init block */
0497     REGA(CSR1) = dvma_vtob(&(MEM->init));
0498     REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
0499
0500 #ifdef CONFIG_SUN3X
0501     REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
0502 #else
0503     REGA(CSR3) = CSR3_BSWP;
0504 #endif
0505
0506 }
0507
0508
0509 static netdev_tx_t
0510 lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
0511 {
0512     struct lance_private *lp = netdev_priv(dev);
0513     int entry, len;
0514     struct lance_tx_head *head;
0515     unsigned long flags;
0516
0517     DPRINTK( 1, ( "%s: transmit start.\n",
0518               dev->name));
0519
0520     /* Transmitter timeout, serious problems. */
0521     if (netif_queue_stopped(dev)) {
0522         int tickssofar = jiffies - dev_trans_start(dev);
0523         if (tickssofar < HZ/5)
0524             return NETDEV_TX_BUSY;
0525
0526         DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
0527                       dev->name, DREG ));
0528         DREG = CSR0_STOP;
0529         /*
0530          * Always set BSWP after a STOP as STOP puts it back into
0531          * little endian mode.
0532          */
0533         REGA(CSR3) = CSR3_BSWP;
0534         dev->stats.tx_errors++;
0535
0536         if(lance_debug >= 2) {
0537             int i;
0538             printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n",
0539                    lp->old_tx, lp->new_tx,
0540                    lp->tx_full ? " (full)" : "",
0541                    lp->new_rx );
0542             for( i = 0 ; i < RX_RING_SIZE; i++ )
0543                 printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
0544                     i, MEM->rx_head[i].base,
0545                     -MEM->rx_head[i].buf_length,
0546                     MEM->rx_head[i].msg_length);
0547             for( i = 0 ; i < TX_RING_SIZE; i++ )
0548                 printk("tx #%d: base=%04x len=%04x misc=%04x\n",
0549                        i, MEM->tx_head[i].base,
0550                        -MEM->tx_head[i].length,
0551                        MEM->tx_head[i].misc );
0552         }
0553
0554         lance_init_ring(dev);
0555         REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
0556
0557         netif_start_queue(dev);
0558
0559         return NETDEV_TX_OK;
0560     }
0561
0562
0563     /* Block a timer-based transmit from overlapping.  This could better be
0564        done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
0565
0566     /* Block a timer-based transmit from overlapping with us by
0567        stopping the queue for a bit... */
0568
0569     netif_stop_queue(dev);
0570
0571     if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
0572         printk( "%s: tx queue lock!.\n", dev->name);
0573         /* don't clear dev->tbusy flag. */
0574         return NETDEV_TX_BUSY;
0575     }
0576
0577     AREG = CSR0;
0578     DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
0579                   dev->name, DREG ));
0580
0581 #ifdef CONFIG_SUN3X
0582     /* this weirdness doesn't appear on sun3... */
0583     if(!(DREG & CSR0_INIT)) {
0584         DPRINTK( 1, ("INIT not set, reinitializing...\n"));
0585         REGA( CSR0 ) = CSR0_STOP;
0586         lance_init_ring(dev);
0587         REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
0588     }
0589 #endif
0590
0591     /* Fill in a Tx ring entry */
0592 #if 0
0593     if (lance_debug >= 2) {
0594         printk( "%s: TX pkt %d type 0x%04x"
0595             " from %s to %s"
0596             " data at 0x%08x len %d\n",
0597             dev->name, lp->new_tx, ((u_short *)skb->data)[6],
0598             DEV_ADDR(&skb->data[6]), DEV_ADDR(skb->data),
0599             (int)skb->data, (int)skb->len );
0600     }
0601 #endif
0602     /* We're not prepared for the int until the last flags are set/reset.
0603      * And the int may happen already after setting the OWN_CHIP... */
0604     local_irq_save(flags);
0605
0606     /* Mask to ring buffer boundary. */
0607     entry = lp->new_tx;
0608     head  = &(MEM->tx_head[entry]);
0609
0610     /* Caution: the write order is important here, set the "ownership" bits
0611      * last.
0612      */
0613
0614     /* the sun3's lance needs it's buffer padded to the minimum
0615        size */
0616     len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
0617
0618 //  head->length = -len;
0619     head->length = (-len) | 0xf000;
0620     head->misc = 0;
0621
0622     skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), skb->len);
0623     if (len != skb->len)
0624         memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len);
0625
0626     head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
0627     lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK;
0628     dev->stats.tx_bytes += skb->len;
0629
0630     /* Trigger an immediate send poll. */
0631     REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
0632     AREG = CSR0;
0633     DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n",
0634                   dev->name, DREG ));
0635     dev_kfree_skb(skb);
0636
0637     lp->lock = 0;
0638     if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
0639         TMD1_OWN_HOST)
0640         netif_start_queue(dev);
0641
0642     local_irq_restore(flags);
0643
0644     return NETDEV_TX_OK;
0645 }
0646
0647 /* The LANCE interrupt handler. */
0648
0649 static irqreturn_t lance_interrupt( int irq, void *dev_id)
0650 {
0651     struct net_device *dev = dev_id;
0652     struct lance_private *lp = netdev_priv(dev);
0653     int csr0;
0654
0655  still_more:
0656     flush_cache_all();
0657
0658     AREG = CSR0;
0659     csr0 = DREG;
0660
0661     /* ack interrupts */
0662     DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON);
0663
0664     /* clear errors */
0665     if(csr0 & CSR0_ERR)
0666         DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS;
0667
0668
0669     DPRINTK( 2, ( "%s: interrupt  csr0=%04x new csr=%04x.\n",
0670               dev->name, csr0, DREG ));
0671
0672     if (csr0 & CSR0_TINT) {         /* Tx-done interrupt */
0673         int old_tx = lp->old_tx;
0674
0675 //      if(lance_debug >= 3) {
0676 //          int i;
0677 //
0678 //          printk("%s: tx int\n", dev->name);
0679 //
0680 //          for(i = 0; i < TX_RING_SIZE; i++)
0681 //              printk("ring %d flag=%04x\n", i,
0682 //                     MEM->tx_head[i].flag);
0683 //      }
0684
0685         while( old_tx != lp->new_tx) {
0686             struct lance_tx_head *head = &(MEM->tx_head[old_tx]);
0687
0688             DPRINTK(3, ("on tx_ring %d\n", old_tx));
0689
0690             if (head->flag & TMD1_OWN_CHIP)
0691                 break; /* It still hasn't been Txed */
0692
0693             if (head->flag & TMD1_ERR) {
0694                 int status = head->misc;
0695                 dev->stats.tx_errors++;
0696                 if (status & TMD3_RTRY) dev->stats.tx_aborted_errors++;
0697                 if (status & TMD3_LCAR) dev->stats.tx_carrier_errors++;
0698                 if (status & TMD3_LCOL) dev->stats.tx_window_errors++;
0699                 if (status & (TMD3_UFLO | TMD3_BUFF)) {
0700                     dev->stats.tx_fifo_errors++;
0701                     printk("%s: Tx FIFO error\n",
0702                            dev->name);
0703                     REGA(CSR0) = CSR0_STOP;
0704                     REGA(CSR3) = CSR3_BSWP;
0705                     lance_init_ring(dev);
0706                     REGA(CSR0) = CSR0_STRT | CSR0_INEA;
0707                     return IRQ_HANDLED;
0708                 }
0709             } else if(head->flag & (TMD1_ENP | TMD1_STP)) {
0710
0711                 head->flag &= ~(TMD1_ENP | TMD1_STP);
0712                 if(head->flag & (TMD1_ONE | TMD1_MORE))
0713                     dev->stats.collisions++;
0714
0715                 dev->stats.tx_packets++;
0716                 DPRINTK(3, ("cleared tx ring %d\n", old_tx));
0717             }
0718             old_tx = (old_tx +1) & TX_RING_MOD_MASK;
0719         }
0720
0721         lp->old_tx = old_tx;
0722     }
0723
0724
0725     if (netif_queue_stopped(dev)) {
0726         /* The ring is no longer full, clear tbusy. */
0727         netif_start_queue(dev);
0728         netif_wake_queue(dev);
0729     }
0730
0731     if (csr0 & CSR0_RINT)           /* Rx interrupt */
0732         lance_rx( dev );
0733
0734     /* Log misc errors. */
0735     if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */
0736     if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */
0737     if (csr0 & CSR0_MERR) {
0738         DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
0739                   "status %04x.\n", dev->name, csr0 ));
0740         /* Restart the chip. */
0741         REGA(CSR0) = CSR0_STOP;
0742         REGA(CSR3) = CSR3_BSWP;
0743         lance_init_ring(dev);
0744         REGA(CSR0) = CSR0_STRT | CSR0_INEA;
0745     }
0746
0747
0748     /* Clear any other interrupt, and set interrupt enable. */
0749 //  DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
0750 //         CSR0_IDON | CSR0_INEA;
0751
0752     REGA(CSR0) = CSR0_INEA;
0753
0754     if(DREG & (CSR0_RINT | CSR0_TINT)) {
0755          DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG));
0756          goto still_more;
0757     }
0758
0759     DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
0760                   dev->name, DREG ));
0761     return IRQ_HANDLED;
0762 }
0763
0764 /* get packet, toss into skbuff */
0765 static int lance_rx( struct net_device *dev )
0766 {
0767     struct lance_private *lp = netdev_priv(dev);
0768     int entry = lp->new_rx;
0769
0770     /* If we own the next entry, it's a new packet. Send it up. */
0771     while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
0772         struct lance_rx_head *head = &(MEM->rx_head[entry]);
0773         int status = head->flag;
0774
0775         if (status != (RMD1_ENP|RMD1_STP)) {  /* There was an error. */
0776             /* There is a tricky error noted by John Murphy,
0777                <murf@perftech.com> to Russ Nelson: Even with
0778                full-sized buffers it's possible for a jabber packet to use two
0779                buffers, with only the last correctly noting the error. */
0780             if (status & RMD1_ENP)  /* Only count a general error at the */
0781                 dev->stats.rx_errors++; /* end of a packet.*/
0782             if (status & RMD1_FRAM) dev->stats.rx_frame_errors++;
0783             if (status & RMD1_OFLO) dev->stats.rx_over_errors++;
0784             if (status & RMD1_CRC) dev->stats.rx_crc_errors++;
0785             if (status & RMD1_BUFF) dev->stats.rx_fifo_errors++;
0786             head->flag &= (RMD1_ENP|RMD1_STP);
0787         } else {
0788             /* Malloc up new buffer, compatible with net-3. */
0789 //          short pkt_len = head->msg_length;// & 0xfff;
0790             short pkt_len = (head->msg_length & 0xfff) - 4;
0791             struct sk_buff *skb;
0792
0793             if (pkt_len < 60) {
0794                 printk( "%s: Runt packet!\n", dev->name );
0795                 dev->stats.rx_errors++;
0796             }
0797             else {
0798                 skb = netdev_alloc_skb(dev, pkt_len + 2);
0799                 if (skb == NULL) {
0800                     dev->stats.rx_dropped++;
0801                     head->msg_length = 0;
0802                     head->flag |= RMD1_OWN_CHIP;
0803                     lp->new_rx = (lp->new_rx+1) &
0804                          RX_RING_MOD_MASK;
0805                 }
0806
0807 #if 0
0808                 if (lance_debug >= 3) {
0809                     u_char *data = PKTBUF_ADDR(head);
0810                     printk("%s: RX pkt %d type 0x%04x"
0811                            " from %pM to %pM",
0812                            dev->name, lp->new_tx, ((u_short *)data)[6],
0813                            &data[6], data);
0814
0815                     printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
0816                            "len %d at %08x\n",
0817                            data[15], data[16], data[17], data[18],
0818                            data[19], data[20], data[21], data[22],
0819                            pkt_len, data);
0820                 }
0821 #endif
0822                 if (lance_debug >= 3) {
0823                     u_char *data = PKTBUF_ADDR(head);
0824                     printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len);
0825                 }
0826
0827
0828                 skb_reserve( skb, 2 );  /* 16 byte align */
0829                 skb_put( skb, pkt_len );    /* Make room */
0830                 skb_copy_to_linear_data(skb,
0831                          PKTBUF_ADDR(head),
0832                          pkt_len);
0833
0834                 skb->protocol = eth_type_trans( skb, dev );
0835                 netif_rx( skb );
0836                 dev->stats.rx_packets++;
0837                 dev->stats.rx_bytes += pkt_len;
0838             }
0839         }
0840
0841 //      head->buf_length = -PKT_BUF_SZ | 0xf000;
0842         head->msg_length = 0;
0843         head->flag = RMD1_OWN_CHIP;
0844
0845         entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK;
0846     }
0847
0848     /* From lance.c (Donald Becker): */
0849     /* We should check that at least two ring entries are free.
0850        If not, we should free one and mark stats->rx_dropped++. */
0851
0852     return 0;
0853 }
0854
0855
0856 static int lance_close( struct net_device *dev )
0857 {
0858     struct lance_private *lp = netdev_priv(dev);
0859
0860     netif_stop_queue(dev);
0861
0862     AREG = CSR0;
0863
0864     DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
0865                   dev->name, DREG ));
0866
0867     /* We stop the LANCE here -- it occasionally polls
0868        memory if we don't. */
0869     DREG = CSR0_STOP;
0870     return 0;
0871 }
0872
0873
0874 /* Set or clear the multicast filter for this adaptor.
0875    num_addrs == -1      Promiscuous mode, receive all packets
0876    num_addrs == 0       Normal mode, clear multicast list
0877    num_addrs > 0        Multicast mode, receive normal and MC packets, and do
0878                         best-effort filtering.
0879  */
0880
0881 /* completely untested on a sun3 */
0882 static void set_multicast_list( struct net_device *dev )
0883 {
0884     struct lance_private *lp = netdev_priv(dev);
0885
0886     if(netif_queue_stopped(dev))
0887         /* Only possible if board is already started */
0888         return;
0889
0890     /* We take the simple way out and always enable promiscuous mode. */
0891     DREG = CSR0_STOP; /* Temporarily stop the lance. */
0892
0893     if (dev->flags & IFF_PROMISC) {
0894         /* Log any net taps. */
0895         DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n", dev->name ));
0896         REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
0897     } else {
0898         short multicast_table[4];
0899         int num_addrs = netdev_mc_count(dev);
0900         int i;
0901         /* We don't use the multicast table, but rely on upper-layer
0902          * filtering. */
0903         memset( multicast_table, (num_addrs == 0) ? 0 : -1,
0904                 sizeof(multicast_table) );
0905         for( i = 0; i < 4; i++ )
0906             REGA( CSR8+i ) = multicast_table[i];
0907         REGA( CSR15 ) = 0; /* Unset promiscuous mode */
0908     }
0909
0910     /*
0911      * Always set BSWP after a STOP as STOP puts it back into
0912      * little endian mode.
0913      */
0914     REGA( CSR3 ) = CSR3_BSWP;
0915
0916     /* Resume normal operation and reset AREG to CSR0 */
0917     REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
0918 }
0919
0920
0921 static struct net_device *sun3lance_dev;
0922
0923 static int __init sun3lance_init(void)
0924 {
0925     sun3lance_dev = sun3lance_probe();
0926     return PTR_ERR_OR_ZERO(sun3lance_dev);
0927 }
0928 module_init(sun3lance_init);
0929
0930 static void __exit sun3lance_cleanup(void)
0931 {
0932     unregister_netdev(sun3lance_dev);
0933 #ifdef CONFIG_SUN3
0934     iounmap((void __iomem *)sun3lance_dev->base_addr);
0935 #endif
0936     free_netdev(sun3lance_dev);
0937 }
0938 module_exit(sun3lance_cleanup);