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0001 /* ----------------------------------------------------------------------------
0002 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
0003   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
0004 
0005   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
0006   Access Controller for Ethernet (MACE).  It is essentially the Am2150
0007   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
0008 
0009 Written by Roger C. Pao <rpao@paonet.org>
0010   Copyright 1995 Roger C. Pao
0011   Linux 2.5 cleanups Copyright Red Hat 2003
0012 
0013   This software may be used and distributed according to the terms of
0014   the GNU General Public License.
0015 
0016 Ported to Linux 1.3.* network driver environment by
0017   Matti Aarnio <mea@utu.fi>
0018 
0019 References
0020 
0021   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
0022   Am79C940 (MACE) Data Sheet, 1994
0023   Am79C90 (C-LANCE) Data Sheet, 1994
0024   Linux PCMCIA Programmer's Guide v1.17
0025   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
0026 
0027   Eric Mears, New Media Corporation
0028   Tom Pollard, New Media Corporation
0029   Dean Siasoyco, New Media Corporation
0030   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
0031   Donald Becker <becker@scyld.com>
0032   David Hinds <dahinds@users.sourceforge.net>
0033 
0034   The Linux client driver is based on the 3c589_cs.c client driver by
0035   David Hinds.
0036 
0037   The Linux network driver outline is based on the 3c589_cs.c driver,
0038   the 8390.c driver, and the example skeleton.c kernel code, which are
0039   by Donald Becker.
0040 
0041   The Am2150 network driver hardware interface code is based on the
0042   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
0043 
0044   Special thanks for testing and help in debugging this driver goes
0045   to Ken Lesniak.
0046 
0047 -------------------------------------------------------------------------------
0048 Driver Notes and Issues
0049 -------------------------------------------------------------------------------
0050 
0051 1. Developed on a Dell 320SLi
0052    PCMCIA Card Services 2.6.2
0053    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
0054 
0055 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
0056    'insmod pcmcia_core.o io_speed=300'.
0057    This will avoid problems with fast systems which causes rx_framecnt
0058    to return random values.
0059 
0060 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
0061    before extraction.
0062 
0063 4. There is a bad slow-down problem in this driver.
0064 
0065 5. Future: Multicast processing.  In the meantime, do _not_ compile your
0066    kernel with multicast ip enabled.
0067 
0068 -------------------------------------------------------------------------------
0069 History
0070 -------------------------------------------------------------------------------
0071 Log: nmclan_cs.c,v
0072  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
0073  * Fixed hang on card eject as we probe it
0074  * Cleaned up to use new style locking.
0075  *
0076  * Revision 0.16  1995/07/01  06:42:17  rpao
0077  * Bug fix: nmclan_reset() called CardServices incorrectly.
0078  *
0079  * Revision 0.15  1995/05/24  08:09:47  rpao
0080  * Re-implement MULTI_TX dev->tbusy handling.
0081  *
0082  * Revision 0.14  1995/05/23  03:19:30  rpao
0083  * Added, in nmclan_config(), "tuple.Attributes = 0;".
0084  * Modified MACE ID check to ignore chip revision level.
0085  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
0086  *
0087  * Revision 0.13  1995/05/18  05:56:34  rpao
0088  * Statistics changes.
0089  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
0090  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
0091  *
0092  * Revision 0.12  1995/05/14  00:12:23  rpao
0093  * Statistics overhaul.
0094  *
0095 
0096 95/05/13 rpao   V0.10a
0097         Bug fix: MACE statistics counters used wrong I/O ports.
0098         Bug fix: mace_interrupt() needed to allow statistics to be
0099         processed without RX or TX interrupts pending.
0100 95/05/11 rpao   V0.10
0101         Multiple transmit request processing.
0102         Modified statistics to use MACE counters where possible.
0103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
0104         *Released
0105 95/05/10 rpao   V0.08
0106         Bug fix: Make all non-exported functions private by using
0107         static keyword.
0108         Bug fix: Test IntrCnt _before_ reading MACE_IR.
0109 95/05/10 rpao   V0.07 Statistics.
0110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
0111 
0112 ---------------------------------------------------------------------------- */
0113 
0114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0115 
0116 #define DRV_NAME    "nmclan_cs"
0117 
0118 /* ----------------------------------------------------------------------------
0119 Conditional Compilation Options
0120 ---------------------------------------------------------------------------- */
0121 
0122 #define MULTI_TX            0
0123 #define RESET_ON_TIMEOUT        1
0124 #define TX_INTERRUPTABLE        1
0125 #define RESET_XILINX            0
0126 
0127 /* ----------------------------------------------------------------------------
0128 Include Files
0129 ---------------------------------------------------------------------------- */
0130 
0131 #include <linux/module.h>
0132 #include <linux/kernel.h>
0133 #include <linux/ptrace.h>
0134 #include <linux/slab.h>
0135 #include <linux/string.h>
0136 #include <linux/timer.h>
0137 #include <linux/interrupt.h>
0138 #include <linux/in.h>
0139 #include <linux/delay.h>
0140 #include <linux/ethtool.h>
0141 #include <linux/netdevice.h>
0142 #include <linux/etherdevice.h>
0143 #include <linux/skbuff.h>
0144 #include <linux/if_arp.h>
0145 #include <linux/ioport.h>
0146 #include <linux/bitops.h>
0147 
0148 #include <pcmcia/cisreg.h>
0149 #include <pcmcia/cistpl.h>
0150 #include <pcmcia/ds.h>
0151 
0152 #include <linux/uaccess.h>
0153 #include <asm/io.h>
0154 
0155 /* ----------------------------------------------------------------------------
0156 Defines
0157 ---------------------------------------------------------------------------- */
0158 
0159 #define MACE_LADRF_LEN          8
0160                     /* 8 bytes in Logical Address Filter */
0161 
0162 /* Loop Control Defines */
0163 #define MACE_MAX_IR_ITERATIONS      10
0164 #define MACE_MAX_RX_ITERATIONS      12
0165     /*
0166     TBD: Dean brought this up, and I assumed the hardware would
0167     handle it:
0168 
0169     If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
0170     non-zero when the isr exits.  We may not get another interrupt
0171     to process the remaining packets for some time.
0172     */
0173 
0174 /*
0175 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
0176 which manages the interface between the MACE and the PCMCIA bus.  It
0177 also includes buffer management for the 32K x 8 SRAM to control up to
0178 four transmit and 12 receive frames at a time.
0179 */
0180 #define AM2150_MAX_TX_FRAMES        4
0181 #define AM2150_MAX_RX_FRAMES        12
0182 
0183 /* Am2150 Ethernet Card I/O Mapping */
0184 #define AM2150_RCV          0x00
0185 #define AM2150_XMT          0x04
0186 #define AM2150_XMT_SKIP         0x09
0187 #define AM2150_RCV_NEXT         0x0A
0188 #define AM2150_RCV_FRAME_COUNT      0x0B
0189 #define AM2150_MACE_BANK        0x0C
0190 #define AM2150_MACE_BASE        0x10
0191 
0192 /* MACE Registers */
0193 #define MACE_RCVFIFO            0
0194 #define MACE_XMTFIFO            1
0195 #define MACE_XMTFC          2
0196 #define MACE_XMTFS          3
0197 #define MACE_XMTRC          4
0198 #define MACE_RCVFC          5
0199 #define MACE_RCVFS          6
0200 #define MACE_FIFOFC         7
0201 #define MACE_IR             8
0202 #define MACE_IMR            9
0203 #define MACE_PR             10
0204 #define MACE_BIUCC          11
0205 #define MACE_FIFOCC         12
0206 #define MACE_MACCC          13
0207 #define MACE_PLSCC          14
0208 #define MACE_PHYCC          15
0209 #define MACE_CHIPIDL            16
0210 #define MACE_CHIPIDH            17
0211 #define MACE_IAC            18
0212 /* Reserved */
0213 #define MACE_LADRF          20
0214 #define MACE_PADR           21
0215 /* Reserved */
0216 /* Reserved */
0217 #define MACE_MPC            24
0218 /* Reserved */
0219 #define MACE_RNTPC          26
0220 #define MACE_RCVCC          27
0221 /* Reserved */
0222 #define MACE_UTR            29
0223 #define MACE_RTR1           30
0224 #define MACE_RTR2           31
0225 
0226 /* MACE Bit Masks */
0227 #define MACE_XMTRC_EXDEF        0x80
0228 #define MACE_XMTRC_XMTRC        0x0F
0229 
0230 #define MACE_XMTFS_XMTSV        0x80
0231 #define MACE_XMTFS_UFLO         0x40
0232 #define MACE_XMTFS_LCOL         0x20
0233 #define MACE_XMTFS_MORE         0x10
0234 #define MACE_XMTFS_ONE          0x08
0235 #define MACE_XMTFS_DEFER        0x04
0236 #define MACE_XMTFS_LCAR         0x02
0237 #define MACE_XMTFS_RTRY         0x01
0238 
0239 #define MACE_RCVFS_RCVSTS       0xF000
0240 #define MACE_RCVFS_OFLO         0x8000
0241 #define MACE_RCVFS_CLSN         0x4000
0242 #define MACE_RCVFS_FRAM         0x2000
0243 #define MACE_RCVFS_FCS          0x1000
0244 
0245 #define MACE_FIFOFC_RCVFC       0xF0
0246 #define MACE_FIFOFC_XMTFC       0x0F
0247 
0248 #define MACE_IR_JAB         0x80
0249 #define MACE_IR_BABL            0x40
0250 #define MACE_IR_CERR            0x20
0251 #define MACE_IR_RCVCCO          0x10
0252 #define MACE_IR_RNTPCO          0x08
0253 #define MACE_IR_MPCO            0x04
0254 #define MACE_IR_RCVINT          0x02
0255 #define MACE_IR_XMTINT          0x01
0256 
0257 #define MACE_MACCC_PROM         0x80
0258 #define MACE_MACCC_DXMT2PD      0x40
0259 #define MACE_MACCC_EMBA         0x20
0260 #define MACE_MACCC_RESERVED     0x10
0261 #define MACE_MACCC_DRCVPA       0x08
0262 #define MACE_MACCC_DRCVBC       0x04
0263 #define MACE_MACCC_ENXMT        0x02
0264 #define MACE_MACCC_ENRCV        0x01
0265 
0266 #define MACE_PHYCC_LNKFL        0x80
0267 #define MACE_PHYCC_DLNKTST      0x40
0268 #define MACE_PHYCC_REVPOL       0x20
0269 #define MACE_PHYCC_DAPC         0x10
0270 #define MACE_PHYCC_LRT          0x08
0271 #define MACE_PHYCC_ASEL         0x04
0272 #define MACE_PHYCC_RWAKE        0x02
0273 #define MACE_PHYCC_AWAKE        0x01
0274 
0275 #define MACE_IAC_ADDRCHG        0x80
0276 #define MACE_IAC_PHYADDR        0x04
0277 #define MACE_IAC_LOGADDR        0x02
0278 
0279 #define MACE_UTR_RTRE           0x80
0280 #define MACE_UTR_RTRD           0x40
0281 #define MACE_UTR_RPA            0x20
0282 #define MACE_UTR_FCOLL          0x10
0283 #define MACE_UTR_RCVFCSE        0x08
0284 #define MACE_UTR_LOOP_INCL_MENDEC   0x06
0285 #define MACE_UTR_LOOP_NO_MENDEC     0x04
0286 #define MACE_UTR_LOOP_EXTERNAL      0x02
0287 #define MACE_UTR_LOOP_NONE      0x00
0288 #define MACE_UTR_RESERVED       0x01
0289 
0290 /* Switch MACE register bank (only 0 and 1 are valid) */
0291 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
0292 
0293 #define MACE_IMR_DEFAULT \
0294   (0xFF - \
0295     ( \
0296       MACE_IR_CERR | \
0297       MACE_IR_RCVCCO | \
0298       MACE_IR_RNTPCO | \
0299       MACE_IR_MPCO | \
0300       MACE_IR_RCVINT | \
0301       MACE_IR_XMTINT \
0302     ) \
0303   )
0304 #undef MACE_IMR_DEFAULT
0305 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
0306 
0307 #define TX_TIMEOUT      ((400*HZ)/1000)
0308 
0309 /* ----------------------------------------------------------------------------
0310 Type Definitions
0311 ---------------------------------------------------------------------------- */
0312 
0313 typedef struct _mace_statistics {
0314     /* MACE_XMTFS */
0315     int xmtsv;
0316     int uflo;
0317     int lcol;
0318     int more;
0319     int one;
0320     int defer;
0321     int lcar;
0322     int rtry;
0323 
0324     /* MACE_XMTRC */
0325     int exdef;
0326     int xmtrc;
0327 
0328     /* RFS1--Receive Status (RCVSTS) */
0329     int oflo;
0330     int clsn;
0331     int fram;
0332     int fcs;
0333 
0334     /* RFS2--Runt Packet Count (RNTPC) */
0335     int rfs_rntpc;
0336 
0337     /* RFS3--Receive Collision Count (RCVCC) */
0338     int rfs_rcvcc;
0339 
0340     /* MACE_IR */
0341     int jab;
0342     int babl;
0343     int cerr;
0344     int rcvcco;
0345     int rntpco;
0346     int mpco;
0347 
0348     /* MACE_MPC */
0349     int mpc;
0350 
0351     /* MACE_RNTPC */
0352     int rntpc;
0353 
0354     /* MACE_RCVCC */
0355     int rcvcc;
0356 } mace_statistics;
0357 
0358 typedef struct _mace_private {
0359     struct pcmcia_device    *p_dev;
0360     mace_statistics mace_stats; /* MACE chip statistics counters */
0361 
0362     /* restore_multicast_list() state variables */
0363     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
0364     int multicast_num_addrs;
0365 
0366     char tx_free_frames; /* Number of free transmit frame buffers */
0367     char tx_irq_disabled; /* MACE TX interrupt disabled */
0368 
0369     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
0370 } mace_private;
0371 
0372 /* ----------------------------------------------------------------------------
0373 Private Global Variables
0374 ---------------------------------------------------------------------------- */
0375 
0376 static const char *if_names[]={
0377     "Auto", "10baseT", "BNC",
0378 };
0379 
0380 /* ----------------------------------------------------------------------------
0381 Parameters
0382     These are the parameters that can be set during loading with
0383     'insmod'.
0384 ---------------------------------------------------------------------------- */
0385 
0386 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
0387 MODULE_LICENSE("GPL");
0388 
0389 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
0390 
0391 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
0392 INT_MODULE_PARM(if_port, 0);
0393 
0394 
0395 /* ----------------------------------------------------------------------------
0396 Function Prototypes
0397 ---------------------------------------------------------------------------- */
0398 
0399 static int nmclan_config(struct pcmcia_device *link);
0400 static void nmclan_release(struct pcmcia_device *link);
0401 
0402 static void nmclan_reset(struct net_device *dev);
0403 static int mace_config(struct net_device *dev, struct ifmap *map);
0404 static int mace_open(struct net_device *dev);
0405 static int mace_close(struct net_device *dev);
0406 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
0407                      struct net_device *dev);
0408 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue);
0409 static irqreturn_t mace_interrupt(int irq, void *dev_id);
0410 static struct net_device_stats *mace_get_stats(struct net_device *dev);
0411 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
0412 static void restore_multicast_list(struct net_device *dev);
0413 static void set_multicast_list(struct net_device *dev);
0414 static const struct ethtool_ops netdev_ethtool_ops;
0415 
0416 
0417 static void nmclan_detach(struct pcmcia_device *p_dev);
0418 
0419 static const struct net_device_ops mace_netdev_ops = {
0420     .ndo_open       = mace_open,
0421     .ndo_stop       = mace_close,
0422     .ndo_start_xmit     = mace_start_xmit,
0423     .ndo_tx_timeout     = mace_tx_timeout,
0424     .ndo_set_config     = mace_config,
0425     .ndo_get_stats      = mace_get_stats,
0426     .ndo_set_rx_mode    = set_multicast_list,
0427     .ndo_set_mac_address    = eth_mac_addr,
0428     .ndo_validate_addr  = eth_validate_addr,
0429 };
0430 
0431 static int nmclan_probe(struct pcmcia_device *link)
0432 {
0433     mace_private *lp;
0434     struct net_device *dev;
0435 
0436     dev_dbg(&link->dev, "nmclan_attach()\n");
0437 
0438     /* Create new ethernet device */
0439     dev = alloc_etherdev(sizeof(mace_private));
0440     if (!dev)
0441         return -ENOMEM;
0442     lp = netdev_priv(dev);
0443     lp->p_dev = link;
0444     link->priv = dev;
0445 
0446     spin_lock_init(&lp->bank_lock);
0447     link->resource[0]->end = 32;
0448     link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
0449     link->config_flags |= CONF_ENABLE_IRQ;
0450     link->config_index = 1;
0451     link->config_regs = PRESENT_OPTION;
0452 
0453     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
0454 
0455     dev->netdev_ops = &mace_netdev_ops;
0456     dev->ethtool_ops = &netdev_ethtool_ops;
0457     dev->watchdog_timeo = TX_TIMEOUT;
0458 
0459     return nmclan_config(link);
0460 } /* nmclan_attach */
0461 
0462 static void nmclan_detach(struct pcmcia_device *link)
0463 {
0464     struct net_device *dev = link->priv;
0465 
0466     dev_dbg(&link->dev, "nmclan_detach\n");
0467 
0468     unregister_netdev(dev);
0469 
0470     nmclan_release(link);
0471 
0472     free_netdev(dev);
0473 } /* nmclan_detach */
0474 
0475 /* ----------------------------------------------------------------------------
0476 mace_read
0477     Reads a MACE register.  This is bank independent; however, the
0478     caller must ensure that this call is not interruptable.  We are
0479     assuming that during normal operation, the MACE is always in
0480     bank 0.
0481 ---------------------------------------------------------------------------- */
0482 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
0483 {
0484   int data = 0xFF;
0485   unsigned long flags;
0486 
0487   switch (reg >> 4) {
0488     case 0: /* register 0-15 */
0489       data = inb(ioaddr + AM2150_MACE_BASE + reg);
0490       break;
0491     case 1: /* register 16-31 */
0492       spin_lock_irqsave(&lp->bank_lock, flags);
0493       MACEBANK(1);
0494       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
0495       MACEBANK(0);
0496       spin_unlock_irqrestore(&lp->bank_lock, flags);
0497       break;
0498   }
0499   return data & 0xFF;
0500 } /* mace_read */
0501 
0502 /* ----------------------------------------------------------------------------
0503 mace_write
0504     Writes to a MACE register.  This is bank independent; however,
0505     the caller must ensure that this call is not interruptable.  We
0506     are assuming that during normal operation, the MACE is always in
0507     bank 0.
0508 ---------------------------------------------------------------------------- */
0509 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
0510                int data)
0511 {
0512   unsigned long flags;
0513 
0514   switch (reg >> 4) {
0515     case 0: /* register 0-15 */
0516       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
0517       break;
0518     case 1: /* register 16-31 */
0519       spin_lock_irqsave(&lp->bank_lock, flags);
0520       MACEBANK(1);
0521       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
0522       MACEBANK(0);
0523       spin_unlock_irqrestore(&lp->bank_lock, flags);
0524       break;
0525   }
0526 } /* mace_write */
0527 
0528 /* ----------------------------------------------------------------------------
0529 mace_init
0530     Resets the MACE chip.
0531 ---------------------------------------------------------------------------- */
0532 static int mace_init(mace_private *lp, unsigned int ioaddr,
0533              const char *enet_addr)
0534 {
0535   int i;
0536   int ct = 0;
0537 
0538   /* MACE Software reset */
0539   mace_write(lp, ioaddr, MACE_BIUCC, 1);
0540   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
0541     /* Wait for reset bit to be cleared automatically after <= 200ns */;
0542     if(++ct > 500)
0543     {
0544     pr_err("reset failed, card removed?\n");
0545     return -1;
0546     }
0547     udelay(1);
0548   }
0549   mace_write(lp, ioaddr, MACE_BIUCC, 0);
0550 
0551   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
0552   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
0553 
0554   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
0555   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
0556 
0557   /*
0558    * Bit 2-1 PORTSEL[1-0] Port Select.
0559    * 00 AUI/10Base-2
0560    * 01 10Base-T
0561    * 10 DAI Port (reserved in Am2150)
0562    * 11 GPSI
0563    * For this card, only the first two are valid.
0564    * So, PLSCC should be set to
0565    * 0x00 for 10Base-2
0566    * 0x02 for 10Base-T
0567    * Or just set ASEL in PHYCC below!
0568    */
0569   switch (if_port) {
0570     case 1:
0571       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
0572       break;
0573     case 2:
0574       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
0575       break;
0576     default:
0577       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
0578       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
0579      and the MACE device will automatically select the operating media
0580      interface port. */
0581       break;
0582   }
0583 
0584   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
0585   /* Poll ADDRCHG bit */
0586   ct = 0;
0587   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
0588   {
0589     if(++ ct > 500)
0590     {
0591         pr_err("ADDRCHG timeout, card removed?\n");
0592         return -1;
0593     }
0594   }
0595   /* Set PADR register */
0596   for (i = 0; i < ETH_ALEN; i++)
0597     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
0598 
0599   /* MAC Configuration Control Register should be written last */
0600   /* Let set_multicast_list set this. */
0601   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
0602   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
0603   return 0;
0604 } /* mace_init */
0605 
0606 static int nmclan_config(struct pcmcia_device *link)
0607 {
0608   struct net_device *dev = link->priv;
0609   mace_private *lp = netdev_priv(dev);
0610   u8 *buf;
0611   size_t len;
0612   int i, ret;
0613   unsigned int ioaddr;
0614 
0615   dev_dbg(&link->dev, "nmclan_config\n");
0616 
0617   link->io_lines = 5;
0618   ret = pcmcia_request_io(link);
0619   if (ret)
0620       goto failed;
0621   ret = pcmcia_request_irq(link, mace_interrupt);
0622   if (ret)
0623       goto failed;
0624   ret = pcmcia_enable_device(link);
0625   if (ret)
0626       goto failed;
0627 
0628   dev->irq = link->irq;
0629   dev->base_addr = link->resource[0]->start;
0630 
0631   ioaddr = dev->base_addr;
0632 
0633   /* Read the ethernet address from the CIS. */
0634   len = pcmcia_get_tuple(link, 0x80, &buf);
0635   if (!buf || len < ETH_ALEN) {
0636       kfree(buf);
0637       goto failed;
0638   }
0639   eth_hw_addr_set(dev, buf);
0640   kfree(buf);
0641 
0642   /* Verify configuration by reading the MACE ID. */
0643   {
0644     char sig[2];
0645 
0646     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
0647     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
0648     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
0649       dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
0650         sig[0], sig[1]);
0651     } else {
0652       pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
0653         sig[0], sig[1]);
0654       return -ENODEV;
0655     }
0656   }
0657 
0658   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
0659     goto failed;
0660 
0661   /* The if_port symbol can be set when the module is loaded */
0662   if (if_port <= 2)
0663     dev->if_port = if_port;
0664   else
0665     pr_notice("invalid if_port requested\n");
0666 
0667   SET_NETDEV_DEV(dev, &link->dev);
0668 
0669   i = register_netdev(dev);
0670   if (i != 0) {
0671     pr_notice("register_netdev() failed\n");
0672     goto failed;
0673   }
0674 
0675   netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
0676           dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
0677   return 0;
0678 
0679 failed:
0680     nmclan_release(link);
0681     return -ENODEV;
0682 } /* nmclan_config */
0683 
0684 static void nmclan_release(struct pcmcia_device *link)
0685 {
0686     dev_dbg(&link->dev, "nmclan_release\n");
0687     pcmcia_disable_device(link);
0688 }
0689 
0690 static int nmclan_suspend(struct pcmcia_device *link)
0691 {
0692     struct net_device *dev = link->priv;
0693 
0694     if (link->open)
0695         netif_device_detach(dev);
0696 
0697     return 0;
0698 }
0699 
0700 static int nmclan_resume(struct pcmcia_device *link)
0701 {
0702     struct net_device *dev = link->priv;
0703 
0704     if (link->open) {
0705         nmclan_reset(dev);
0706         netif_device_attach(dev);
0707     }
0708 
0709     return 0;
0710 }
0711 
0712 
0713 /* ----------------------------------------------------------------------------
0714 nmclan_reset
0715     Reset and restore all of the Xilinx and MACE registers.
0716 ---------------------------------------------------------------------------- */
0717 static void nmclan_reset(struct net_device *dev)
0718 {
0719   mace_private *lp = netdev_priv(dev);
0720 
0721 #if RESET_XILINX
0722   struct pcmcia_device *link = &lp->link;
0723   u8 OrigCorValue;
0724 
0725   /* Save original COR value */
0726   pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
0727 
0728   /* Reset Xilinx */
0729   dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
0730     OrigCorValue);
0731   pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
0732   /* Need to wait for 20 ms for PCMCIA to finish reset. */
0733 
0734   /* Restore original COR configuration index */
0735   pcmcia_write_config_byte(link, CISREG_COR,
0736               (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
0737   /* Xilinx is now completely reset along with the MACE chip. */
0738   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
0739 
0740 #endif /* #if RESET_XILINX */
0741 
0742   /* Xilinx is now completely reset along with the MACE chip. */
0743   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
0744 
0745   /* Reinitialize the MACE chip for operation. */
0746   mace_init(lp, dev->base_addr, dev->dev_addr);
0747   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
0748 
0749   /* Restore the multicast list and enable TX and RX. */
0750   restore_multicast_list(dev);
0751 } /* nmclan_reset */
0752 
0753 /* ----------------------------------------------------------------------------
0754 mace_config
0755     [Someone tell me what this is supposed to do?  Is if_port a defined
0756     standard?  If so, there should be defines to indicate 1=10Base-T,
0757     2=10Base-2, etc. including limited automatic detection.]
0758 ---------------------------------------------------------------------------- */
0759 static int mace_config(struct net_device *dev, struct ifmap *map)
0760 {
0761   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
0762     if (map->port <= 2) {
0763       dev->if_port = map->port;
0764       netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
0765     } else
0766       return -EINVAL;
0767   }
0768   return 0;
0769 } /* mace_config */
0770 
0771 /* ----------------------------------------------------------------------------
0772 mace_open
0773     Open device driver.
0774 ---------------------------------------------------------------------------- */
0775 static int mace_open(struct net_device *dev)
0776 {
0777   unsigned int ioaddr = dev->base_addr;
0778   mace_private *lp = netdev_priv(dev);
0779   struct pcmcia_device *link = lp->p_dev;
0780 
0781   if (!pcmcia_dev_present(link))
0782     return -ENODEV;
0783 
0784   link->open++;
0785 
0786   MACEBANK(0);
0787 
0788   netif_start_queue(dev);
0789   nmclan_reset(dev);
0790 
0791   return 0; /* Always succeed */
0792 } /* mace_open */
0793 
0794 /* ----------------------------------------------------------------------------
0795 mace_close
0796     Closes device driver.
0797 ---------------------------------------------------------------------------- */
0798 static int mace_close(struct net_device *dev)
0799 {
0800   unsigned int ioaddr = dev->base_addr;
0801   mace_private *lp = netdev_priv(dev);
0802   struct pcmcia_device *link = lp->p_dev;
0803 
0804   dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
0805 
0806   /* Mask off all interrupts from the MACE chip. */
0807   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
0808 
0809   link->open--;
0810   netif_stop_queue(dev);
0811 
0812   return 0;
0813 } /* mace_close */
0814 
0815 static void netdev_get_drvinfo(struct net_device *dev,
0816                    struct ethtool_drvinfo *info)
0817 {
0818     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0819     snprintf(info->bus_info, sizeof(info->bus_info),
0820         "PCMCIA 0x%lx", dev->base_addr);
0821 }
0822 
0823 static const struct ethtool_ops netdev_ethtool_ops = {
0824     .get_drvinfo        = netdev_get_drvinfo,
0825 };
0826 
0827 /* ----------------------------------------------------------------------------
0828 mace_start_xmit
0829     This routine begins the packet transmit function.  When completed,
0830     it will generate a transmit interrupt.
0831 
0832     According to /usr/src/linux/net/inet/dev.c, if _start_xmit
0833     returns 0, the "packet is now solely the responsibility of the
0834     driver."  If _start_xmit returns non-zero, the "transmission
0835     failed, put skb back into a list."
0836 ---------------------------------------------------------------------------- */
0837 
0838 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue)
0839 {
0840   mace_private *lp = netdev_priv(dev);
0841   struct pcmcia_device *link = lp->p_dev;
0842 
0843   netdev_notice(dev, "transmit timed out -- ");
0844 #if RESET_ON_TIMEOUT
0845   pr_cont("resetting card\n");
0846   pcmcia_reset_card(link->socket);
0847 #else /* #if RESET_ON_TIMEOUT */
0848   pr_cont("NOT resetting card\n");
0849 #endif /* #if RESET_ON_TIMEOUT */
0850   netif_trans_update(dev); /* prevent tx timeout */
0851   netif_wake_queue(dev);
0852 }
0853 
0854 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
0855                      struct net_device *dev)
0856 {
0857   mace_private *lp = netdev_priv(dev);
0858   unsigned int ioaddr = dev->base_addr;
0859 
0860   netif_stop_queue(dev);
0861 
0862   pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
0863     dev->name, (long)skb->len);
0864 
0865 #if (!TX_INTERRUPTABLE)
0866   /* Disable MACE TX interrupts. */
0867   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
0868     ioaddr + AM2150_MACE_BASE + MACE_IMR);
0869   lp->tx_irq_disabled=1;
0870 #endif /* #if (!TX_INTERRUPTABLE) */
0871 
0872   {
0873     /* This block must not be interrupted by another transmit request!
0874        mace_tx_timeout will take care of timer-based retransmissions from
0875        the upper layers.  The interrupt handler is guaranteed never to
0876        service a transmit interrupt while we are in here.
0877     */
0878 
0879     dev->stats.tx_bytes += skb->len;
0880     lp->tx_free_frames--;
0881 
0882     /* WARNING: Write the _exact_ number of bytes written in the header! */
0883     /* Put out the word header [must be an outw()] . . . */
0884     outw(skb->len, ioaddr + AM2150_XMT);
0885     /* . . . and the packet [may be any combination of outw() and outb()] */
0886     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
0887     if (skb->len & 1) {
0888       /* Odd byte transfer */
0889       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
0890     }
0891 
0892 #if MULTI_TX
0893     if (lp->tx_free_frames > 0)
0894       netif_start_queue(dev);
0895 #endif /* #if MULTI_TX */
0896   }
0897 
0898 #if (!TX_INTERRUPTABLE)
0899   /* Re-enable MACE TX interrupts. */
0900   lp->tx_irq_disabled=0;
0901   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
0902 #endif /* #if (!TX_INTERRUPTABLE) */
0903 
0904   dev_kfree_skb(skb);
0905 
0906   return NETDEV_TX_OK;
0907 } /* mace_start_xmit */
0908 
0909 /* ----------------------------------------------------------------------------
0910 mace_interrupt
0911     The interrupt handler.
0912 ---------------------------------------------------------------------------- */
0913 static irqreturn_t mace_interrupt(int irq, void *dev_id)
0914 {
0915   struct net_device *dev = (struct net_device *) dev_id;
0916   mace_private *lp = netdev_priv(dev);
0917   unsigned int ioaddr;
0918   int status;
0919   int IntrCnt = MACE_MAX_IR_ITERATIONS;
0920 
0921   if (dev == NULL) {
0922     pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
0923       irq);
0924     return IRQ_NONE;
0925   }
0926 
0927   ioaddr = dev->base_addr;
0928 
0929   if (lp->tx_irq_disabled) {
0930     const char *msg;
0931     if (lp->tx_irq_disabled)
0932       msg = "Interrupt with tx_irq_disabled";
0933     else
0934       msg = "Re-entering the interrupt handler";
0935     netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
0936           msg,
0937           inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
0938           inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
0939     /* WARNING: MACE_IR has been read! */
0940     return IRQ_NONE;
0941   }
0942 
0943   if (!netif_device_present(dev)) {
0944     netdev_dbg(dev, "interrupt from dead card\n");
0945     return IRQ_NONE;
0946   }
0947 
0948   do {
0949     /* WARNING: MACE_IR is a READ/CLEAR port! */
0950     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
0951     if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
0952       return IRQ_NONE;
0953 
0954     pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
0955 
0956     if (status & MACE_IR_RCVINT) {
0957       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
0958     }
0959 
0960     if (status & MACE_IR_XMTINT) {
0961       unsigned char fifofc;
0962       unsigned char xmtrc;
0963       unsigned char xmtfs;
0964 
0965       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
0966       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
0967     dev->stats.tx_errors++;
0968     outb(0xFF, ioaddr + AM2150_XMT_SKIP);
0969       }
0970 
0971       /* Transmit Retry Count (XMTRC, reg 4) */
0972       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
0973       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
0974       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
0975 
0976       if (
0977         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
0978         MACE_XMTFS_XMTSV /* Transmit Status Valid */
0979       ) {
0980     lp->mace_stats.xmtsv++;
0981 
0982     if (xmtfs & ~MACE_XMTFS_XMTSV) {
0983       if (xmtfs & MACE_XMTFS_UFLO) {
0984         /* Underflow.  Indicates that the Transmit FIFO emptied before
0985            the end of frame was reached. */
0986         lp->mace_stats.uflo++;
0987       }
0988       if (xmtfs & MACE_XMTFS_LCOL) {
0989         /* Late Collision */
0990         lp->mace_stats.lcol++;
0991       }
0992       if (xmtfs & MACE_XMTFS_MORE) {
0993         /* MORE than one retry was needed */
0994         lp->mace_stats.more++;
0995       }
0996       if (xmtfs & MACE_XMTFS_ONE) {
0997         /* Exactly ONE retry occurred */
0998         lp->mace_stats.one++;
0999       }
1000       if (xmtfs & MACE_XMTFS_DEFER) {
1001         /* Transmission was defered */
1002         lp->mace_stats.defer++;
1003       }
1004       if (xmtfs & MACE_XMTFS_LCAR) {
1005         /* Loss of carrier */
1006         lp->mace_stats.lcar++;
1007       }
1008       if (xmtfs & MACE_XMTFS_RTRY) {
1009         /* Retry error: transmit aborted after 16 attempts */
1010         lp->mace_stats.rtry++;
1011       }
1012         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1013 
1014       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1015 
1016       dev->stats.tx_packets++;
1017       lp->tx_free_frames++;
1018       netif_wake_queue(dev);
1019     } /* if (status & MACE_IR_XMTINT) */
1020 
1021     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1022       if (status & MACE_IR_JAB) {
1023         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1024         lp->mace_stats.jab++;
1025       }
1026       if (status & MACE_IR_BABL) {
1027         /* Babble Error.  >1518 bytes transmitted. */
1028         lp->mace_stats.babl++;
1029       }
1030       if (status & MACE_IR_CERR) {
1031     /* Collision Error.  CERR indicates the absence of the
1032        Signal Quality Error Test message after a packet
1033        transmission. */
1034         lp->mace_stats.cerr++;
1035       }
1036       if (status & MACE_IR_RCVCCO) {
1037         /* Receive Collision Count Overflow; */
1038         lp->mace_stats.rcvcco++;
1039       }
1040       if (status & MACE_IR_RNTPCO) {
1041         /* Runt Packet Count Overflow */
1042         lp->mace_stats.rntpco++;
1043       }
1044       if (status & MACE_IR_MPCO) {
1045         /* Missed Packet Count Overflow */
1046         lp->mace_stats.mpco++;
1047       }
1048     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1049 
1050   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1051 
1052   return IRQ_HANDLED;
1053 } /* mace_interrupt */
1054 
1055 /* ----------------------------------------------------------------------------
1056 mace_rx
1057     Receives packets.
1058 ---------------------------------------------------------------------------- */
1059 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1060 {
1061   mace_private *lp = netdev_priv(dev);
1062   unsigned int ioaddr = dev->base_addr;
1063   unsigned char rx_framecnt;
1064   unsigned short rx_status;
1065 
1066   while (
1067     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1068     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1069     (RxCnt--)
1070   ) {
1071     rx_status = inw(ioaddr + AM2150_RCV);
1072 
1073     pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1074       " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1075 
1076     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1077       dev->stats.rx_errors++;
1078       if (rx_status & MACE_RCVFS_OFLO) {
1079         lp->mace_stats.oflo++;
1080       }
1081       if (rx_status & MACE_RCVFS_CLSN) {
1082         lp->mace_stats.clsn++;
1083       }
1084       if (rx_status & MACE_RCVFS_FRAM) {
1085     lp->mace_stats.fram++;
1086       }
1087       if (rx_status & MACE_RCVFS_FCS) {
1088         lp->mace_stats.fcs++;
1089       }
1090     } else {
1091       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1092         /* Auto Strip is off, always subtract 4 */
1093       struct sk_buff *skb;
1094 
1095       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1096         /* runt packet count */
1097       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1098         /* rcv collision count */
1099 
1100       pr_debug("    receiving packet size 0x%X rx_status"
1101         " 0x%X.\n", pkt_len, rx_status);
1102 
1103       skb = netdev_alloc_skb(dev, pkt_len + 2);
1104 
1105       if (skb != NULL) {
1106     skb_reserve(skb, 2);
1107     insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1108     if (pkt_len & 1)
1109         *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1110     skb->protocol = eth_type_trans(skb, dev);
1111 
1112     netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1113 
1114     dev->stats.rx_packets++;
1115     dev->stats.rx_bytes += pkt_len;
1116     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1117     continue;
1118       } else {
1119     pr_debug("%s: couldn't allocate a sk_buff of size"
1120           " %d.\n", dev->name, pkt_len);
1121     dev->stats.rx_dropped++;
1122       }
1123     }
1124     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1125   } /* while */
1126 
1127   return 0;
1128 } /* mace_rx */
1129 
1130 /* ----------------------------------------------------------------------------
1131 pr_linux_stats
1132 ---------------------------------------------------------------------------- */
1133 static void pr_linux_stats(struct net_device_stats *pstats)
1134 {
1135   pr_debug("pr_linux_stats\n");
1136   pr_debug(" rx_packets=%-7ld        tx_packets=%ld\n",
1137     (long)pstats->rx_packets, (long)pstats->tx_packets);
1138   pr_debug(" rx_errors=%-7ld         tx_errors=%ld\n",
1139     (long)pstats->rx_errors, (long)pstats->tx_errors);
1140   pr_debug(" rx_dropped=%-7ld        tx_dropped=%ld\n",
1141     (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1142   pr_debug(" multicast=%-7ld         collisions=%ld\n",
1143     (long)pstats->multicast, (long)pstats->collisions);
1144 
1145   pr_debug(" rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1146     (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1147   pr_debug(" rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1148     (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1149   pr_debug(" rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1150     (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1151 
1152   pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1153     (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1154   pr_debug(" tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1155     (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1156   pr_debug(" tx_window_errors=%ld\n",
1157     (long)pstats->tx_window_errors);
1158 } /* pr_linux_stats */
1159 
1160 /* ----------------------------------------------------------------------------
1161 pr_mace_stats
1162 ---------------------------------------------------------------------------- */
1163 static void pr_mace_stats(mace_statistics *pstats)
1164 {
1165   pr_debug("pr_mace_stats\n");
1166 
1167   pr_debug(" xmtsv=%-7d             uflo=%d\n",
1168     pstats->xmtsv, pstats->uflo);
1169   pr_debug(" lcol=%-7d              more=%d\n",
1170     pstats->lcol, pstats->more);
1171   pr_debug(" one=%-7d               defer=%d\n",
1172     pstats->one, pstats->defer);
1173   pr_debug(" lcar=%-7d              rtry=%d\n",
1174     pstats->lcar, pstats->rtry);
1175 
1176   /* MACE_XMTRC */
1177   pr_debug(" exdef=%-7d             xmtrc=%d\n",
1178     pstats->exdef, pstats->xmtrc);
1179 
1180   /* RFS1--Receive Status (RCVSTS) */
1181   pr_debug(" oflo=%-7d              clsn=%d\n",
1182     pstats->oflo, pstats->clsn);
1183   pr_debug(" fram=%-7d              fcs=%d\n",
1184     pstats->fram, pstats->fcs);
1185 
1186   /* RFS2--Runt Packet Count (RNTPC) */
1187   /* RFS3--Receive Collision Count (RCVCC) */
1188   pr_debug(" rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1189     pstats->rfs_rntpc, pstats->rfs_rcvcc);
1190 
1191   /* MACE_IR */
1192   pr_debug(" jab=%-7d               babl=%d\n",
1193     pstats->jab, pstats->babl);
1194   pr_debug(" cerr=%-7d              rcvcco=%d\n",
1195     pstats->cerr, pstats->rcvcco);
1196   pr_debug(" rntpco=%-7d            mpco=%d\n",
1197     pstats->rntpco, pstats->mpco);
1198 
1199   /* MACE_MPC */
1200   pr_debug(" mpc=%d\n", pstats->mpc);
1201 
1202   /* MACE_RNTPC */
1203   pr_debug(" rntpc=%d\n", pstats->rntpc);
1204 
1205   /* MACE_RCVCC */
1206   pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1207 
1208 } /* pr_mace_stats */
1209 
1210 /* ----------------------------------------------------------------------------
1211 update_stats
1212     Update statistics.  We change to register window 1, so this
1213     should be run single-threaded if the device is active. This is
1214     expected to be a rare operation, and it's simpler for the rest
1215     of the driver to assume that window 0 is always valid rather
1216     than use a special window-state variable.
1217 
1218     oflo & uflo should _never_ occur since it would mean the Xilinx
1219     was not able to transfer data between the MACE FIFO and the
1220     card's SRAM fast enough.  If this happens, something is
1221     seriously wrong with the hardware.
1222 ---------------------------------------------------------------------------- */
1223 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1224 {
1225   mace_private *lp = netdev_priv(dev);
1226 
1227   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1228   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1229   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1230   /* At this point, mace_stats is fully updated for this call.
1231      We may now update the netdev stats. */
1232 
1233   /* The MACE has no equivalent for netdev stats field which are commented
1234      out. */
1235 
1236   /* dev->stats.multicast; */
1237   dev->stats.collisions =
1238     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1239     /* Collision: The MACE may retry sending a packet 15 times
1240        before giving up.  The retry count is in XMTRC.
1241        Does each retry constitute a collision?
1242        If so, why doesn't the RCVCC record these collisions? */
1243 
1244   /* detailed rx_errors: */
1245   dev->stats.rx_length_errors =
1246     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1247   /* dev->stats.rx_over_errors */
1248   dev->stats.rx_crc_errors = lp->mace_stats.fcs;
1249   dev->stats.rx_frame_errors = lp->mace_stats.fram;
1250   dev->stats.rx_fifo_errors = lp->mace_stats.oflo;
1251   dev->stats.rx_missed_errors =
1252     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1253 
1254   /* detailed tx_errors */
1255   dev->stats.tx_aborted_errors = lp->mace_stats.rtry;
1256   dev->stats.tx_carrier_errors = lp->mace_stats.lcar;
1257     /* LCAR usually results from bad cabling. */
1258   dev->stats.tx_fifo_errors = lp->mace_stats.uflo;
1259   dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1260   /* dev->stats.tx_window_errors; */
1261 } /* update_stats */
1262 
1263 /* ----------------------------------------------------------------------------
1264 mace_get_stats
1265     Gathers ethernet statistics from the MACE chip.
1266 ---------------------------------------------------------------------------- */
1267 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1268 {
1269   mace_private *lp = netdev_priv(dev);
1270 
1271   update_stats(dev->base_addr, dev);
1272 
1273   pr_debug("%s: updating the statistics.\n", dev->name);
1274   pr_linux_stats(&dev->stats);
1275   pr_mace_stats(&lp->mace_stats);
1276 
1277   return &dev->stats;
1278 } /* net_device_stats */
1279 
1280 /* ----------------------------------------------------------------------------
1281 updateCRC
1282     Modified from Am79C90 data sheet.
1283 ---------------------------------------------------------------------------- */
1284 
1285 #ifdef BROKEN_MULTICAST
1286 
1287 static void updateCRC(int *CRC, int bit)
1288 {
1289   static const int poly[]={
1290     1,1,1,0, 1,1,0,1,
1291     1,0,1,1, 1,0,0,0,
1292     1,0,0,0, 0,0,1,1,
1293     0,0,1,0, 0,0,0,0
1294   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1295     CRC generator polynomial. */
1296 
1297   int j;
1298 
1299   /* shift CRC and control bit (CRC[32]) */
1300   for (j = 32; j > 0; j--)
1301     CRC[j] = CRC[j-1];
1302   CRC[0] = 0;
1303 
1304   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1305   if (bit ^ CRC[32])
1306     for (j = 0; j < 32; j++)
1307       CRC[j] ^= poly[j];
1308 } /* updateCRC */
1309 
1310 /* ----------------------------------------------------------------------------
1311 BuildLAF
1312     Build logical address filter.
1313     Modified from Am79C90 data sheet.
1314 
1315 Input
1316     ladrf: logical address filter (contents initialized to 0)
1317     adr: ethernet address
1318 ---------------------------------------------------------------------------- */
1319 static void BuildLAF(int *ladrf, int *adr)
1320 {
1321   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1322 
1323   int i, byte; /* temporary array indices */
1324   int hashcode; /* the output object */
1325 
1326   CRC[32]=0;
1327 
1328   for (byte = 0; byte < 6; byte++)
1329     for (i = 0; i < 8; i++)
1330       updateCRC(CRC, (adr[byte] >> i) & 1);
1331 
1332   hashcode = 0;
1333   for (i = 0; i < 6; i++)
1334     hashcode = (hashcode << 1) + CRC[i];
1335 
1336   byte = hashcode >> 3;
1337   ladrf[byte] |= (1 << (hashcode & 7));
1338 
1339 #ifdef PCMCIA_DEBUG
1340   if (0)
1341     printk(KERN_DEBUG "    adr =%pM\n", adr);
1342   printk(KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1343   for (i = 0; i < 8; i++)
1344     pr_cont(" %02X", ladrf[i]);
1345   pr_cont("\n");
1346 #endif
1347 } /* BuildLAF */
1348 
1349 /* ----------------------------------------------------------------------------
1350 restore_multicast_list
1351     Restores the multicast filter for MACE chip to the last
1352     set_multicast_list() call.
1353 
1354 Input
1355     multicast_num_addrs
1356     multicast_ladrf[]
1357 ---------------------------------------------------------------------------- */
1358 static void restore_multicast_list(struct net_device *dev)
1359 {
1360   mace_private *lp = netdev_priv(dev);
1361   int num_addrs = lp->multicast_num_addrs;
1362   int *ladrf = lp->multicast_ladrf;
1363   unsigned int ioaddr = dev->base_addr;
1364   int i;
1365 
1366   pr_debug("%s: restoring Rx mode to %d addresses.\n",
1367     dev->name, num_addrs);
1368 
1369   if (num_addrs > 0) {
1370 
1371     pr_debug("Attempt to restore multicast list detected.\n");
1372 
1373     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1374     /* Poll ADDRCHG bit */
1375     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1376       ;
1377     /* Set LADRF register */
1378     for (i = 0; i < MACE_LADRF_LEN; i++)
1379       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1380 
1381     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1382     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1383 
1384   } else if (num_addrs < 0) {
1385 
1386     /* Promiscuous mode: receive all packets */
1387     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1388     mace_write(lp, ioaddr, MACE_MACCC,
1389       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1390     );
1391 
1392   } else {
1393 
1394     /* Normal mode */
1395     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1396     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1397 
1398   }
1399 } /* restore_multicast_list */
1400 
1401 /* ----------------------------------------------------------------------------
1402 set_multicast_list
1403     Set or clear the multicast filter for this adaptor.
1404 
1405 Input
1406     num_addrs == -1 Promiscuous mode, receive all packets
1407     num_addrs == 0  Normal mode, clear multicast list
1408     num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1409             best-effort filtering.
1410 Output
1411     multicast_num_addrs
1412     multicast_ladrf[]
1413 ---------------------------------------------------------------------------- */
1414 
1415 static void set_multicast_list(struct net_device *dev)
1416 {
1417   mace_private *lp = netdev_priv(dev);
1418   int adr[ETH_ALEN] = {0}; /* Ethernet address */
1419   struct netdev_hw_addr *ha;
1420 
1421 #ifdef PCMCIA_DEBUG
1422   {
1423     static int old;
1424     if (netdev_mc_count(dev) != old) {
1425       old = netdev_mc_count(dev);
1426       pr_debug("%s: setting Rx mode to %d addresses.\n",
1427         dev->name, old);
1428     }
1429   }
1430 #endif
1431 
1432   /* Set multicast_num_addrs. */
1433   lp->multicast_num_addrs = netdev_mc_count(dev);
1434 
1435   /* Set multicast_ladrf. */
1436   if (num_addrs > 0) {
1437     /* Calculate multicast logical address filter */
1438     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1439     netdev_for_each_mc_addr(ha, dev) {
1440       memcpy(adr, ha->addr, ETH_ALEN);
1441       BuildLAF(lp->multicast_ladrf, adr);
1442     }
1443   }
1444 
1445   restore_multicast_list(dev);
1446 
1447 } /* set_multicast_list */
1448 
1449 #endif /* BROKEN_MULTICAST */
1450 
1451 static void restore_multicast_list(struct net_device *dev)
1452 {
1453   unsigned int ioaddr = dev->base_addr;
1454   mace_private *lp = netdev_priv(dev);
1455 
1456   pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1457     lp->multicast_num_addrs);
1458 
1459   if (dev->flags & IFF_PROMISC) {
1460     /* Promiscuous mode: receive all packets */
1461     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1462     mace_write(lp, ioaddr, MACE_MACCC,
1463       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1464     );
1465   } else {
1466     /* Normal mode */
1467     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1468     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1469   }
1470 } /* restore_multicast_list */
1471 
1472 static void set_multicast_list(struct net_device *dev)
1473 {
1474   mace_private *lp = netdev_priv(dev);
1475 
1476 #ifdef PCMCIA_DEBUG
1477   {
1478     static int old;
1479     if (netdev_mc_count(dev) != old) {
1480       old = netdev_mc_count(dev);
1481       pr_debug("%s: setting Rx mode to %d addresses.\n",
1482         dev->name, old);
1483     }
1484   }
1485 #endif
1486 
1487   lp->multicast_num_addrs = netdev_mc_count(dev);
1488   restore_multicast_list(dev);
1489 
1490 } /* set_multicast_list */
1491 
1492 static const struct pcmcia_device_id nmclan_ids[] = {
1493     PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1494     PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1495     PCMCIA_DEVICE_NULL,
1496 };
1497 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1498 
1499 static struct pcmcia_driver nmclan_cs_driver = {
1500     .owner      = THIS_MODULE,
1501     .name       = "nmclan_cs",
1502     .probe      = nmclan_probe,
1503     .remove     = nmclan_detach,
1504     .id_table       = nmclan_ids,
1505     .suspend    = nmclan_suspend,
1506     .resume     = nmclan_resume,
1507 };
1508 module_pcmcia_driver(nmclan_cs_driver);
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