ethernet/amd/au1000_eth.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Alchemy Au1x00 ethernet driver include file
0005  *
0006  * Author: Pete Popov <ppopov@mvista.com>
0007  *
0008  * Copyright 2001 MontaVista Software Inc.
0009  */
0010
0011
0012 #define MAC_IOSIZE 0x10000
0013 #define NUM_RX_DMA 4       /* Au1x00 has 4 rx hardware descriptors */
0014 #define NUM_TX_DMA 4       /* Au1x00 has 4 tx hardware descriptors */
0015
0016 #define NUM_RX_BUFFS 4
0017 #define NUM_TX_BUFFS 4
0018 #define MAX_BUF_SIZE 2048
0019
0020 #define ETH_TX_TIMEOUT (HZ/4)
0021 #define MAC_MIN_PKT_SIZE 64
0022
0023 #define MULTICAST_FILTER_LIMIT 64
0024
0025 /*
0026  * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
0027  * boundary for both, receive and transmit.
0028  */
0029 struct db_dest {
0030     struct db_dest *pnext;
0031     u32 *vaddr;
0032     dma_addr_t dma_addr;
0033 };
0034
0035 /*
0036  * The transmit and receive descriptors are memory
0037  * mapped registers.
0038  */
0039 struct tx_dma {
0040     u32 status;
0041     u32 buff_stat;
0042     u32 len;
0043     u32 pad;
0044 };
0045
0046 struct rx_dma {
0047     u32 status;
0048     u32 buff_stat;
0049     u32 pad[2];
0050 };
0051
0052
0053 /*
0054  * MAC control registers, memory mapped.
0055  */
0056 struct mac_reg {
0057     u32 control;
0058     u32 mac_addr_high;
0059     u32 mac_addr_low;
0060     u32 multi_hash_high;
0061     u32 multi_hash_low;
0062     u32 mii_control;
0063     u32 mii_data;
0064     u32 flow_control;
0065     u32 vlan1_tag;
0066     u32 vlan2_tag;
0067 };
0068
0069
0070 struct au1000_private {
0071     struct db_dest *pDBfree;
0072     struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
0073     struct rx_dma *rx_dma_ring[NUM_RX_DMA];
0074     struct tx_dma *tx_dma_ring[NUM_TX_DMA];
0075     struct db_dest *rx_db_inuse[NUM_RX_DMA];
0076     struct db_dest *tx_db_inuse[NUM_TX_DMA];
0077     u32 rx_head;
0078     u32 tx_head;
0079     u32 tx_tail;
0080     u32 tx_full;
0081
0082     int mac_id;
0083
0084     int mac_enabled;       /* whether MAC is currently enabled and running
0085                 * (req. for mdio)
0086                 */
0087
0088     int old_link;          /* used by au1000_adjust_link */
0089     int old_speed;
0090     int old_duplex;
0091
0092     struct mii_bus *mii_bus;
0093
0094     /* PHY configuration */
0095     int phy_static_config;
0096     int phy_search_highest_addr;
0097     int phy1_search_mac0;
0098
0099     int phy_addr;
0100     int phy_busid;
0101     int phy_irq;
0102
0103     /* These variables are just for quick access
0104      * to certain regs addresses.
0105      */
0106     struct mac_reg *mac;  /* mac registers                      */
0107     u32 *enable;     /* address of MAC Enable Register     */
0108     void __iomem *macdma;   /* base of MAC DMA port */
0109     void *vaddr;        /* virtual address of rx/tx buffers   */
0110     dma_addr_t dma_addr;    /* dma address of rx/tx buffers       */
0111
0112     spinlock_t lock;       /* Serialise access to device */
0113
0114     u32 msg_enable;
0115 };