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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Alchemy Au1x00 ethernet driver
0005  *
0006  * Copyright 2001-2003, 2006 MontaVista Software Inc.
0007  * Copyright 2002 TimeSys Corp.
0008  * Added ethtool/mii-tool support,
0009  * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
0010  * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
0011  * or riemer@riemer-nt.de: fixed the link beat detection with
0012  * ioctls (SIOCGMIIPHY)
0013  * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
0014  *  converted to use linux-2.6.x's PHY framework
0015  *
0016  * Author: MontaVista Software, Inc.
0017  *      ppopov@mvista.com or source@mvista.com
0018  */
0019 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0020 
0021 #include <linux/capability.h>
0022 #include <linux/dma-mapping.h>
0023 #include <linux/module.h>
0024 #include <linux/kernel.h>
0025 #include <linux/string.h>
0026 #include <linux/timer.h>
0027 #include <linux/errno.h>
0028 #include <linux/in.h>
0029 #include <linux/ioport.h>
0030 #include <linux/bitops.h>
0031 #include <linux/slab.h>
0032 #include <linux/interrupt.h>
0033 #include <linux/netdevice.h>
0034 #include <linux/etherdevice.h>
0035 #include <linux/ethtool.h>
0036 #include <linux/mii.h>
0037 #include <linux/skbuff.h>
0038 #include <linux/delay.h>
0039 #include <linux/crc32.h>
0040 #include <linux/phy.h>
0041 #include <linux/platform_device.h>
0042 #include <linux/cpu.h>
0043 #include <linux/io.h>
0044 
0045 #include <asm/mipsregs.h>
0046 #include <asm/irq.h>
0047 #include <asm/processor.h>
0048 
0049 #include <au1000.h>
0050 #include <au1xxx_eth.h>
0051 #include <prom.h>
0052 
0053 #include "au1000_eth.h"
0054 
0055 #ifdef AU1000_ETH_DEBUG
0056 static int au1000_debug = 5;
0057 #else
0058 static int au1000_debug = 3;
0059 #endif
0060 
0061 #define AU1000_DEF_MSG_ENABLE   (NETIF_MSG_DRV  | \
0062                 NETIF_MSG_PROBE | \
0063                 NETIF_MSG_LINK)
0064 
0065 #define DRV_NAME    "au1000_eth"
0066 #define DRV_AUTHOR  "Pete Popov <ppopov@embeddedalley.com>"
0067 #define DRV_DESC    "Au1xxx on-chip Ethernet driver"
0068 
0069 MODULE_AUTHOR(DRV_AUTHOR);
0070 MODULE_DESCRIPTION(DRV_DESC);
0071 MODULE_LICENSE("GPL");
0072 
0073 /* AU1000 MAC registers and bits */
0074 #define MAC_CONTROL     0x0
0075 #  define MAC_RX_ENABLE     (1 << 2)
0076 #  define MAC_TX_ENABLE     (1 << 3)
0077 #  define MAC_DEF_CHECK     (1 << 5)
0078 #  define MAC_SET_BL(X)     (((X) & 0x3) << 6)
0079 #  define MAC_AUTO_PAD      (1 << 8)
0080 #  define MAC_DISABLE_RETRY (1 << 10)
0081 #  define MAC_DISABLE_BCAST (1 << 11)
0082 #  define MAC_LATE_COL      (1 << 12)
0083 #  define MAC_HASH_MODE     (1 << 13)
0084 #  define MAC_HASH_ONLY     (1 << 15)
0085 #  define MAC_PASS_ALL      (1 << 16)
0086 #  define MAC_INVERSE_FILTER    (1 << 17)
0087 #  define MAC_PROMISCUOUS   (1 << 18)
0088 #  define MAC_PASS_ALL_MULTI    (1 << 19)
0089 #  define MAC_FULL_DUPLEX   (1 << 20)
0090 #  define MAC_NORMAL_MODE   0
0091 #  define MAC_INT_LOOPBACK  (1 << 21)
0092 #  define MAC_EXT_LOOPBACK  (1 << 22)
0093 #  define MAC_DISABLE_RX_OWN    (1 << 23)
0094 #  define MAC_BIG_ENDIAN    (1 << 30)
0095 #  define MAC_RX_ALL        (1 << 31)
0096 #define MAC_ADDRESS_HIGH    0x4
0097 #define MAC_ADDRESS_LOW     0x8
0098 #define MAC_MCAST_HIGH      0xC
0099 #define MAC_MCAST_LOW       0x10
0100 #define MAC_MII_CNTRL       0x14
0101 #  define MAC_MII_BUSY      (1 << 0)
0102 #  define MAC_MII_READ      0
0103 #  define MAC_MII_WRITE     (1 << 1)
0104 #  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
0105 #  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
0106 #define MAC_MII_DATA        0x18
0107 #define MAC_FLOW_CNTRL      0x1C
0108 #  define MAC_FLOW_CNTRL_BUSY   (1 << 0)
0109 #  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
0110 #  define MAC_PASS_CONTROL  (1 << 2)
0111 #  define MAC_SET_PAUSE(X)  (((X) & 0xffff) << 16)
0112 #define MAC_VLAN1_TAG       0x20
0113 #define MAC_VLAN2_TAG       0x24
0114 
0115 /* Ethernet Controller Enable */
0116 #  define MAC_EN_CLOCK_ENABLE   (1 << 0)
0117 #  define MAC_EN_RESET0     (1 << 1)
0118 #  define MAC_EN_TOSS       (0 << 2)
0119 #  define MAC_EN_CACHEABLE  (1 << 3)
0120 #  define MAC_EN_RESET1     (1 << 4)
0121 #  define MAC_EN_RESET2     (1 << 5)
0122 #  define MAC_DMA_RESET     (1 << 6)
0123 
0124 /* Ethernet Controller DMA Channels */
0125 /* offsets from MAC_TX_RING_ADDR address */
0126 #define MAC_TX_BUFF0_STATUS 0x0
0127 #  define TX_FRAME_ABORTED  (1 << 0)
0128 #  define TX_JAB_TIMEOUT    (1 << 1)
0129 #  define TX_NO_CARRIER     (1 << 2)
0130 #  define TX_LOSS_CARRIER   (1 << 3)
0131 #  define TX_EXC_DEF        (1 << 4)
0132 #  define TX_LATE_COLL_ABORT    (1 << 5)
0133 #  define TX_EXC_COLL       (1 << 6)
0134 #  define TX_UNDERRUN       (1 << 7)
0135 #  define TX_DEFERRED       (1 << 8)
0136 #  define TX_LATE_COLL      (1 << 9)
0137 #  define TX_COLL_CNT_MASK  (0xF << 10)
0138 #  define TX_PKT_RETRY      (1 << 31)
0139 #define MAC_TX_BUFF0_ADDR   0x4
0140 #  define TX_DMA_ENABLE     (1 << 0)
0141 #  define TX_T_DONE     (1 << 1)
0142 #  define TX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
0143 #define MAC_TX_BUFF0_LEN    0x8
0144 #define MAC_TX_BUFF1_STATUS 0x10
0145 #define MAC_TX_BUFF1_ADDR   0x14
0146 #define MAC_TX_BUFF1_LEN    0x18
0147 #define MAC_TX_BUFF2_STATUS 0x20
0148 #define MAC_TX_BUFF2_ADDR   0x24
0149 #define MAC_TX_BUFF2_LEN    0x28
0150 #define MAC_TX_BUFF3_STATUS 0x30
0151 #define MAC_TX_BUFF3_ADDR   0x34
0152 #define MAC_TX_BUFF3_LEN    0x38
0153 
0154 /* offsets from MAC_RX_RING_ADDR */
0155 #define MAC_RX_BUFF0_STATUS 0x0
0156 #  define RX_FRAME_LEN_MASK 0x3fff
0157 #  define RX_WDOG_TIMER     (1 << 14)
0158 #  define RX_RUNT       (1 << 15)
0159 #  define RX_OVERLEN        (1 << 16)
0160 #  define RX_COLL       (1 << 17)
0161 #  define RX_ETHER      (1 << 18)
0162 #  define RX_MII_ERROR      (1 << 19)
0163 #  define RX_DRIBBLING      (1 << 20)
0164 #  define RX_CRC_ERROR      (1 << 21)
0165 #  define RX_VLAN1      (1 << 22)
0166 #  define RX_VLAN2      (1 << 23)
0167 #  define RX_LEN_ERROR      (1 << 24)
0168 #  define RX_CNTRL_FRAME    (1 << 25)
0169 #  define RX_U_CNTRL_FRAME  (1 << 26)
0170 #  define RX_MCAST_FRAME    (1 << 27)
0171 #  define RX_BCAST_FRAME    (1 << 28)
0172 #  define RX_FILTER_FAIL    (1 << 29)
0173 #  define RX_PACKET_FILTER  (1 << 30)
0174 #  define RX_MISSED_FRAME   (1 << 31)
0175 
0176 #  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
0177             RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
0178             RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
0179 #define MAC_RX_BUFF0_ADDR   0x4
0180 #  define RX_DMA_ENABLE     (1 << 0)
0181 #  define RX_T_DONE     (1 << 1)
0182 #  define RX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
0183 #  define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
0184 #define MAC_RX_BUFF1_STATUS 0x10
0185 #define MAC_RX_BUFF1_ADDR   0x14
0186 #define MAC_RX_BUFF2_STATUS 0x20
0187 #define MAC_RX_BUFF2_ADDR   0x24
0188 #define MAC_RX_BUFF3_STATUS 0x30
0189 #define MAC_RX_BUFF3_ADDR   0x34
0190 
0191 /*
0192  * Theory of operation
0193  *
0194  * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
0195  * There are four receive and four transmit descriptors.  These
0196  * descriptors are not in memory; rather, they are just a set of
0197  * hardware registers.
0198  *
0199  * Since the Au1000 has a coherent data cache, the receive and
0200  * transmit buffers are allocated from the KSEG0 segment. The
0201  * hardware registers, however, are still mapped at KSEG1 to
0202  * make sure there's no out-of-order writes, and that all writes
0203  * complete immediately.
0204  */
0205 
0206 /*
0207  * board-specific configurations
0208  *
0209  * PHY detection algorithm
0210  *
0211  * If phy_static_config is undefined, the PHY setup is
0212  * autodetected:
0213  *
0214  * mii_probe() first searches the current MAC's MII bus for a PHY,
0215  * selecting the first (or last, if phy_search_highest_addr is
0216  * defined) PHY address not already claimed by another netdev.
0217  *
0218  * If nothing was found that way when searching for the 2nd ethernet
0219  * controller's PHY and phy1_search_mac0 is defined, then
0220  * the first MII bus is searched as well for an unclaimed PHY; this is
0221  * needed in case of a dual-PHY accessible only through the MAC0's MII
0222  * bus.
0223  *
0224  * Finally, if no PHY is found, then the corresponding ethernet
0225  * controller is not registered to the network subsystem.
0226  */
0227 
0228 /* autodetection defaults: phy1_search_mac0 */
0229 
0230 /* static PHY setup
0231  *
0232  * most boards PHY setup should be detectable properly with the
0233  * autodetection algorithm in mii_probe(), but in some cases (e.g. if
0234  * you have a switch attached, or want to use the PHY's interrupt
0235  * notification capabilities) you can provide a static PHY
0236  * configuration here
0237  *
0238  * IRQs may only be set, if a PHY address was configured
0239  * If a PHY address is given, also a bus id is required to be set
0240  *
0241  * ps: make sure the used irqs are configured properly in the board
0242  * specific irq-map
0243  */
0244 static void au1000_enable_mac(struct net_device *dev, int force_reset)
0245 {
0246     unsigned long flags;
0247     struct au1000_private *aup = netdev_priv(dev);
0248 
0249     spin_lock_irqsave(&aup->lock, flags);
0250 
0251     if (force_reset || (!aup->mac_enabled)) {
0252         writel(MAC_EN_CLOCK_ENABLE, aup->enable);
0253         wmb(); /* drain writebuffer */
0254         mdelay(2);
0255         writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
0256                 | MAC_EN_CLOCK_ENABLE), aup->enable);
0257         wmb(); /* drain writebuffer */
0258         mdelay(2);
0259 
0260         aup->mac_enabled = 1;
0261     }
0262 
0263     spin_unlock_irqrestore(&aup->lock, flags);
0264 }
0265 
0266 /*
0267  * MII operations
0268  */
0269 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
0270 {
0271     struct au1000_private *aup = netdev_priv(dev);
0272     u32 *const mii_control_reg = &aup->mac->mii_control;
0273     u32 *const mii_data_reg = &aup->mac->mii_data;
0274     u32 timedout = 20;
0275     u32 mii_control;
0276 
0277     while (readl(mii_control_reg) & MAC_MII_BUSY) {
0278         mdelay(1);
0279         if (--timedout == 0) {
0280             netdev_err(dev, "read_MII busy timeout!!\n");
0281             return -1;
0282         }
0283     }
0284 
0285     mii_control = MAC_SET_MII_SELECT_REG(reg) |
0286         MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
0287 
0288     writel(mii_control, mii_control_reg);
0289 
0290     timedout = 20;
0291     while (readl(mii_control_reg) & MAC_MII_BUSY) {
0292         mdelay(1);
0293         if (--timedout == 0) {
0294             netdev_err(dev, "mdio_read busy timeout!!\n");
0295             return -1;
0296         }
0297     }
0298     return readl(mii_data_reg);
0299 }
0300 
0301 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
0302                   int reg, u16 value)
0303 {
0304     struct au1000_private *aup = netdev_priv(dev);
0305     u32 *const mii_control_reg = &aup->mac->mii_control;
0306     u32 *const mii_data_reg = &aup->mac->mii_data;
0307     u32 timedout = 20;
0308     u32 mii_control;
0309 
0310     while (readl(mii_control_reg) & MAC_MII_BUSY) {
0311         mdelay(1);
0312         if (--timedout == 0) {
0313             netdev_err(dev, "mdio_write busy timeout!!\n");
0314             return;
0315         }
0316     }
0317 
0318     mii_control = MAC_SET_MII_SELECT_REG(reg) |
0319         MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
0320 
0321     writel(value, mii_data_reg);
0322     writel(mii_control, mii_control_reg);
0323 }
0324 
0325 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0326 {
0327     struct net_device *const dev = bus->priv;
0328 
0329     /* make sure the MAC associated with this
0330      * mii_bus is enabled
0331      */
0332     au1000_enable_mac(dev, 0);
0333 
0334     return au1000_mdio_read(dev, phy_addr, regnum);
0335 }
0336 
0337 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
0338                 u16 value)
0339 {
0340     struct net_device *const dev = bus->priv;
0341 
0342     /* make sure the MAC associated with this
0343      * mii_bus is enabled
0344      */
0345     au1000_enable_mac(dev, 0);
0346 
0347     au1000_mdio_write(dev, phy_addr, regnum, value);
0348     return 0;
0349 }
0350 
0351 static int au1000_mdiobus_reset(struct mii_bus *bus)
0352 {
0353     struct net_device *const dev = bus->priv;
0354 
0355     /* make sure the MAC associated with this
0356      * mii_bus is enabled
0357      */
0358     au1000_enable_mac(dev, 0);
0359 
0360     return 0;
0361 }
0362 
0363 static void au1000_hard_stop(struct net_device *dev)
0364 {
0365     struct au1000_private *aup = netdev_priv(dev);
0366     u32 reg;
0367 
0368     netif_dbg(aup, drv, dev, "hard stop\n");
0369 
0370     reg = readl(&aup->mac->control);
0371     reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
0372     writel(reg, &aup->mac->control);
0373     wmb(); /* drain writebuffer */
0374     mdelay(10);
0375 }
0376 
0377 static void au1000_enable_rx_tx(struct net_device *dev)
0378 {
0379     struct au1000_private *aup = netdev_priv(dev);
0380     u32 reg;
0381 
0382     netif_dbg(aup, hw, dev, "enable_rx_tx\n");
0383 
0384     reg = readl(&aup->mac->control);
0385     reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
0386     writel(reg, &aup->mac->control);
0387     wmb(); /* drain writebuffer */
0388     mdelay(10);
0389 }
0390 
0391 static void
0392 au1000_adjust_link(struct net_device *dev)
0393 {
0394     struct au1000_private *aup = netdev_priv(dev);
0395     struct phy_device *phydev = dev->phydev;
0396     unsigned long flags;
0397     u32 reg;
0398 
0399     int status_change = 0;
0400 
0401     BUG_ON(!phydev);
0402 
0403     spin_lock_irqsave(&aup->lock, flags);
0404 
0405     if (phydev->link && (aup->old_speed != phydev->speed)) {
0406         /* speed changed */
0407 
0408         switch (phydev->speed) {
0409         case SPEED_10:
0410         case SPEED_100:
0411             break;
0412         default:
0413             netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
0414                             phydev->speed);
0415             break;
0416         }
0417 
0418         aup->old_speed = phydev->speed;
0419 
0420         status_change = 1;
0421     }
0422 
0423     if (phydev->link && (aup->old_duplex != phydev->duplex)) {
0424         /* duplex mode changed */
0425 
0426         /* switching duplex mode requires to disable rx and tx! */
0427         au1000_hard_stop(dev);
0428 
0429         reg = readl(&aup->mac->control);
0430         if (DUPLEX_FULL == phydev->duplex) {
0431             reg |= MAC_FULL_DUPLEX;
0432             reg &= ~MAC_DISABLE_RX_OWN;
0433         } else {
0434             reg &= ~MAC_FULL_DUPLEX;
0435             reg |= MAC_DISABLE_RX_OWN;
0436         }
0437         writel(reg, &aup->mac->control);
0438         wmb(); /* drain writebuffer */
0439         mdelay(1);
0440 
0441         au1000_enable_rx_tx(dev);
0442         aup->old_duplex = phydev->duplex;
0443 
0444         status_change = 1;
0445     }
0446 
0447     if (phydev->link != aup->old_link) {
0448         /* link state changed */
0449 
0450         if (!phydev->link) {
0451             /* link went down */
0452             aup->old_speed = 0;
0453             aup->old_duplex = -1;
0454         }
0455 
0456         aup->old_link = phydev->link;
0457         status_change = 1;
0458     }
0459 
0460     spin_unlock_irqrestore(&aup->lock, flags);
0461 
0462     if (status_change) {
0463         if (phydev->link)
0464             netdev_info(dev, "link up (%d/%s)\n",
0465                    phydev->speed,
0466                    DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
0467         else
0468             netdev_info(dev, "link down\n");
0469     }
0470 }
0471 
0472 static int au1000_mii_probe(struct net_device *dev)
0473 {
0474     struct au1000_private *const aup = netdev_priv(dev);
0475     struct phy_device *phydev = NULL;
0476     int phy_addr;
0477 
0478     if (aup->phy_static_config) {
0479         BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
0480 
0481         if (aup->phy_addr)
0482             phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
0483         else
0484             netdev_info(dev, "using PHY-less setup\n");
0485         return 0;
0486     }
0487 
0488     /* find the first (lowest address) PHY
0489      * on the current MAC's MII bus
0490      */
0491     for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
0492         if (mdiobus_get_phy(aup->mii_bus, phy_addr)) {
0493             phydev = mdiobus_get_phy(aup->mii_bus, phy_addr);
0494             if (!aup->phy_search_highest_addr)
0495                 /* break out with first one found */
0496                 break;
0497         }
0498 
0499     if (aup->phy1_search_mac0) {
0500         /* try harder to find a PHY */
0501         if (!phydev && (aup->mac_id == 1)) {
0502             /* no PHY found, maybe we have a dual PHY? */
0503             dev_info(&dev->dev, ": no PHY found on MAC1, "
0504                 "let's see if it's attached to MAC0...\n");
0505 
0506             /* find the first (lowest address) non-attached
0507              * PHY on the MAC0 MII bus
0508              */
0509             for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
0510                 struct phy_device *const tmp_phydev =
0511                     mdiobus_get_phy(aup->mii_bus,
0512                             phy_addr);
0513 
0514                 if (aup->mac_id == 1)
0515                     break;
0516 
0517                 /* no PHY here... */
0518                 if (!tmp_phydev)
0519                     continue;
0520 
0521                 /* already claimed by MAC0 */
0522                 if (tmp_phydev->attached_dev)
0523                     continue;
0524 
0525                 phydev = tmp_phydev;
0526                 break; /* found it */
0527             }
0528         }
0529     }
0530 
0531     if (!phydev) {
0532         netdev_err(dev, "no PHY found\n");
0533         return -1;
0534     }
0535 
0536     /* now we are supposed to have a proper phydev, to attach to... */
0537     BUG_ON(phydev->attached_dev);
0538 
0539     phydev = phy_connect(dev, phydev_name(phydev),
0540                  &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
0541 
0542     if (IS_ERR(phydev)) {
0543         netdev_err(dev, "Could not attach to PHY\n");
0544         return PTR_ERR(phydev);
0545     }
0546 
0547     phy_set_max_speed(phydev, SPEED_100);
0548 
0549     aup->old_link = 0;
0550     aup->old_speed = 0;
0551     aup->old_duplex = -1;
0552 
0553     phy_attached_info(phydev);
0554 
0555     return 0;
0556 }
0557 
0558 /*
0559  * Buffer allocation/deallocation routines. The buffer descriptor returned
0560  * has the virtual and dma address of a buffer suitable for
0561  * both, receive and transmit operations.
0562  */
0563 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
0564 {
0565     struct db_dest *pDB;
0566     pDB = aup->pDBfree;
0567 
0568     if (pDB)
0569         aup->pDBfree = pDB->pnext;
0570 
0571     return pDB;
0572 }
0573 
0574 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
0575 {
0576     struct db_dest *pDBfree = aup->pDBfree;
0577     if (pDBfree)
0578         pDBfree->pnext = pDB;
0579     aup->pDBfree = pDB;
0580 }
0581 
0582 static void au1000_reset_mac_unlocked(struct net_device *dev)
0583 {
0584     struct au1000_private *const aup = netdev_priv(dev);
0585     int i;
0586 
0587     au1000_hard_stop(dev);
0588 
0589     writel(MAC_EN_CLOCK_ENABLE, aup->enable);
0590     wmb(); /* drain writebuffer */
0591     mdelay(2);
0592     writel(0, aup->enable);
0593     wmb(); /* drain writebuffer */
0594     mdelay(2);
0595 
0596     aup->tx_full = 0;
0597     for (i = 0; i < NUM_RX_DMA; i++) {
0598         /* reset control bits */
0599         aup->rx_dma_ring[i]->buff_stat &= ~0xf;
0600     }
0601     for (i = 0; i < NUM_TX_DMA; i++) {
0602         /* reset control bits */
0603         aup->tx_dma_ring[i]->buff_stat &= ~0xf;
0604     }
0605 
0606     aup->mac_enabled = 0;
0607 
0608 }
0609 
0610 static void au1000_reset_mac(struct net_device *dev)
0611 {
0612     struct au1000_private *const aup = netdev_priv(dev);
0613     unsigned long flags;
0614 
0615     netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
0616                     (unsigned)aup);
0617 
0618     spin_lock_irqsave(&aup->lock, flags);
0619 
0620     au1000_reset_mac_unlocked(dev);
0621 
0622     spin_unlock_irqrestore(&aup->lock, flags);
0623 }
0624 
0625 /*
0626  * Setup the receive and transmit "rings".  These pointers are the addresses
0627  * of the rx and tx MAC DMA registers so they are fixed by the hardware --
0628  * these are not descriptors sitting in memory.
0629  */
0630 static void
0631 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
0632 {
0633     int i;
0634 
0635     for (i = 0; i < NUM_RX_DMA; i++) {
0636         aup->rx_dma_ring[i] = (struct rx_dma *)
0637             (tx_base + 0x100 + sizeof(struct rx_dma) * i);
0638     }
0639     for (i = 0; i < NUM_TX_DMA; i++) {
0640         aup->tx_dma_ring[i] = (struct tx_dma *)
0641             (tx_base + sizeof(struct tx_dma) * i);
0642     }
0643 }
0644 
0645 /*
0646  * ethtool operations
0647  */
0648 static void
0649 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
0650 {
0651     struct au1000_private *aup = netdev_priv(dev);
0652 
0653     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0654     snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
0655          aup->mac_id);
0656 }
0657 
0658 static void au1000_set_msglevel(struct net_device *dev, u32 value)
0659 {
0660     struct au1000_private *aup = netdev_priv(dev);
0661     aup->msg_enable = value;
0662 }
0663 
0664 static u32 au1000_get_msglevel(struct net_device *dev)
0665 {
0666     struct au1000_private *aup = netdev_priv(dev);
0667     return aup->msg_enable;
0668 }
0669 
0670 static const struct ethtool_ops au1000_ethtool_ops = {
0671     .get_drvinfo = au1000_get_drvinfo,
0672     .get_link = ethtool_op_get_link,
0673     .get_msglevel = au1000_get_msglevel,
0674     .set_msglevel = au1000_set_msglevel,
0675     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0676     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0677 };
0678 
0679 /*
0680  * Initialize the interface.
0681  *
0682  * When the device powers up, the clocks are disabled and the
0683  * mac is in reset state.  When the interface is closed, we
0684  * do the same -- reset the device and disable the clocks to
0685  * conserve power. Thus, whenever au1000_init() is called,
0686  * the device should already be in reset state.
0687  */
0688 static int au1000_init(struct net_device *dev)
0689 {
0690     struct au1000_private *aup = netdev_priv(dev);
0691     unsigned long flags;
0692     int i;
0693     u32 control;
0694 
0695     netif_dbg(aup, hw, dev, "au1000_init\n");
0696 
0697     /* bring the device out of reset */
0698     au1000_enable_mac(dev, 1);
0699 
0700     spin_lock_irqsave(&aup->lock, flags);
0701 
0702     writel(0, &aup->mac->control);
0703     aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
0704     aup->tx_tail = aup->tx_head;
0705     aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
0706 
0707     writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
0708                     &aup->mac->mac_addr_high);
0709     writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
0710         dev->dev_addr[1]<<8 | dev->dev_addr[0],
0711                     &aup->mac->mac_addr_low);
0712 
0713 
0714     for (i = 0; i < NUM_RX_DMA; i++)
0715         aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
0716 
0717     wmb(); /* drain writebuffer */
0718 
0719     control = MAC_RX_ENABLE | MAC_TX_ENABLE;
0720 #ifndef CONFIG_CPU_LITTLE_ENDIAN
0721     control |= MAC_BIG_ENDIAN;
0722 #endif
0723     if (dev->phydev) {
0724         if (dev->phydev->link && (DUPLEX_FULL == dev->phydev->duplex))
0725             control |= MAC_FULL_DUPLEX;
0726         else
0727             control |= MAC_DISABLE_RX_OWN;
0728     } else { /* PHY-less op, assume full-duplex */
0729         control |= MAC_FULL_DUPLEX;
0730     }
0731 
0732     writel(control, &aup->mac->control);
0733     writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
0734     wmb(); /* drain writebuffer */
0735 
0736     spin_unlock_irqrestore(&aup->lock, flags);
0737     return 0;
0738 }
0739 
0740 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
0741 {
0742     struct net_device_stats *ps = &dev->stats;
0743 
0744     ps->rx_packets++;
0745     if (status & RX_MCAST_FRAME)
0746         ps->multicast++;
0747 
0748     if (status & RX_ERROR) {
0749         ps->rx_errors++;
0750         if (status & RX_MISSED_FRAME)
0751             ps->rx_missed_errors++;
0752         if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
0753             ps->rx_length_errors++;
0754         if (status & RX_CRC_ERROR)
0755             ps->rx_crc_errors++;
0756         if (status & RX_COLL)
0757             ps->collisions++;
0758     } else
0759         ps->rx_bytes += status & RX_FRAME_LEN_MASK;
0760 
0761 }
0762 
0763 /*
0764  * Au1000 receive routine.
0765  */
0766 static int au1000_rx(struct net_device *dev)
0767 {
0768     struct au1000_private *aup = netdev_priv(dev);
0769     struct sk_buff *skb;
0770     struct rx_dma *prxd;
0771     u32 buff_stat, status;
0772     struct db_dest *pDB;
0773     u32 frmlen;
0774 
0775     netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
0776 
0777     prxd = aup->rx_dma_ring[aup->rx_head];
0778     buff_stat = prxd->buff_stat;
0779     while (buff_stat & RX_T_DONE)  {
0780         status = prxd->status;
0781         pDB = aup->rx_db_inuse[aup->rx_head];
0782         au1000_update_rx_stats(dev, status);
0783         if (!(status & RX_ERROR))  {
0784 
0785             /* good frame */
0786             frmlen = (status & RX_FRAME_LEN_MASK);
0787             frmlen -= 4; /* Remove FCS */
0788             skb = netdev_alloc_skb(dev, frmlen + 2);
0789             if (skb == NULL) {
0790                 dev->stats.rx_dropped++;
0791                 continue;
0792             }
0793             skb_reserve(skb, 2);    /* 16 byte IP header align */
0794             skb_copy_to_linear_data(skb,
0795                 (unsigned char *)pDB->vaddr, frmlen);
0796             skb_put(skb, frmlen);
0797             skb->protocol = eth_type_trans(skb, dev);
0798             netif_rx(skb);  /* pass the packet to upper layers */
0799         } else {
0800             if (au1000_debug > 4) {
0801                 pr_err("rx_error(s):");
0802                 if (status & RX_MISSED_FRAME)
0803                     pr_cont(" miss");
0804                 if (status & RX_WDOG_TIMER)
0805                     pr_cont(" wdog");
0806                 if (status & RX_RUNT)
0807                     pr_cont(" runt");
0808                 if (status & RX_OVERLEN)
0809                     pr_cont(" overlen");
0810                 if (status & RX_COLL)
0811                     pr_cont(" coll");
0812                 if (status & RX_MII_ERROR)
0813                     pr_cont(" mii error");
0814                 if (status & RX_CRC_ERROR)
0815                     pr_cont(" crc error");
0816                 if (status & RX_LEN_ERROR)
0817                     pr_cont(" len error");
0818                 if (status & RX_U_CNTRL_FRAME)
0819                     pr_cont(" u control frame");
0820                 pr_cont("\n");
0821             }
0822         }
0823         prxd->buff_stat = lower_32_bits(pDB->dma_addr) | RX_DMA_ENABLE;
0824         aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
0825         wmb(); /* drain writebuffer */
0826 
0827         /* next descriptor */
0828         prxd = aup->rx_dma_ring[aup->rx_head];
0829         buff_stat = prxd->buff_stat;
0830     }
0831     return 0;
0832 }
0833 
0834 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
0835 {
0836     struct net_device_stats *ps = &dev->stats;
0837 
0838     if (status & TX_FRAME_ABORTED) {
0839         if (!dev->phydev || (DUPLEX_FULL == dev->phydev->duplex)) {
0840             if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
0841                 /* any other tx errors are only valid
0842                  * in half duplex mode
0843                  */
0844                 ps->tx_errors++;
0845                 ps->tx_aborted_errors++;
0846             }
0847         } else {
0848             ps->tx_errors++;
0849             ps->tx_aborted_errors++;
0850             if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
0851                 ps->tx_carrier_errors++;
0852         }
0853     }
0854 }
0855 
0856 /*
0857  * Called from the interrupt service routine to acknowledge
0858  * the TX DONE bits.  This is a must if the irq is setup as
0859  * edge triggered.
0860  */
0861 static void au1000_tx_ack(struct net_device *dev)
0862 {
0863     struct au1000_private *aup = netdev_priv(dev);
0864     struct tx_dma *ptxd;
0865 
0866     ptxd = aup->tx_dma_ring[aup->tx_tail];
0867 
0868     while (ptxd->buff_stat & TX_T_DONE) {
0869         au1000_update_tx_stats(dev, ptxd->status);
0870         ptxd->buff_stat &= ~TX_T_DONE;
0871         ptxd->len = 0;
0872         wmb(); /* drain writebuffer */
0873 
0874         aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
0875         ptxd = aup->tx_dma_ring[aup->tx_tail];
0876 
0877         if (aup->tx_full) {
0878             aup->tx_full = 0;
0879             netif_wake_queue(dev);
0880         }
0881     }
0882 }
0883 
0884 /*
0885  * Au1000 interrupt service routine.
0886  */
0887 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
0888 {
0889     struct net_device *dev = dev_id;
0890 
0891     /* Handle RX interrupts first to minimize chance of overrun */
0892 
0893     au1000_rx(dev);
0894     au1000_tx_ack(dev);
0895     return IRQ_RETVAL(1);
0896 }
0897 
0898 static int au1000_open(struct net_device *dev)
0899 {
0900     int retval;
0901     struct au1000_private *aup = netdev_priv(dev);
0902 
0903     netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
0904 
0905     retval = request_irq(dev->irq, au1000_interrupt, 0,
0906                     dev->name, dev);
0907     if (retval) {
0908         netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
0909         return retval;
0910     }
0911 
0912     retval = au1000_init(dev);
0913     if (retval) {
0914         netdev_err(dev, "error in au1000_init\n");
0915         free_irq(dev->irq, dev);
0916         return retval;
0917     }
0918 
0919     if (dev->phydev)
0920         phy_start(dev->phydev);
0921 
0922     netif_start_queue(dev);
0923 
0924     netif_dbg(aup, drv, dev, "open: Initialization done.\n");
0925 
0926     return 0;
0927 }
0928 
0929 static int au1000_close(struct net_device *dev)
0930 {
0931     unsigned long flags;
0932     struct au1000_private *const aup = netdev_priv(dev);
0933 
0934     netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
0935 
0936     if (dev->phydev)
0937         phy_stop(dev->phydev);
0938 
0939     spin_lock_irqsave(&aup->lock, flags);
0940 
0941     au1000_reset_mac_unlocked(dev);
0942 
0943     /* stop the device */
0944     netif_stop_queue(dev);
0945 
0946     /* disable the interrupt */
0947     free_irq(dev->irq, dev);
0948     spin_unlock_irqrestore(&aup->lock, flags);
0949 
0950     return 0;
0951 }
0952 
0953 /*
0954  * Au1000 transmit routine.
0955  */
0956 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
0957 {
0958     struct au1000_private *aup = netdev_priv(dev);
0959     struct net_device_stats *ps = &dev->stats;
0960     struct tx_dma *ptxd;
0961     u32 buff_stat;
0962     struct db_dest *pDB;
0963     int i;
0964 
0965     netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
0966                 (unsigned)aup, skb->len,
0967                 skb->data, aup->tx_head);
0968 
0969     ptxd = aup->tx_dma_ring[aup->tx_head];
0970     buff_stat = ptxd->buff_stat;
0971     if (buff_stat & TX_DMA_ENABLE) {
0972         /* We've wrapped around and the transmitter is still busy */
0973         netif_stop_queue(dev);
0974         aup->tx_full = 1;
0975         return NETDEV_TX_BUSY;
0976     } else if (buff_stat & TX_T_DONE) {
0977         au1000_update_tx_stats(dev, ptxd->status);
0978         ptxd->len = 0;
0979     }
0980 
0981     if (aup->tx_full) {
0982         aup->tx_full = 0;
0983         netif_wake_queue(dev);
0984     }
0985 
0986     pDB = aup->tx_db_inuse[aup->tx_head];
0987     skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
0988     if (skb->len < ETH_ZLEN) {
0989         for (i = skb->len; i < ETH_ZLEN; i++)
0990             ((char *)pDB->vaddr)[i] = 0;
0991 
0992         ptxd->len = ETH_ZLEN;
0993     } else
0994         ptxd->len = skb->len;
0995 
0996     ps->tx_packets++;
0997     ps->tx_bytes += ptxd->len;
0998 
0999     ptxd->buff_stat = lower_32_bits(pDB->dma_addr) | TX_DMA_ENABLE;
1000     wmb(); /* drain writebuffer */
1001     dev_kfree_skb(skb);
1002     aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1003     return NETDEV_TX_OK;
1004 }
1005 
1006 /*
1007  * The Tx ring has been full longer than the watchdog timeout
1008  * value. The transmitter must be hung?
1009  */
1010 static void au1000_tx_timeout(struct net_device *dev, unsigned int txqueue)
1011 {
1012     netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1013     au1000_reset_mac(dev);
1014     au1000_init(dev);
1015     netif_trans_update(dev); /* prevent tx timeout */
1016     netif_wake_queue(dev);
1017 }
1018 
1019 static void au1000_multicast_list(struct net_device *dev)
1020 {
1021     struct au1000_private *aup = netdev_priv(dev);
1022     u32 reg;
1023 
1024     netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1025     reg = readl(&aup->mac->control);
1026     if (dev->flags & IFF_PROMISC) {         /* Set promiscuous. */
1027         reg |= MAC_PROMISCUOUS;
1028     } else if ((dev->flags & IFF_ALLMULTI)  ||
1029                netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1030         reg |= MAC_PASS_ALL_MULTI;
1031         reg &= ~MAC_PROMISCUOUS;
1032         netdev_info(dev, "Pass all multicast\n");
1033     } else {
1034         struct netdev_hw_addr *ha;
1035         u32 mc_filter[2];   /* Multicast hash filter */
1036 
1037         mc_filter[1] = mc_filter[0] = 0;
1038         netdev_for_each_mc_addr(ha, dev)
1039             set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1040                     (long *)mc_filter);
1041         writel(mc_filter[1], &aup->mac->multi_hash_high);
1042         writel(mc_filter[0], &aup->mac->multi_hash_low);
1043         reg &= ~MAC_PROMISCUOUS;
1044         reg |= MAC_HASH_MODE;
1045     }
1046     writel(reg, &aup->mac->control);
1047 }
1048 
1049 static const struct net_device_ops au1000_netdev_ops = {
1050     .ndo_open       = au1000_open,
1051     .ndo_stop       = au1000_close,
1052     .ndo_start_xmit     = au1000_tx,
1053     .ndo_set_rx_mode    = au1000_multicast_list,
1054     .ndo_eth_ioctl      = phy_do_ioctl_running,
1055     .ndo_tx_timeout     = au1000_tx_timeout,
1056     .ndo_set_mac_address    = eth_mac_addr,
1057     .ndo_validate_addr  = eth_validate_addr,
1058 };
1059 
1060 static int au1000_probe(struct platform_device *pdev)
1061 {
1062     struct au1000_private *aup = NULL;
1063     struct au1000_eth_platform_data *pd;
1064     struct net_device *dev = NULL;
1065     struct db_dest *pDB, *pDBfree;
1066     int irq, i, err = 0;
1067     struct resource *base, *macen, *macdma;
1068 
1069     base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1070     if (!base) {
1071         dev_err(&pdev->dev, "failed to retrieve base register\n");
1072         err = -ENODEV;
1073         goto out;
1074     }
1075 
1076     macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1077     if (!macen) {
1078         dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1079         err = -ENODEV;
1080         goto out;
1081     }
1082 
1083     irq = platform_get_irq(pdev, 0);
1084     if (irq < 0) {
1085         err = -ENODEV;
1086         goto out;
1087     }
1088 
1089     macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1090     if (!macdma) {
1091         dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1092         err = -ENODEV;
1093         goto out;
1094     }
1095 
1096     if (!request_mem_region(base->start, resource_size(base),
1097                             pdev->name)) {
1098         dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1099         err = -ENXIO;
1100         goto out;
1101     }
1102 
1103     if (!request_mem_region(macen->start, resource_size(macen),
1104                             pdev->name)) {
1105         dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1106         err = -ENXIO;
1107         goto err_request;
1108     }
1109 
1110     if (!request_mem_region(macdma->start, resource_size(macdma),
1111                             pdev->name)) {
1112         dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1113         err = -ENXIO;
1114         goto err_macdma;
1115     }
1116 
1117     dev = alloc_etherdev(sizeof(struct au1000_private));
1118     if (!dev) {
1119         err = -ENOMEM;
1120         goto err_alloc;
1121     }
1122 
1123     SET_NETDEV_DEV(dev, &pdev->dev);
1124     platform_set_drvdata(pdev, dev);
1125     aup = netdev_priv(dev);
1126 
1127     spin_lock_init(&aup->lock);
1128     aup->msg_enable = (au1000_debug < 4 ?
1129                 AU1000_DEF_MSG_ENABLE : au1000_debug);
1130 
1131     /* Allocate the data buffers
1132      * Snooping works fine with eth on all au1xxx
1133      */
1134     aup->vaddr = dma_alloc_coherent(&pdev->dev, MAX_BUF_SIZE *
1135                     (NUM_TX_BUFFS + NUM_RX_BUFFS),
1136                     &aup->dma_addr, 0);
1137     if (!aup->vaddr) {
1138         dev_err(&pdev->dev, "failed to allocate data buffers\n");
1139         err = -ENOMEM;
1140         goto err_vaddr;
1141     }
1142 
1143     /* aup->mac is the base address of the MAC's registers */
1144     aup->mac = (struct mac_reg *)
1145             ioremap(base->start, resource_size(base));
1146     if (!aup->mac) {
1147         dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1148         err = -ENXIO;
1149         goto err_remap1;
1150     }
1151 
1152     /* Setup some variables for quick register address access */
1153     aup->enable = (u32 *)ioremap(macen->start,
1154                         resource_size(macen));
1155     if (!aup->enable) {
1156         dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1157         err = -ENXIO;
1158         goto err_remap2;
1159     }
1160     aup->mac_id = pdev->id;
1161 
1162     aup->macdma = ioremap(macdma->start, resource_size(macdma));
1163     if (!aup->macdma) {
1164         dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1165         err = -ENXIO;
1166         goto err_remap3;
1167     }
1168 
1169     au1000_setup_hw_rings(aup, aup->macdma);
1170 
1171     writel(0, aup->enable);
1172     aup->mac_enabled = 0;
1173 
1174     pd = dev_get_platdata(&pdev->dev);
1175     if (!pd) {
1176         dev_info(&pdev->dev, "no platform_data passed,"
1177                     " PHY search on MAC0\n");
1178         aup->phy1_search_mac0 = 1;
1179     } else {
1180         if (is_valid_ether_addr(pd->mac)) {
1181             eth_hw_addr_set(dev, pd->mac);
1182         } else {
1183             /* Set a random MAC since no valid provided by platform_data. */
1184             eth_hw_addr_random(dev);
1185         }
1186 
1187         aup->phy_static_config = pd->phy_static_config;
1188         aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1189         aup->phy1_search_mac0 = pd->phy1_search_mac0;
1190         aup->phy_addr = pd->phy_addr;
1191         aup->phy_busid = pd->phy_busid;
1192         aup->phy_irq = pd->phy_irq;
1193     }
1194 
1195     if (aup->phy_busid > 0) {
1196         dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1197         err = -ENODEV;
1198         goto err_mdiobus_alloc;
1199     }
1200 
1201     aup->mii_bus = mdiobus_alloc();
1202     if (aup->mii_bus == NULL) {
1203         dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1204         err = -ENOMEM;
1205         goto err_mdiobus_alloc;
1206     }
1207 
1208     aup->mii_bus->priv = dev;
1209     aup->mii_bus->read = au1000_mdiobus_read;
1210     aup->mii_bus->write = au1000_mdiobus_write;
1211     aup->mii_bus->reset = au1000_mdiobus_reset;
1212     aup->mii_bus->name = "au1000_eth_mii";
1213     snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1214         pdev->name, aup->mac_id);
1215 
1216     /* if known, set corresponding PHY IRQs */
1217     if (aup->phy_static_config)
1218         if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1219             aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1220 
1221     err = mdiobus_register(aup->mii_bus);
1222     if (err) {
1223         dev_err(&pdev->dev, "failed to register MDIO bus\n");
1224         goto err_mdiobus_reg;
1225     }
1226 
1227     err = au1000_mii_probe(dev);
1228     if (err != 0)
1229         goto err_out;
1230 
1231     pDBfree = NULL;
1232     /* setup the data buffer descriptors and attach a buffer to each one */
1233     pDB = aup->db;
1234     for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1235         pDB->pnext = pDBfree;
1236         pDBfree = pDB;
1237         pDB->vaddr = aup->vaddr + MAX_BUF_SIZE * i;
1238         pDB->dma_addr = aup->dma_addr + MAX_BUF_SIZE * i;
1239         pDB++;
1240     }
1241     aup->pDBfree = pDBfree;
1242 
1243     err = -ENODEV;
1244     for (i = 0; i < NUM_RX_DMA; i++) {
1245         pDB = au1000_GetFreeDB(aup);
1246         if (!pDB)
1247             goto err_out;
1248 
1249         aup->rx_dma_ring[i]->buff_stat = lower_32_bits(pDB->dma_addr);
1250         aup->rx_db_inuse[i] = pDB;
1251     }
1252 
1253     for (i = 0; i < NUM_TX_DMA; i++) {
1254         pDB = au1000_GetFreeDB(aup);
1255         if (!pDB)
1256             goto err_out;
1257 
1258         aup->tx_dma_ring[i]->buff_stat = lower_32_bits(pDB->dma_addr);
1259         aup->tx_dma_ring[i]->len = 0;
1260         aup->tx_db_inuse[i] = pDB;
1261     }
1262 
1263     dev->base_addr = base->start;
1264     dev->irq = irq;
1265     dev->netdev_ops = &au1000_netdev_ops;
1266     dev->ethtool_ops = &au1000_ethtool_ops;
1267     dev->watchdog_timeo = ETH_TX_TIMEOUT;
1268 
1269     /*
1270      * The boot code uses the ethernet controller, so reset it to start
1271      * fresh.  au1000_init() expects that the device is in reset state.
1272      */
1273     au1000_reset_mac(dev);
1274 
1275     err = register_netdev(dev);
1276     if (err) {
1277         netdev_err(dev, "Cannot register net device, aborting.\n");
1278         goto err_out;
1279     }
1280 
1281     netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1282             (unsigned long)base->start, irq);
1283 
1284     return 0;
1285 
1286 err_out:
1287     if (aup->mii_bus != NULL)
1288         mdiobus_unregister(aup->mii_bus);
1289 
1290     /* here we should have a valid dev plus aup-> register addresses
1291      * so we can reset the mac properly.
1292      */
1293     au1000_reset_mac(dev);
1294 
1295     for (i = 0; i < NUM_RX_DMA; i++) {
1296         if (aup->rx_db_inuse[i])
1297             au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1298     }
1299     for (i = 0; i < NUM_TX_DMA; i++) {
1300         if (aup->tx_db_inuse[i])
1301             au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1302     }
1303 err_mdiobus_reg:
1304     mdiobus_free(aup->mii_bus);
1305 err_mdiobus_alloc:
1306     iounmap(aup->macdma);
1307 err_remap3:
1308     iounmap(aup->enable);
1309 err_remap2:
1310     iounmap(aup->mac);
1311 err_remap1:
1312     dma_free_coherent(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1313               aup->vaddr, aup->dma_addr);
1314 err_vaddr:
1315     free_netdev(dev);
1316 err_alloc:
1317     release_mem_region(macdma->start, resource_size(macdma));
1318 err_macdma:
1319     release_mem_region(macen->start, resource_size(macen));
1320 err_request:
1321     release_mem_region(base->start, resource_size(base));
1322 out:
1323     return err;
1324 }
1325 
1326 static int au1000_remove(struct platform_device *pdev)
1327 {
1328     struct net_device *dev = platform_get_drvdata(pdev);
1329     struct au1000_private *aup = netdev_priv(dev);
1330     int i;
1331     struct resource *base, *macen;
1332 
1333     unregister_netdev(dev);
1334     mdiobus_unregister(aup->mii_bus);
1335     mdiobus_free(aup->mii_bus);
1336 
1337     for (i = 0; i < NUM_RX_DMA; i++)
1338         if (aup->rx_db_inuse[i])
1339             au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1340 
1341     for (i = 0; i < NUM_TX_DMA; i++)
1342         if (aup->tx_db_inuse[i])
1343             au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1344 
1345     dma_free_coherent(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1346               aup->vaddr, aup->dma_addr);
1347 
1348     iounmap(aup->macdma);
1349     iounmap(aup->mac);
1350     iounmap(aup->enable);
1351 
1352     base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1353     release_mem_region(base->start, resource_size(base));
1354 
1355     base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356     release_mem_region(base->start, resource_size(base));
1357 
1358     macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1359     release_mem_region(macen->start, resource_size(macen));
1360 
1361     free_netdev(dev);
1362 
1363     return 0;
1364 }
1365 
1366 static struct platform_driver au1000_eth_driver = {
1367     .probe  = au1000_probe,
1368     .remove = au1000_remove,
1369     .driver = {
1370         .name   = "au1000-eth",
1371     },
1372 };
1373 
1374 module_platform_driver(au1000_eth_driver);
1375 
1376 MODULE_ALIAS("platform:au1000-eth");
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