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0001 /* 0002 * Amiga Linux/m68k Ariadne Ethernet Driver 0003 * 0004 * © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org) 0005 * Peter De Schrijver 0006 * (Peter.DeSchrijver@linux.cc.kuleuven.ac.be) 0007 * 0008 * ---------------------------------------------------------------------------------- 0009 * 0010 * This program is based on 0011 * 0012 * lance.c: An AMD LANCE ethernet driver for linux. 0013 * Written 1993-94 by Donald Becker. 0014 * 0015 * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller 0016 * Advanced Micro Devices 0017 * Publication #16907, Rev. B, Amendment/0, May 1994 0018 * 0019 * MC68230: Parallel Interface/Timer (PI/T) 0020 * Motorola Semiconductors, December, 1983 0021 * 0022 * ---------------------------------------------------------------------------------- 0023 * 0024 * This file is subject to the terms and conditions of the GNU General Public 0025 * License. See the file COPYING in the main directory of the Linux 0026 * distribution for more details. 0027 * 0028 * ---------------------------------------------------------------------------------- 0029 * 0030 * The Ariadne is a Zorro-II board made by Village Tronic. It contains: 0031 * 0032 * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both 0033 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors 0034 * 0035 * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports 0036 */ 0037 0038 0039 /* 0040 * Am79C960 PCnet-ISA 0041 */ 0042 0043 struct Am79C960 { 0044 volatile u_short AddressPROM[8]; 0045 /* IEEE Address PROM (Unused in the Ariadne) */ 0046 volatile u_short RDP; /* Register Data Port */ 0047 volatile u_short RAP; /* Register Address Port */ 0048 volatile u_short Reset; /* Reset Chip on Read Access */ 0049 volatile u_short IDP; /* ISACSR Data Port */ 0050 }; 0051 0052 0053 /* 0054 * Am79C960 Control and Status Registers 0055 * 0056 * These values are already swap()ed!! 0057 * 0058 * Only registers marked with a `-' are intended for network software 0059 * access 0060 */ 0061 0062 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ 0063 #define CSR1 0x0100 /* - IADR[15:0] */ 0064 #define CSR2 0x0200 /* - IADR[23:16] */ 0065 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ 0066 #define CSR4 0x0400 /* - Test and Features Control */ 0067 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */ 0068 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ 0069 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */ 0070 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */ 0071 #define CSR11 0x0b00 /* - Logical Address Filter, LADRF[63:48] */ 0072 #define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */ 0073 #define CSR13 0x0d00 /* - Physical Address Register, PADR[31:16] */ 0074 #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */ 0075 #define CSR15 0x0f00 /* - Mode Register */ 0076 #define CSR16 0x1000 /* Initialization Block Address Lower */ 0077 #define CSR17 0x1100 /* Initialization Block Address Upper */ 0078 #define CSR18 0x1200 /* Current Receive Buffer Address */ 0079 #define CSR19 0x1300 /* Current Receive Buffer Address */ 0080 #define CSR20 0x1400 /* Current Transmit Buffer Address */ 0081 #define CSR21 0x1500 /* Current Transmit Buffer Address */ 0082 #define CSR22 0x1600 /* Next Receive Buffer Address */ 0083 #define CSR23 0x1700 /* Next Receive Buffer Address */ 0084 #define CSR24 0x1800 /* - Base Address of Receive Ring */ 0085 #define CSR25 0x1900 /* - Base Address of Receive Ring */ 0086 #define CSR26 0x1a00 /* Next Receive Descriptor Address */ 0087 #define CSR27 0x1b00 /* Next Receive Descriptor Address */ 0088 #define CSR28 0x1c00 /* Current Receive Descriptor Address */ 0089 #define CSR29 0x1d00 /* Current Receive Descriptor Address */ 0090 #define CSR30 0x1e00 /* - Base Address of Transmit Ring */ 0091 #define CSR31 0x1f00 /* - Base Address of transmit Ring */ 0092 #define CSR32 0x2000 /* Next Transmit Descriptor Address */ 0093 #define CSR33 0x2100 /* Next Transmit Descriptor Address */ 0094 #define CSR34 0x2200 /* Current Transmit Descriptor Address */ 0095 #define CSR35 0x2300 /* Current Transmit Descriptor Address */ 0096 #define CSR36 0x2400 /* Next Next Receive Descriptor Address */ 0097 #define CSR37 0x2500 /* Next Next Receive Descriptor Address */ 0098 #define CSR38 0x2600 /* Next Next Transmit Descriptor Address */ 0099 #define CSR39 0x2700 /* Next Next Transmit Descriptor Address */ 0100 #define CSR40 0x2800 /* Current Receive Status and Byte Count */ 0101 #define CSR41 0x2900 /* Current Receive Status and Byte Count */ 0102 #define CSR42 0x2a00 /* Current Transmit Status and Byte Count */ 0103 #define CSR43 0x2b00 /* Current Transmit Status and Byte Count */ 0104 #define CSR44 0x2c00 /* Next Receive Status and Byte Count */ 0105 #define CSR45 0x2d00 /* Next Receive Status and Byte Count */ 0106 #define CSR46 0x2e00 /* Poll Time Counter */ 0107 #define CSR47 0x2f00 /* Polling Interval */ 0108 #define CSR48 0x3000 /* Temporary Storage */ 0109 #define CSR49 0x3100 /* Temporary Storage */ 0110 #define CSR50 0x3200 /* Temporary Storage */ 0111 #define CSR51 0x3300 /* Temporary Storage */ 0112 #define CSR52 0x3400 /* Temporary Storage */ 0113 #define CSR53 0x3500 /* Temporary Storage */ 0114 #define CSR54 0x3600 /* Temporary Storage */ 0115 #define CSR55 0x3700 /* Temporary Storage */ 0116 #define CSR56 0x3800 /* Temporary Storage */ 0117 #define CSR57 0x3900 /* Temporary Storage */ 0118 #define CSR58 0x3a00 /* Temporary Storage */ 0119 #define CSR59 0x3b00 /* Temporary Storage */ 0120 #define CSR60 0x3c00 /* Previous Transmit Descriptor Address */ 0121 #define CSR61 0x3d00 /* Previous Transmit Descriptor Address */ 0122 #define CSR62 0x3e00 /* Previous Transmit Status and Byte Count */ 0123 #define CSR63 0x3f00 /* Previous Transmit Status and Byte Count */ 0124 #define CSR64 0x4000 /* Next Transmit Buffer Address */ 0125 #define CSR65 0x4100 /* Next Transmit Buffer Address */ 0126 #define CSR66 0x4200 /* Next Transmit Status and Byte Count */ 0127 #define CSR67 0x4300 /* Next Transmit Status and Byte Count */ 0128 #define CSR68 0x4400 /* Transmit Status Temporary Storage */ 0129 #define CSR69 0x4500 /* Transmit Status Temporary Storage */ 0130 #define CSR70 0x4600 /* Temporary Storage */ 0131 #define CSR71 0x4700 /* Temporary Storage */ 0132 #define CSR72 0x4800 /* Receive Ring Counter */ 0133 #define CSR74 0x4a00 /* Transmit Ring Counter */ 0134 #define CSR76 0x4c00 /* - Receive Ring Length */ 0135 #define CSR78 0x4e00 /* - Transmit Ring Length */ 0136 #define CSR80 0x5000 /* - Burst and FIFO Threshold Control */ 0137 #define CSR82 0x5200 /* - Bus Activity Timer */ 0138 #define CSR84 0x5400 /* DMA Address */ 0139 #define CSR85 0x5500 /* DMA Address */ 0140 #define CSR86 0x5600 /* Buffer Byte Counter */ 0141 #define CSR88 0x5800 /* - Chip ID */ 0142 #define CSR89 0x5900 /* - Chip ID */ 0143 #define CSR92 0x5c00 /* Ring Length Conversion */ 0144 #define CSR94 0x5e00 /* Transmit Time Domain Reflectometry Count */ 0145 #define CSR96 0x6000 /* Bus Interface Scratch Register 0 */ 0146 #define CSR97 0x6100 /* Bus Interface Scratch Register 0 */ 0147 #define CSR98 0x6200 /* Bus Interface Scratch Register 1 */ 0148 #define CSR99 0x6300 /* Bus Interface Scratch Register 1 */ 0149 #define CSR104 0x6800 /* SWAP */ 0150 #define CSR105 0x6900 /* SWAP */ 0151 #define CSR108 0x6c00 /* Buffer Management Scratch */ 0152 #define CSR109 0x6d00 /* Buffer Management Scratch */ 0153 #define CSR112 0x7000 /* - Missed Frame Count */ 0154 #define CSR114 0x7200 /* - Receive Collision Count */ 0155 #define CSR124 0x7c00 /* - Buffer Management Unit Test */ 0156 0157 0158 /* 0159 * Am79C960 ISA Control and Status Registers 0160 * 0161 * These values are already swap()ed!! 0162 */ 0163 0164 #define ISACSR0 0x0000 /* Master Mode Read Active */ 0165 #define ISACSR1 0x0100 /* Master Mode Write Active */ 0166 #define ISACSR2 0x0200 /* Miscellaneous Configuration */ 0167 #define ISACSR4 0x0400 /* LED0 Status (Link Integrity) */ 0168 #define ISACSR5 0x0500 /* LED1 Status */ 0169 #define ISACSR6 0x0600 /* LED2 Status */ 0170 #define ISACSR7 0x0700 /* LED3 Status */ 0171 0172 0173 /* 0174 * Bit definitions for CSR0 (PCnet-ISA Controller Status) 0175 * 0176 * These values are already swap()ed!! 0177 */ 0178 0179 #define ERR 0x0080 /* Error */ 0180 #define BABL 0x0040 /* Babble: Transmitted too many bits */ 0181 #define CERR 0x0020 /* No Heartbeat (10BASE-T) */ 0182 #define MISS 0x0010 /* Missed Frame */ 0183 #define MERR 0x0008 /* Memory Error */ 0184 #define RINT 0x0004 /* Receive Interrupt */ 0185 #define TINT 0x0002 /* Transmit Interrupt */ 0186 #define IDON 0x0001 /* Initialization Done */ 0187 #define INTR 0x8000 /* Interrupt Flag */ 0188 #define INEA 0x4000 /* Interrupt Enable */ 0189 #define RXON 0x2000 /* Receive On */ 0190 #define TXON 0x1000 /* Transmit On */ 0191 #define TDMD 0x0800 /* Transmit Demand */ 0192 #define STOP 0x0400 /* Stop */ 0193 #define STRT 0x0200 /* Start */ 0194 #define INIT 0x0100 /* Initialize */ 0195 0196 0197 /* 0198 * Bit definitions for CSR3 (Interrupt Masks and Deferral Control) 0199 * 0200 * These values are already swap()ed!! 0201 */ 0202 0203 #define BABLM 0x0040 /* Babble Mask */ 0204 #define MISSM 0x0010 /* Missed Frame Mask */ 0205 #define MERRM 0x0008 /* Memory Error Mask */ 0206 #define RINTM 0x0004 /* Receive Interrupt Mask */ 0207 #define TINTM 0x0002 /* Transmit Interrupt Mask */ 0208 #define IDONM 0x0001 /* Initialization Done Mask */ 0209 #define DXMT2PD 0x1000 /* Disable Transmit Two Part Deferral */ 0210 #define EMBA 0x0800 /* Enable Modified Back-off Algorithm */ 0211 0212 0213 /* 0214 * Bit definitions for CSR4 (Test and Features Control) 0215 * 0216 * These values are already swap()ed!! 0217 */ 0218 0219 #define ENTST 0x0080 /* Enable Test Mode */ 0220 #define DMAPLUS 0x0040 /* Disable Burst Transaction Counter */ 0221 #define TIMER 0x0020 /* Timer Enable Register */ 0222 #define DPOLL 0x0010 /* Disable Transmit Polling */ 0223 #define APAD_XMT 0x0008 /* Auto Pad Transmit */ 0224 #define ASTRP_RCV 0x0004 /* Auto Pad Stripping */ 0225 #define MFCO 0x0002 /* Missed Frame Counter Overflow Interrupt */ 0226 #define MFCOM 0x0001 /* Missed Frame Counter Overflow Mask */ 0227 #define RCVCCO 0x2000 /* Receive Collision Counter Overflow Interrupt */ 0228 #define RCVCCOM 0x1000 /* Receive Collision Counter Overflow Mask */ 0229 #define TXSTRT 0x0800 /* Transmit Start Status */ 0230 #define TXSTRTM 0x0400 /* Transmit Start Mask */ 0231 #define JAB 0x0200 /* Jabber Error */ 0232 #define JABM 0x0100 /* Jabber Error Mask */ 0233 0234 0235 /* 0236 * Bit definitions for CSR15 (Mode Register) 0237 * 0238 * These values are already swap()ed!! 0239 */ 0240 0241 #define PROM 0x0080 /* Promiscuous Mode */ 0242 #define DRCVBC 0x0040 /* Disable Receive Broadcast */ 0243 #define DRCVPA 0x0020 /* Disable Receive Physical Address */ 0244 #define DLNKTST 0x0010 /* Disable Link Status */ 0245 #define DAPC 0x0008 /* Disable Automatic Polarity Correction */ 0246 #define MENDECL 0x0004 /* MENDEC Loopback Mode */ 0247 #define LRTTSEL 0x0002 /* Low Receive Threshold/Transmit Mode Select */ 0248 #define PORTSEL1 0x0001 /* Port Select Bits */ 0249 #define PORTSEL2 0x8000 /* Port Select Bits */ 0250 #define INTL 0x4000 /* Internal Loopback */ 0251 #define DRTY 0x2000 /* Disable Retry */ 0252 #define FCOLL 0x1000 /* Force Collision */ 0253 #define DXMTFCS 0x0800 /* Disable Transmit CRC */ 0254 #define LOOP 0x0400 /* Loopback Enable */ 0255 #define DTX 0x0200 /* Disable Transmitter */ 0256 #define DRX 0x0100 /* Disable Receiver */ 0257 0258 0259 /* 0260 * Bit definitions for ISACSR2 (Miscellaneous Configuration) 0261 * 0262 * These values are already swap()ed!! 0263 */ 0264 0265 #define ASEL 0x0200 /* Media Interface Port Auto Select */ 0266 0267 0268 /* 0269 * Bit definitions for ISACSR5-7 (LED1-3 Status) 0270 * 0271 * These values are already swap()ed!! 0272 */ 0273 0274 #define LEDOUT 0x0080 /* Current LED Status */ 0275 #define PSE 0x8000 /* Pulse Stretcher Enable */ 0276 #define XMTE 0x1000 /* Enable Transmit Status Signal */ 0277 #define RVPOLE 0x0800 /* Enable Receive Polarity Signal */ 0278 #define RCVE 0x0400 /* Enable Receive Status Signal */ 0279 #define JABE 0x0200 /* Enable Jabber Signal */ 0280 #define COLE 0x0100 /* Enable Collision Signal */ 0281 0282 0283 /* 0284 * Receive Descriptor Ring Entry 0285 */ 0286 0287 struct RDRE { 0288 volatile u_short RMD0; /* LADR[15:0] */ 0289 volatile u_short RMD1; /* HADR[23:16] | Receive Flags */ 0290 volatile u_short RMD2; /* Buffer Byte Count (two's complement) */ 0291 volatile u_short RMD3; /* Message Byte Count */ 0292 }; 0293 0294 0295 /* 0296 * Transmit Descriptor Ring Entry 0297 */ 0298 0299 struct TDRE { 0300 volatile u_short TMD0; /* LADR[15:0] */ 0301 volatile u_short TMD1; /* HADR[23:16] | Transmit Flags */ 0302 volatile u_short TMD2; /* Buffer Byte Count (two's complement) */ 0303 volatile u_short TMD3; /* Error Flags */ 0304 }; 0305 0306 0307 /* 0308 * Receive Flags 0309 */ 0310 0311 #define RF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */ 0312 #define RF_ERR 0x0040 /* Error */ 0313 #define RF_FRAM 0x0020 /* Framing Error */ 0314 #define RF_OFLO 0x0010 /* Overflow Error */ 0315 #define RF_CRC 0x0008 /* CRC Error */ 0316 #define RF_BUFF 0x0004 /* Buffer Error */ 0317 #define RF_STP 0x0002 /* Start of Packet */ 0318 #define RF_ENP 0x0001 /* End of Packet */ 0319 0320 0321 /* 0322 * Transmit Flags 0323 */ 0324 0325 #define TF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */ 0326 #define TF_ERR 0x0040 /* Error */ 0327 #define TF_ADD_FCS 0x0020 /* Controls FCS Generation */ 0328 #define TF_MORE 0x0010 /* More than one retry needed */ 0329 #define TF_ONE 0x0008 /* One retry needed */ 0330 #define TF_DEF 0x0004 /* Deferred */ 0331 #define TF_STP 0x0002 /* Start of Packet */ 0332 #define TF_ENP 0x0001 /* End of Packet */ 0333 0334 0335 /* 0336 * Error Flags 0337 */ 0338 0339 #define EF_BUFF 0x0080 /* Buffer Error */ 0340 #define EF_UFLO 0x0040 /* Underflow Error */ 0341 #define EF_LCOL 0x0010 /* Late Collision */ 0342 #define EF_LCAR 0x0008 /* Loss of Carrier */ 0343 #define EF_RTRY 0x0004 /* Retry Error */ 0344 #define EF_TDR 0xff03 /* Time Domain Reflectometry */ 0345 0346 0347 0348 /* 0349 * MC68230 Parallel Interface/Timer 0350 */ 0351 0352 struct MC68230 { 0353 volatile u_char PGCR; /* Port General Control Register */ 0354 u_char Pad1[1]; 0355 volatile u_char PSRR; /* Port Service Request Register */ 0356 u_char Pad2[1]; 0357 volatile u_char PADDR; /* Port A Data Direction Register */ 0358 u_char Pad3[1]; 0359 volatile u_char PBDDR; /* Port B Data Direction Register */ 0360 u_char Pad4[1]; 0361 volatile u_char PCDDR; /* Port C Data Direction Register */ 0362 u_char Pad5[1]; 0363 volatile u_char PIVR; /* Port Interrupt Vector Register */ 0364 u_char Pad6[1]; 0365 volatile u_char PACR; /* Port A Control Register */ 0366 u_char Pad7[1]; 0367 volatile u_char PBCR; /* Port B Control Register */ 0368 u_char Pad8[1]; 0369 volatile u_char PADR; /* Port A Data Register */ 0370 u_char Pad9[1]; 0371 volatile u_char PBDR; /* Port B Data Register */ 0372 u_char Pad10[1]; 0373 volatile u_char PAAR; /* Port A Alternate Register */ 0374 u_char Pad11[1]; 0375 volatile u_char PBAR; /* Port B Alternate Register */ 0376 u_char Pad12[1]; 0377 volatile u_char PCDR; /* Port C Data Register */ 0378 u_char Pad13[1]; 0379 volatile u_char PSR; /* Port Status Register */ 0380 u_char Pad14[5]; 0381 volatile u_char TCR; /* Timer Control Register */ 0382 u_char Pad15[1]; 0383 volatile u_char TIVR; /* Timer Interrupt Vector Register */ 0384 u_char Pad16[3]; 0385 volatile u_char CPRH; /* Counter Preload Register (High) */ 0386 u_char Pad17[1]; 0387 volatile u_char CPRM; /* Counter Preload Register (Mid) */ 0388 u_char Pad18[1]; 0389 volatile u_char CPRL; /* Counter Preload Register (Low) */ 0390 u_char Pad19[3]; 0391 volatile u_char CNTRH; /* Count Register (High) */ 0392 u_char Pad20[1]; 0393 volatile u_char CNTRM; /* Count Register (Mid) */ 0394 u_char Pad21[1]; 0395 volatile u_char CNTRL; /* Count Register (Low) */ 0396 u_char Pad22[1]; 0397 volatile u_char TSR; /* Timer Status Register */ 0398 u_char Pad23[11]; 0399 }; 0400 0401 0402 /* 0403 * Ariadne Expansion Board Structure 0404 */ 0405 0406 #define ARIADNE_LANCE 0x360 0407 0408 #define ARIADNE_PIT 0x1000 0409 0410 #define ARIADNE_BOOTPROM 0x4000 /* I guess it's here :-) */ 0411 #define ARIADNE_BOOTPROM_SIZE 0x4000 0412 0413 #define ARIADNE_RAM 0x8000 /* Always access WORDs!! */ 0414 #define ARIADNE_RAM_SIZE 0x8000 0415
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