ethernet/amd/amd8111e.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
0004  * Copyright (C) 2003 Advanced Micro Devices
0005  *
0006
0007 Module Name:
0008
0009     amd8111e.h
0010
0011 Abstract:
0012
0013      AMD8111 based 10/100 Ethernet Controller driver definitions.
0014
0015 Environment:
0016
0017     Kernel Mode
0018
0019 Revision History:
0020     3.0.0
0021        Initial Revision.
0022     3.0.1
0023 */
0024
0025 #ifndef _AMD811E_H
0026 #define _AMD811E_H
0027
0028 /* Command style register access
0029
0030 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register.
0031
0032 eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
0033
0034 */
0035
0036 /*  Offset for Memory Mapped Registers. */
0037 /* 32 bit registers */
0038
0039 #define  ASF_STAT       0x00    /* ASF status register */
0040 #define CHIPID          0x04    /* Chip ID register */
0041 #define MIB_DATA        0x10    /* MIB data register */
0042 #define MIB_ADDR        0x14    /* MIB address register */
0043 #define STAT0           0x30    /* Status0 register */
0044 #define INT0            0x38    /* Interrupt0 register */
0045 #define INTEN0          0x40    /* Interrupt0  enable register*/
0046 #define CMD0            0x48    /* Command0 register */
0047 #define CMD2            0x50    /* Command2 register */
0048 #define CMD3            0x54    /* Command3 resiter */
0049 #define CMD7            0x64    /* Command7 register */
0050
0051 #define CTRL1           0x6C    /* Control1 register */
0052 #define CTRL2           0x70    /* Control2 register */
0053
0054 #define XMT_RING_LIMIT      0x7C    /* Transmit ring limit register */
0055
0056 #define AUTOPOLL0       0x88    /* Auto-poll0 register */
0057 #define AUTOPOLL1       0x8A    /* Auto-poll1 register */
0058 #define AUTOPOLL2       0x8C    /* Auto-poll2 register */
0059 #define AUTOPOLL3       0x8E    /* Auto-poll3 register */
0060 #define AUTOPOLL4       0x90    /* Auto-poll4 register */
0061 #define AUTOPOLL5       0x92    /* Auto-poll5 register */
0062
0063 #define AP_VALUE        0x98    /* Auto-poll value register */
0064 #define DLY_INT_A       0xA8    /* Group A delayed interrupt register */
0065 #define DLY_INT_B       0xAC    /* Group B delayed interrupt register */
0066
0067 #define FLOW_CONTROL        0xC8    /* Flow control register */
0068 #define PHY_ACCESS      0xD0    /* PHY access register */
0069
0070 #define STVAL           0xD8    /* Software timer value register */
0071
0072 #define XMT_RING_BASE_ADDR0 0x100   /* Transmit ring0 base addr register */
0073 #define XMT_RING_BASE_ADDR1 0x108   /* Transmit ring1 base addr register */
0074 #define XMT_RING_BASE_ADDR2 0x110   /* Transmit ring2 base addr register */
0075 #define XMT_RING_BASE_ADDR3 0x118   /* Transmit ring2 base addr register */
0076
0077 #define RCV_RING_BASE_ADDR0 0x120   /* Transmit ring0 base addr register */
0078
0079 #define PMAT0           0x190   /* OnNow pattern register0 */
0080 #define PMAT1           0x194   /* OnNow pattern register1 */
0081
0082 /* 16bit registers */
0083
0084 #define XMT_RING_LEN0       0x140   /* Transmit Ring0 length register */
0085 #define XMT_RING_LEN1       0x144   /* Transmit Ring1 length register */
0086 #define XMT_RING_LEN2       0x148   /* Transmit Ring2 length register */
0087 #define XMT_RING_LEN3       0x14C   /* Transmit Ring3 length register */
0088
0089 #define RCV_RING_LEN0       0x150   /* Receive Ring0 length register */
0090
0091 #define SRAM_SIZE       0x178   /* SRAM size register */
0092 #define SRAM_BOUNDARY       0x17A   /* SRAM boundary register */
0093
0094 /* 48bit register */
0095
0096 #define PADR            0x160   /* Physical address register */
0097
0098 #define IFS1            0x18C   /* Inter-frame spacing Part1 register */
0099 #define IFS         0x18D   /* Inter-frame spacing register */
0100 #define IPG         0x18E   /* Inter-frame gap register */
0101 /* 64bit register */
0102
0103 #define LADRF           0x168   /* Logical address filter register */
0104
0105
0106 /* Register Bit Definitions */
0107 typedef enum {
0108
0109     ASF_INIT_DONE       = (1 << 1),
0110     ASF_INIT_PRESENT    = (1 << 0),
0111
0112 }STAT_ASF_BITS;
0113
0114 typedef enum {
0115
0116     MIB_CMD_ACTIVE      = (1 << 15 ),
0117     MIB_RD_CMD      = (1 << 13 ),
0118     MIB_CLEAR       = (1 << 12 ),
0119     MIB_ADDRESS     = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
0120                     (1 << 4) | (1 << 5),
0121 }MIB_ADDR_BITS;
0122
0123
0124 typedef enum {
0125
0126     PMAT_DET        = (1 << 12),
0127     MP_DET              = (1 << 11),
0128     LC_DET          = (1 << 10),
0129     SPEED_MASK      = (1 << 9)|(1 << 8)|(1 << 7),
0130     FULL_DPLX       = (1 << 6),
0131     LINK_STATS      = (1 << 5),
0132     AUTONEG_COMPLETE    = (1 << 4),
0133     MIIPD           = (1 << 3),
0134     RX_SUSPENDED        = (1 << 2),
0135     TX_SUSPENDED        = (1 << 1),
0136     RUNNING         = (1 << 0),
0137
0138 }STAT0_BITS;
0139
0140 #define PHY_SPEED_10        0x2
0141 #define PHY_SPEED_100       0x3
0142
0143 /* INT0             0x38, 32bit register */
0144 typedef enum {
0145
0146     INTR            = (1 << 31),
0147     PCSINT          = (1 << 28),
0148     LCINT           = (1 << 27),
0149     APINT5          = (1 << 26),
0150     APINT4          = (1 << 25),
0151     APINT3          = (1 << 24),
0152     TINT_SUM        = (1 << 23),
0153     APINT2          = (1 << 22),
0154     APINT1          = (1 << 21),
0155     APINT0          = (1 << 20),
0156     MIIPDTINT       = (1 << 19),
0157     MCCINT          = (1 << 17),
0158     MREINT          = (1 << 16),
0159     RINT_SUM        = (1 << 15),
0160     SPNDINT         = (1 << 14),
0161     MPINT           = (1 << 13),
0162     SINT            = (1 << 12),
0163     TINT3           = (1 << 11),
0164     TINT2           = (1 << 10),
0165     TINT1           = (1 << 9),
0166     TINT0           = (1 << 8),
0167     UINT            = (1 << 7),
0168     STINT           = (1 << 4),
0169     RINT0           = (1 << 0),
0170
0171 }INT0_BITS;
0172
0173 typedef enum {
0174
0175     VAL3            = (1 << 31),   /* VAL bit for byte 3 */
0176     VAL2            = (1 << 23),   /* VAL bit for byte 2 */
0177     VAL1            = (1 << 15),   /* VAL bit for byte 1 */
0178     VAL0            = (1 << 7),    /* VAL bit for byte 0 */
0179
0180 }VAL_BITS;
0181
0182 typedef enum {
0183
0184     /* VAL3 */
0185     LCINTEN         = (1 << 27),
0186     APINT5EN        = (1 << 26),
0187     APINT4EN        = (1 << 25),
0188     APINT3EN        = (1 << 24),
0189     /* VAL2 */
0190     APINT2EN        = (1 << 22),
0191     APINT1EN        = (1 << 21),
0192     APINT0EN        = (1 << 20),
0193     MIIPDTINTEN     = (1 << 19),
0194     MCCIINTEN       = (1 << 18),
0195     MCCINTEN        = (1 << 17),
0196     MREINTEN        = (1 << 16),
0197     /* VAL1 */
0198     SPNDINTEN       = (1 << 14),
0199     MPINTEN         = (1 << 13),
0200     TINTEN3         = (1 << 11),
0201     SINTEN          = (1 << 12),
0202     TINTEN2         = (1 << 10),
0203     TINTEN1         = (1 << 9),
0204     TINTEN0         = (1 << 8),
0205     /* VAL0 */
0206     STINTEN         = (1 << 4),
0207     RINTEN0         = (1 << 0),
0208
0209     INTEN0_CLEAR        = 0x1F7F7F1F, /* Command style register */
0210
0211 }INTEN0_BITS;
0212
0213 typedef enum {
0214     /* VAL2 */
0215     RDMD0           = (1 << 16),
0216     /* VAL1 */
0217     TDMD3           = (1 << 11),
0218     TDMD2           = (1 << 10),
0219     TDMD1           = (1 << 9),
0220     TDMD0           = (1 << 8),
0221     /* VAL0 */
0222     UINTCMD         = (1 << 6),
0223     RX_FAST_SPND        = (1 << 5),
0224     TX_FAST_SPND        = (1 << 4),
0225     RX_SPND         = (1 << 3),
0226     TX_SPND         = (1 << 2),
0227     INTREN          = (1 << 1),
0228     RUN         = (1 << 0),
0229
0230     CMD0_CLEAR      = 0x000F0F7F,   /* Command style register */
0231
0232 }CMD0_BITS;
0233
0234 typedef enum {
0235
0236     /* VAL3 */
0237     CONDUIT_MODE        = (1 << 29),
0238     /* VAL2 */
0239     RPA         = (1 << 19),
0240     DRCVPA          = (1 << 18),
0241     DRCVBC          = (1 << 17),
0242     PROM            = (1 << 16),
0243     /* VAL1 */
0244     ASTRP_RCV       = (1 << 13),
0245     RCV_DROP0       = (1 << 12),
0246     EMBA            = (1 << 11),
0247     DXMT2PD         = (1 << 10),
0248     LTINTEN         = (1 << 9),
0249     DXMTFCS         = (1 << 8),
0250     /* VAL0 */
0251     APAD_XMT        = (1 << 6),
0252     DRTY            = (1 << 5),
0253     INLOOP          = (1 << 4),
0254     EXLOOP          = (1 << 3),
0255     REX_RTRY        = (1 << 2),
0256     REX_UFLO        = (1 << 1),
0257     REX_LCOL        = (1 << 0),
0258
0259     CMD2_CLEAR      = 0x3F7F3F7F,   /* Command style register */
0260
0261 }CMD2_BITS;
0262
0263 typedef enum {
0264
0265     /* VAL3 */
0266     ASF_INIT_DONE_ALIAS = (1 << 29),
0267     /* VAL2 */
0268     JUMBO           = (1 << 21),
0269     VSIZE           = (1 << 20),
0270     VLONLY          = (1 << 19),
0271     VL_TAG_DEL      = (1 << 18),
0272     /* VAL1 */
0273     EN_PMGR         = (1 << 14),
0274     INTLEVEL        = (1 << 13),
0275     FORCE_FULL_DUPLEX   = (1 << 12),
0276     FORCE_LINK_STATUS   = (1 << 11),
0277     APEP            = (1 << 10),
0278     MPPLBA          = (1 << 9),
0279     /* VAL0 */
0280     RESET_PHY_PULSE     = (1 << 2),
0281     RESET_PHY       = (1 << 1),
0282     PHY_RST_POL     = (1 << 0),
0283
0284 }CMD3_BITS;
0285
0286
0287 typedef enum {
0288
0289     /* VAL0 */
0290     PMAT_SAVE_MATCH     = (1 << 4),
0291     PMAT_MODE       = (1 << 3),
0292     MPEN_SW         = (1 << 1),
0293     LCMODE_SW       = (1 << 0),
0294
0295     CMD7_CLEAR          = 0x0000001B    /* Command style register */
0296
0297 }CMD7_BITS;
0298
0299
0300 typedef enum {
0301
0302     RESET_PHY_WIDTH     = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
0303     XMTSP_MASK      = (1 << 9) | (1 << 8),  /* 9:8 */
0304     XMTSP_128       = (1 << 9), /* 9 */
0305     XMTSP_64        = (1 << 8),
0306     CACHE_ALIGN     = (1 << 4),
0307     BURST_LIMIT_MASK    = (0xF << 0 ),
0308     CTRL1_DEFAULT       = 0x00010111,
0309
0310 }CTRL1_BITS;
0311
0312 typedef enum {
0313
0314     FMDC_MASK       = (1 << 9)|(1 << 8),    /* 9:8 */
0315     XPHYRST         = (1 << 7),
0316     XPHYANE         = (1 << 6),
0317     XPHYFD          = (1 << 5),
0318     XPHYSP          = (1 << 4) | (1 << 3),  /* 4:3 */
0319     APDW_MASK       = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
0320
0321 }CTRL2_BITS;
0322
0323 /* XMT_RING_LIMIT       0x7C, 32bit register */
0324 typedef enum {
0325
0326     XMT_RING2_LIMIT     = (0xFF << 16), /* 23:16 */
0327     XMT_RING1_LIMIT     = (0xFF << 8),  /* 15:8 */
0328     XMT_RING0_LIMIT     = (0xFF << 0),  /* 7:0 */
0329
0330 }XMT_RING_LIMIT_BITS;
0331
0332 typedef enum {
0333
0334     AP_REG0_EN      = (1 << 15),
0335     AP_REG0_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0336     AP_PHY0_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0337
0338 }AUTOPOLL0_BITS;
0339
0340 /* AUTOPOLL1            0x8A, 16bit register */
0341 typedef enum {
0342
0343     AP_REG1_EN      = (1 << 15),
0344     AP_REG1_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0345     AP_PRE_SUP1     = (1 << 6),
0346     AP_PHY1_DFLT        = (1 << 5),
0347     AP_PHY1_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0348
0349 }AUTOPOLL1_BITS;
0350
0351
0352 typedef enum {
0353
0354     AP_REG2_EN      = (1 << 15),
0355     AP_REG2_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0356     AP_PRE_SUP2     = (1 << 6),
0357     AP_PHY2_DFLT        = (1 << 5),
0358     AP_PHY2_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0359
0360 }AUTOPOLL2_BITS;
0361
0362 typedef enum {
0363
0364     AP_REG3_EN      = (1 << 15),
0365     AP_REG3_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0366     AP_PRE_SUP3     = (1 << 6),
0367     AP_PHY3_DFLT        = (1 << 5),
0368     AP_PHY3_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0369
0370 }AUTOPOLL3_BITS;
0371
0372
0373 typedef enum {
0374
0375     AP_REG4_EN      = (1 << 15),
0376     AP_REG4_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0377     AP_PRE_SUP4     = (1 << 6),
0378     AP_PHY4_DFLT        = (1 << 5),
0379     AP_PHY4_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0380
0381 }AUTOPOLL4_BITS;
0382
0383
0384 typedef enum {
0385
0386     AP_REG5_EN      = (1 << 15),
0387     AP_REG5_ADDR_MASK   = (0xF << 8) |(1 << 12),/* 12:8 */
0388     AP_PRE_SUP5     = (1 << 6),
0389     AP_PHY5_DFLT        = (1 << 5),
0390     AP_PHY5_ADDR_MASK   = (0xF << 0) |(1 << 4),/* 4:0 */
0391
0392 }AUTOPOLL5_BITS;
0393
0394
0395
0396
0397 /* AP_VALUE             0x98, 32bit ragister */
0398 typedef enum {
0399
0400     AP_VAL_ACTIVE       = (1 << 31),
0401     AP_VAL_RD_CMD       = ( 1 << 29),
0402     AP_ADDR         = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
0403     AP_VAL          = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
0404                   (0xF << 12),  /* 15:0 */
0405
0406 }AP_VALUE_BITS;
0407
0408 typedef enum {
0409
0410     DLY_INT_A_R3        = (1 << 31),
0411     DLY_INT_A_R2        = (1 << 30),
0412     DLY_INT_A_R1        = (1 << 29),
0413     DLY_INT_A_R0        = (1 << 28),
0414     DLY_INT_A_T3        = (1 << 27),
0415     DLY_INT_A_T2        = (1 << 26),
0416     DLY_INT_A_T1        = (1 << 25),
0417     DLY_INT_A_T0        = ( 1 << 24),
0418     EVENT_COUNT_A       = (0xF << 16) | (0x1 << 20),/* 20:16 */
0419     MAX_DELAY_TIME_A    = (0xF << 0) | (0xF << 4) | (1 << 8)|
0420                   (1 << 9) | (1 << 10), /* 10:0 */
0421
0422 }DLY_INT_A_BITS;
0423
0424 typedef enum {
0425
0426     DLY_INT_B_R3        = (1 << 31),
0427     DLY_INT_B_R2        = (1 << 30),
0428     DLY_INT_B_R1        = (1 << 29),
0429     DLY_INT_B_R0        = (1 << 28),
0430     DLY_INT_B_T3        = (1 << 27),
0431     DLY_INT_B_T2        = (1 << 26),
0432     DLY_INT_B_T1        = (1 << 25),
0433     DLY_INT_B_T0        = ( 1 << 24),
0434     EVENT_COUNT_B       = (0xF << 16) | (0x1 << 20),/* 20:16 */
0435     MAX_DELAY_TIME_B    = (0xF << 0) | (0xF << 4) | (1 << 8)|
0436                   (1 << 9) | (1 << 10), /* 10:0 */
0437 }DLY_INT_B_BITS;
0438
0439
0440 /* FLOW_CONTROL         0xC8, 32bit register */
0441 typedef enum {
0442
0443     PAUSE_LEN_CHG       = (1 << 30),
0444     FTPE            = (1 << 22),
0445     FRPE            = (1 << 21),
0446     NAPA            = (1 << 20),
0447     NPA         = (1 << 19),
0448     FIXP            = ( 1 << 18),
0449     FCCMD           = ( 1 << 16),
0450     PAUSE_LEN       = (0xF << 0) | (0xF << 4) |( 0xF << 8) |                      (0xF << 12),  /* 15:0 */
0451
0452 }FLOW_CONTROL_BITS;
0453
0454 /* PHY_ ACCESS          0xD0, 32bit register */
0455 typedef enum {
0456
0457     PHY_CMD_ACTIVE      = (1 << 31),
0458     PHY_WR_CMD      = (1 << 30),
0459     PHY_RD_CMD      = (1 << 29),
0460     PHY_RD_ERR      = (1 << 28),
0461     PHY_PRE_SUP     = (1 << 27),
0462     PHY_ADDR        = (1 << 21) | (1 << 22) | (1 << 23)|
0463                     (1 << 24) |(1 << 25),/* 25:21 */
0464     PHY_REG_ADDR        = (1 << 16) | (1 << 17) | (1 << 18)|                            (1 << 19) | (1 << 20),/* 20:16 */
0465     PHY_DATA        = (0xF << 0)|(0xF << 4) |(0xF << 8)|
0466                     (0xF << 12),/* 15:0 */
0467
0468 }PHY_ACCESS_BITS;
0469
0470
0471 /* PMAT0            0x190,   32bit register */
0472 typedef enum {
0473     PMR_ACTIVE      = (1 << 31),
0474     PMR_WR_CMD      = (1 << 30),
0475     PMR_RD_CMD      = (1 << 29),
0476     PMR_BANK        = (1 <<28),
0477     PMR_ADDR        = (0xF << 16)|(1 << 20)|(1 << 21)|
0478                     (1 << 22),/* 22:16 */
0479     PMR_B4          = (0xF << 0) | (0xF << 4),/* 15:0 */
0480 }PMAT0_BITS;
0481
0482
0483 /* PMAT1            0x194,   32bit register */
0484 typedef enum {
0485     PMR_B3          = (0xF << 24) | (0xF <<28),/* 31:24 */
0486     PMR_B2          = (0xF << 16) |(0xF << 20),/* 23:16 */
0487     PMR_B1          = (0xF << 8) | (0xF <<12), /* 15:8 */
0488     PMR_B0          = (0xF << 0)|(0xF << 4),/* 7:0 */
0489 }PMAT1_BITS;
0490
0491 /************************************************************************/
0492 /*                                                                      */
0493 /*                      MIB counter definitions                         */
0494 /*                                                                      */
0495 /************************************************************************/
0496
0497 #define rcv_miss_pkts               0x00
0498 #define rcv_octets              0x01
0499 #define rcv_broadcast_pkts          0x02
0500 #define rcv_multicast_pkts          0x03
0501 #define rcv_undersize_pkts          0x04
0502 #define rcv_oversize_pkts           0x05
0503 #define rcv_fragments               0x06
0504 #define rcv_jabbers             0x07
0505 #define rcv_unicast_pkts            0x08
0506 #define rcv_alignment_errors            0x09
0507 #define rcv_fcs_errors              0x0A
0508 #define rcv_good_octets             0x0B
0509 #define rcv_mac_ctrl                0x0C
0510 #define rcv_flow_ctrl               0x0D
0511 #define rcv_pkts_64_octets          0x0E
0512 #define rcv_pkts_65to127_octets         0x0F
0513 #define rcv_pkts_128to255_octets        0x10
0514 #define rcv_pkts_256to511_octets        0x11
0515 #define rcv_pkts_512to1023_octets       0x12
0516 #define rcv_pkts_1024to1518_octets      0x13
0517 #define rcv_unsupported_opcode          0x14
0518 #define rcv_symbol_errors           0x15
0519 #define rcv_drop_pkts_ring1         0x16
0520 #define rcv_drop_pkts_ring2         0x17
0521 #define rcv_drop_pkts_ring3         0x18
0522 #define rcv_drop_pkts_ring4         0x19
0523 #define rcv_jumbo_pkts              0x1A
0524
0525 #define xmt_underrun_pkts           0x20
0526 #define xmt_octets              0x21
0527 #define xmt_packets             0x22
0528 #define xmt_broadcast_pkts          0x23
0529 #define xmt_multicast_pkts          0x24
0530 #define xmt_collisions              0x25
0531 #define xmt_unicast_pkts            0x26
0532 #define xmt_one_collision           0x27
0533 #define xmt_multiple_collision          0x28
0534 #define xmt_deferred_transmit           0x29
0535 #define xmt_late_collision          0x2A
0536 #define xmt_excessive_defer         0x2B
0537 #define xmt_loss_carrier            0x2C
0538 #define xmt_excessive_collision         0x2D
0539 #define xmt_back_pressure           0x2E
0540 #define xmt_flow_ctrl               0x2F
0541 #define xmt_pkts_64_octets          0x30
0542 #define xmt_pkts_65to127_octets         0x31
0543 #define xmt_pkts_128to255_octets        0x32
0544 #define xmt_pkts_256to511_octets        0x33
0545 #define xmt_pkts_512to1023_octets       0x34
0546 #define xmt_pkts_1024to1518_octet       0x35
0547 #define xmt_oversize_pkts           0x36
0548 #define xmt_jumbo_pkts              0x37
0549
0550
0551 /* Driver definitions */
0552
0553 #define  PCI_VENDOR_ID_AMD      0x1022
0554 #define  PCI_DEVICE_ID_AMD8111E_7462    0x7462
0555
0556 #define MAX_UNITS           8 /* Maximum number of devices possible */
0557
0558 #define NUM_TX_BUFFERS          32 /* Number of transmit buffers */
0559 #define NUM_RX_BUFFERS          32 /* Number of receive buffers */
0560
0561 #define TX_BUFF_MOD_MASK            31 /* (NUM_TX_BUFFERS -1) */
0562 #define RX_BUFF_MOD_MASK            31 /* (NUM_RX_BUFFERS -1) */
0563
0564 #define NUM_TX_RING_DR          32
0565 #define NUM_RX_RING_DR          32
0566
0567 #define TX_RING_DR_MOD_MASK             31 /* (NUM_TX_RING_DR -1) */
0568 #define RX_RING_DR_MOD_MASK             31 /* (NUM_RX_RING_DR -1) */
0569
0570 #define MAX_FILTER_SIZE         64 /* Maximum multicast address */
0571 #define AMD8111E_MIN_MTU        60
0572 #define AMD8111E_MAX_MTU        9000
0573
0574 #define PKT_BUFF_SZ         1536
0575 #define MIN_PKT_LEN         60
0576
0577 #define  AMD8111E_TX_TIMEOUT        (3 * HZ)/* 3 sec */
0578 #define SOFT_TIMER_FREQ         0xBEBC  /* 0.5 sec */
0579 #define DELAY_TIMER_CONV        50    /* msec to 10 usec conversion.
0580                          Only 500 usec resolution */
0581 #define OPTION_VLAN_ENABLE      0x0001
0582 #define OPTION_JUMBO_ENABLE     0x0002
0583 #define OPTION_MULTICAST_ENABLE     0x0004
0584 #define OPTION_WOL_ENABLE       0x0008
0585 #define OPTION_WAKE_MAGIC_ENABLE    0x0010
0586 #define OPTION_WAKE_PHY_ENABLE      0x0020
0587 #define OPTION_INTR_COAL_ENABLE     0x0040
0588 #define OPTION_DYN_IPG_ENABLE           0x0080
0589
0590 #define PHY_REG_ADDR_MASK       0x1f
0591
0592 /* ipg parameters */
0593 #define DEFAULT_IPG         0x60
0594 #define IFS1_DELTA          36
0595 #define IPG_CONVERGE_JIFFIES (HZ/2)
0596 #define IPG_STABLE_TIME 5
0597 #define MIN_IPG 96
0598 #define MAX_IPG 255
0599 #define IPG_STEP    16
0600 #define CSTATE  1
0601 #define SSTATE  2
0602
0603 /* Assume contoller gets data 10 times the maximum processing time */
0604 #define  REPEAT_CNT         10
0605
0606 /* amd8111e descriptor flag definitions */
0607 typedef enum {
0608
0609     OWN_BIT     =   (1 << 15),
0610     ADD_FCS_BIT =   (1 << 13),
0611     LTINT_BIT   =   (1 << 12),
0612     STP_BIT     =   (1 << 9),
0613     ENP_BIT     =   (1 << 8),
0614     KILL_BIT    =   (1 << 6),
0615     TCC_VLAN_INSERT =   (1 << 1),
0616     TCC_VLAN_REPLACE =  (1 << 1) |( 1<< 0),
0617
0618 }TX_FLAG_BITS;
0619
0620 typedef enum {
0621     ERR_BIT     =   (1 << 14),
0622     FRAM_BIT    =   (1 << 13),
0623     OFLO_BIT    =       (1 << 12),
0624     CRC_BIT     =   (1 << 11),
0625     PAM_BIT     =   (1 << 6),
0626     LAFM_BIT    =   (1 << 5),
0627     BAM_BIT     =   (1 << 4),
0628     TT_VLAN_TAGGED  =   (1 << 3) |(1 << 2),/* 0x000 */
0629     TT_PRTY_TAGGED  =   (1 << 3),/* 0x0008 */
0630
0631 }RX_FLAG_BITS;
0632
0633 #define RESET_RX_FLAGS      0x0000
0634 #define TT_MASK         0x000c
0635 #define TCC_MASK        0x0003
0636
0637 /* driver ioctl parameters */
0638 #define AMD8111E_REG_DUMP_LEN    13*sizeof(u32)
0639
0640 /* amd8111e descriptor format */
0641
0642 struct amd8111e_tx_dr{
0643
0644     __le16 buff_count; /* Size of the buffer pointed by this descriptor */
0645
0646     __le16 tx_flags;
0647
0648     __le16 tag_ctrl_info;
0649
0650     __le16 tag_ctrl_cmd;
0651
0652     __le32 buff_phy_addr;
0653
0654     __le32 reserved;
0655 };
0656
0657 struct amd8111e_rx_dr{
0658
0659     __le32 reserved;
0660
0661     __le16 msg_count; /* Received message len */
0662
0663     __le16 tag_ctrl_info;
0664
0665     __le16 buff_count;  /* Len of the buffer pointed by descriptor. */
0666
0667     __le16 rx_flags;
0668
0669     __le32 buff_phy_addr;
0670
0671 };
0672 struct amd8111e_link_config{
0673
0674 #define SPEED_INVALID       0xffff
0675 #define DUPLEX_INVALID      0xff
0676 #define AUTONEG_INVALID     0xff
0677
0678     unsigned long           orig_phy_option;
0679     u16             speed;
0680     u8              duplex;
0681     u8              autoneg;
0682     u8              reserved;  /* 32bit alignment */
0683 };
0684
0685 enum coal_type{
0686
0687     NO_COALESCE,
0688     LOW_COALESCE,
0689     MEDIUM_COALESCE,
0690     HIGH_COALESCE,
0691
0692 };
0693
0694 enum coal_mode{
0695     RX_INTR_COAL,
0696     TX_INTR_COAL,
0697     DISABLE_COAL,
0698     ENABLE_COAL,
0699
0700 };
0701 #define MAX_TIMEOUT 40
0702 #define MAX_EVENT_COUNT 31
0703 struct amd8111e_coalesce_conf{
0704
0705     unsigned int rx_timeout;
0706     unsigned int rx_event_count;
0707     unsigned long rx_packets;
0708     unsigned long rx_prev_packets;
0709     unsigned long rx_bytes;
0710     unsigned long rx_prev_bytes;
0711     unsigned int rx_coal_type;
0712
0713     unsigned int tx_timeout;
0714     unsigned int tx_event_count;
0715     unsigned long tx_packets;
0716     unsigned long tx_prev_packets;
0717     unsigned long tx_bytes;
0718     unsigned long tx_prev_bytes;
0719     unsigned int tx_coal_type;
0720
0721 };
0722 struct ipg_info{
0723
0724     unsigned int ipg_state;
0725     unsigned int ipg;
0726     unsigned int current_ipg;
0727     unsigned int col_cnt;
0728     unsigned int diff_col_cnt;
0729     unsigned int timer_tick;
0730     unsigned int prev_ipg;
0731     struct timer_list ipg_timer;
0732 };
0733
0734 struct amd8111e_priv{
0735
0736     struct amd8111e_tx_dr*  tx_ring;
0737     struct amd8111e_rx_dr* rx_ring;
0738     dma_addr_t tx_ring_dma_addr;    /* tx descriptor ring base address */
0739     dma_addr_t rx_ring_dma_addr;    /* rx descriptor ring base address */
0740     const char *name;
0741     struct pci_dev *pci_dev;    /* Ptr to the associated pci_dev */
0742     struct net_device* amd8111e_net_dev;    /* ptr to associated net_device */
0743     /* Transmit and receive skbs */
0744     struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
0745     struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
0746     /* Transmit and receive dma mapped addr */
0747     dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
0748     dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
0749     /* Reg memory mapped address */
0750     void __iomem *mmio;
0751
0752     struct napi_struct napi;
0753
0754     spinlock_t lock;    /* Guard lock */
0755     unsigned long rx_idx, tx_idx;   /* The next free ring entry */
0756     unsigned long tx_complete_idx;
0757     unsigned long tx_ring_complete_idx;
0758     unsigned long tx_ring_idx;
0759     unsigned int rx_buff_len;   /* Buffer length of rx buffers */
0760     int options;        /* Options enabled/disabled for the device */
0761
0762     unsigned long ext_phy_option;
0763     int ext_phy_addr;
0764     u32 ext_phy_id;
0765
0766     struct amd8111e_link_config link_config;
0767     int pm_cap;
0768
0769     struct net_device *next;
0770     int mii;
0771     struct mii_if_info mii_if;
0772     char opened;
0773     unsigned int drv_rx_errors;
0774     struct amd8111e_coalesce_conf coal_conf;
0775
0776     struct ipg_info  ipg_data;
0777
0778 };
0779
0780 /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
0781 BUG? */
0782 #define  amd8111e_writeq(_UlData,_memMap)   \
0783         writel(*(u32*)(&_UlData), _memMap); \
0784         writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
0785
0786 /* maps the external speed options to internal value */
0787 typedef enum {
0788     SPEED_AUTONEG,
0789     SPEED10_HALF,
0790     SPEED10_FULL,
0791     SPEED100_HALF,
0792     SPEED100_FULL,
0793 }EXT_PHY_OPTION;
0794
0795 static int card_idx;
0796 static int speed_duplex[MAX_UNITS] = { 0, };
0797 static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
0798 static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };
0799 static unsigned int chip_version;
0800
0801 #endif /* _AMD8111E_H */
0802