ethernet/amd/a2065.h

0001 /*
0002  * Amiga Linux/68k A2065 Ethernet Driver
0003  *
0004  * (C) Copyright 1995 by Geert Uytterhoeven <geert@linux-m68k.org>
0005  *
0006  * ---------------------------------------------------------------------------
0007  *
0008  * This program is based on
0009  *
0010  *  ariadne.?:  Amiga Linux/68k Ariadne Ethernet Driver
0011  *          (C) Copyright 1995 by Geert Uytterhoeven,
0012  *          Peter De Schrijver
0013  *
0014  *  lance.c:    An AMD LANCE ethernet driver for linux.
0015  *          Written 1993-94 by Donald Becker.
0016  *
0017  *  Am79C960:   PCnet(tm)-ISA Single-Chip Ethernet Controller
0018  *          Advanced Micro Devices
0019  *          Publication #16907, Rev. B, Amendment/0, May 1994
0020  *
0021  * ---------------------------------------------------------------------------
0022  *
0023  * This file is subject to the terms and conditions of the GNU General Public
0024  * License.  See the file COPYING in the main directory of the Linux
0025  * distribution for more details.
0026  *
0027  * ---------------------------------------------------------------------------
0028  *
0029  * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
0030  *
0031  *  - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
0032  *    both 10BASE-2 (thin coax) and AUI (DB-15) connectors
0033  */
0034
0035
0036 /*
0037  *      Am7990 Local Area Network Controller for Ethernet (LANCE)
0038  */
0039
0040 struct lance_regs {
0041     unsigned short rdp;     /* Register Data Port */
0042     unsigned short rap;     /* Register Address Port */
0043 };
0044
0045
0046 /*
0047  *      Am7990 Control and Status Registers
0048  */
0049
0050 #define LE_CSR0     0x0000      /* LANCE Controller Status */
0051 #define LE_CSR1     0x0001      /* IADR[15:0] */
0052 #define LE_CSR2     0x0002      /* IADR[23:16] */
0053 #define LE_CSR3     0x0003      /* Misc */
0054
0055
0056 /*
0057  *      Bit definitions for CSR0 (LANCE Controller Status)
0058  */
0059
0060 #define LE_C0_ERR   0x8000      /* Error */
0061 #define LE_C0_BABL  0x4000      /* Babble: Transmitted too many bits */
0062 #define LE_C0_CERR  0x2000      /* No Heartbeat (10BASE-T) */
0063 #define LE_C0_MISS  0x1000      /* Missed Frame */
0064 #define LE_C0_MERR  0x0800      /* Memory Error */
0065 #define LE_C0_RINT  0x0400      /* Receive Interrupt */
0066 #define LE_C0_TINT  0x0200      /* Transmit Interrupt */
0067 #define LE_C0_IDON  0x0100      /* Initialization Done */
0068 #define LE_C0_INTR  0x0080      /* Interrupt Flag */
0069 #define LE_C0_INEA  0x0040      /* Interrupt Enable */
0070 #define LE_C0_RXON  0x0020      /* Receive On */
0071 #define LE_C0_TXON  0x0010      /* Transmit On */
0072 #define LE_C0_TDMD  0x0008      /* Transmit Demand */
0073 #define LE_C0_STOP  0x0004      /* Stop */
0074 #define LE_C0_STRT  0x0002      /* Start */
0075 #define LE_C0_INIT  0x0001      /* Initialize */
0076
0077
0078 /*
0079  *      Bit definitions for CSR3
0080  */
0081
0082 #define LE_C3_BSWP  0x0004      /* Byte Swap
0083                        (on for big endian byte order) */
0084 #define LE_C3_ACON  0x0002      /* ALE Control
0085                        (on for active low ALE) */
0086 #define LE_C3_BCON  0x0001      /* Byte Control */
0087
0088
0089 /*
0090  *      Mode Flags
0091  */
0092
0093 #define LE_MO_PROM  0x8000      /* Promiscuous Mode */
0094 #define LE_MO_INTL  0x0040      /* Internal Loopback */
0095 #define LE_MO_DRTY  0x0020      /* Disable Retry */
0096 #define LE_MO_FCOLL 0x0010      /* Force Collision */
0097 #define LE_MO_DXMTFCS   0x0008      /* Disable Transmit CRC */
0098 #define LE_MO_LOOP  0x0004      /* Loopback Enable */
0099 #define LE_MO_DTX   0x0002      /* Disable Transmitter */
0100 #define LE_MO_DRX   0x0001      /* Disable Receiver */
0101
0102
0103 struct lance_rx_desc {
0104     unsigned short rmd0;        /* low address of packet */
0105     unsigned char  rmd1_bits;   /* descriptor bits */
0106     unsigned char  rmd1_hadr;   /* high address of packet */
0107     short    length;            /* This length is 2s complement (negative)!
0108                      * Buffer length
0109                      */
0110     unsigned short mblength;    /* Aactual number of bytes received */
0111 };
0112
0113 struct lance_tx_desc {
0114     unsigned short tmd0;        /* low address of packet */
0115     unsigned char  tmd1_bits;   /* descriptor bits */
0116     unsigned char  tmd1_hadr;   /* high address of packet */
0117     short    length;            /* Length is 2s complement (negative)! */
0118     unsigned short misc;
0119 };
0120
0121
0122 /*
0123  *      Receive Flags
0124  */
0125
0126 #define LE_R1_OWN   0x80        /* LANCE owns the descriptor */
0127 #define LE_R1_ERR   0x40        /* Error */
0128 #define LE_R1_FRA   0x20        /* Framing Error */
0129 #define LE_R1_OFL   0x10        /* Overflow Error */
0130 #define LE_R1_CRC   0x08        /* CRC Error */
0131 #define LE_R1_BUF   0x04        /* Buffer Error */
0132 #define LE_R1_SOP   0x02        /* Start of Packet */
0133 #define LE_R1_EOP   0x01        /* End of Packet */
0134 #define LE_R1_POK       0x03        /* Packet is complete: SOP + EOP */
0135
0136
0137 /*
0138  *      Transmit Flags
0139  */
0140
0141 #define LE_T1_OWN   0x80        /* LANCE owns the descriptor */
0142 #define LE_T1_ERR   0x40        /* Error */
0143 #define LE_T1_RES   0x20        /* Reserved,
0144                        LANCE writes this with a zero */
0145 #define LE_T1_EMORE 0x10        /* More than one retry needed */
0146 #define LE_T1_EONE  0x08        /* One retry needed */
0147 #define LE_T1_EDEF  0x04        /* Deferred */
0148 #define LE_T1_SOP   0x02        /* Start of Packet */
0149 #define LE_T1_EOP   0x01        /* End of Packet */
0150 #define LE_T1_POK   0x03        /* Packet is complete: SOP + EOP */
0151
0152
0153 /*
0154  *      Error Flags
0155  */
0156
0157 #define LE_T3_BUF   0x8000      /* Buffer Error */
0158 #define LE_T3_UFL   0x4000      /* Underflow Error */
0159 #define LE_T3_LCOL  0x1000      /* Late Collision */
0160 #define LE_T3_CLOS  0x0800      /* Loss of Carrier */
0161 #define LE_T3_RTY   0x0400      /* Retry Error */
0162 #define LE_T3_TDR   0x03ff      /* Time Domain Reflectometry */
0163
0164
0165 /*
0166  *      A2065 Expansion Board Structure
0167  */
0168
0169 #define A2065_LANCE     0x4000
0170
0171 #define A2065_RAM       0x8000
0172 #define A2065_RAM_SIZE      0x8000
0173