ethernet/amd/7990.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * 7990.h -- LANCE ethernet IC generic routines.
0004  * This is an attempt to separate out the bits of various ethernet
0005  * drivers that are common because they all use the AMD 7990 LANCE
0006  * (Local Area Network Controller for Ethernet) chip.
0007  *
0008  * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
0009  *
0010  * Most of this stuff was obtained by looking at other LANCE drivers,
0011  * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
0012  */
0013
0014 #ifndef _7990_H
0015 #define _7990_H
0016
0017 /* The lance only has two register locations. We communicate mostly via memory. */
0018 #define LANCE_RDP   0   /* Register Data Port */
0019 #define LANCE_RAP   2   /* Register Address Port */
0020
0021 /* Transmit/receive ring definitions.
0022  * We allow the specific drivers to override these defaults if they want to.
0023  * NB: according to lance.c, increasing the number of buffers is a waste
0024  * of space and reduces the chance that an upper layer will be able to
0025  * reorder queued Tx packets based on priority. [Clearly there is a minimum
0026  * limit too: too small and we drop rx packets and can't tx at full speed.]
0027  * 4+4 seems to be the usual setting; the atarilance driver uses 3 and 5.
0028  */
0029
0030 /* Blast! This won't work. The problem is that we can't specify a default
0031  * setting because that would cause the lance_init_block struct to be
0032  * too long (and overflow the RAM on shared-memory cards like the HP LANCE.
0033  */
0034 #ifndef LANCE_LOG_TX_BUFFERS
0035 #define LANCE_LOG_TX_BUFFERS 1
0036 #define LANCE_LOG_RX_BUFFERS 3
0037 #endif
0038
0039 #define TX_RING_SIZE        (1 << LANCE_LOG_TX_BUFFERS)
0040 #define RX_RING_SIZE        (1 << LANCE_LOG_RX_BUFFERS)
0041 #define TX_RING_MOD_MASK    (TX_RING_SIZE - 1)
0042 #define RX_RING_MOD_MASK    (RX_RING_SIZE - 1)
0043 #define TX_RING_LEN_BITS    ((LANCE_LOG_TX_BUFFERS) << 29)
0044 #define RX_RING_LEN_BITS    ((LANCE_LOG_RX_BUFFERS) << 29)
0045 #define PKT_BUFF_SIZE       (1544)
0046 #define RX_BUFF_SIZE        PKT_BUFF_SIZE
0047 #define TX_BUFF_SIZE        PKT_BUFF_SIZE
0048
0049 /* Each receive buffer is described by a receive message descriptor (RMD) */
0050 struct lance_rx_desc {
0051     volatile unsigned short rmd0;       /* low address of packet */
0052     volatile unsigned char  rmd1_bits;  /* descriptor bits */
0053     volatile unsigned char  rmd1_hadr;  /* high address of packet */
0054     volatile short    length;       /* This length is 2s complement (negative)!
0055                          * Buffer length */
0056     volatile unsigned short mblength;   /* Actual number of bytes received */
0057 };
0058
0059 /* Ditto for TMD: */
0060 struct lance_tx_desc {
0061     volatile unsigned short tmd0;       /* low address of packet */
0062     volatile unsigned char  tmd1_bits;  /* descriptor bits */
0063     volatile unsigned char  tmd1_hadr;  /* high address of packet */
0064     volatile short    length;       /* Length is 2s complement (negative)! */
0065     volatile unsigned short misc;
0066 };
0067
0068 /* There are three memory structures accessed by the LANCE:
0069  * the initialization block, the receive and transmit descriptor rings,
0070  * and the data buffers themselves. In fact we might as well put the
0071  * init block,the Tx and Rx rings and the buffers together in memory:
0072  */
0073 struct lance_init_block {
0074     volatile unsigned short mode;       /* Pre-set mode (reg. 15) */
0075     volatile unsigned char phys_addr[6];    /* Physical ethernet address */
0076     volatile unsigned filter[2];        /* Multicast filter (64 bits) */
0077
0078     /* Receive and transmit ring base, along with extra bits. */
0079     volatile unsigned short rx_ptr;     /* receive descriptor addr */
0080     volatile unsigned short rx_len;     /* receive len and high addr */
0081     volatile unsigned short tx_ptr;     /* transmit descriptor addr */
0082     volatile unsigned short tx_len;     /* transmit len and high addr */
0083
0084     /* The Tx and Rx ring entries must be aligned on 8-byte boundaries.
0085      * This will be true if this whole struct is 8-byte aligned.
0086      */
0087     volatile struct lance_tx_desc btx_ring[TX_RING_SIZE];
0088     volatile struct lance_rx_desc brx_ring[RX_RING_SIZE];
0089
0090     volatile char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
0091     volatile char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
0092     /* we use this just to make the struct big enough that we can move its startaddr
0093      * in order to force alignment to an eight byte boundary.
0094      */
0095 };
0096
0097 /* This is where we keep all the stuff the driver needs to know about.
0098  * I'm definitely unhappy about the mechanism for allowing specific
0099  * drivers to add things...
0100  */
0101 struct lance_private {
0102     const char *name;
0103     unsigned long base;
0104     volatile struct lance_init_block *init_block; /* CPU address of RAM */
0105     volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */
0106
0107     int rx_new, tx_new;
0108     int rx_old, tx_old;
0109
0110     int lance_log_rx_bufs, lance_log_tx_bufs;
0111     int rx_ring_mod_mask, tx_ring_mod_mask;
0112
0113     int tpe;            /* TPE is selected */
0114     int auto_select;        /* cable-selection is by carrier */
0115     unsigned short busmaster_regval;
0116
0117     unsigned int irq;       /* IRQ to register */
0118
0119     /* This is because the HP LANCE is disgusting and you have to check
0120      * a DIO-specific register every time you read/write the LANCE regs :-<
0121      * [could we get away with making these some sort of macro?]
0122      */
0123     void (*writerap)(void *, unsigned short);
0124     void (*writerdp)(void *, unsigned short);
0125     unsigned short (*readrdp)(void *);
0126     spinlock_t devlock;
0127     char tx_full;
0128 };
0129
0130 /*
0131  *      Am7990 Control and Status Registers
0132  */
0133 #define LE_CSR0     0x0000  /* LANCE Controller Status */
0134 #define LE_CSR1     0x0001  /* IADR[15:0] (bit0==0 ie word aligned) */
0135 #define LE_CSR2     0x0002  /* IADR[23:16] (high bits reserved) */
0136 #define LE_CSR3     0x0003  /* Misc */
0137
0138 /*
0139  *      Bit definitions for CSR0 (LANCE Controller Status)
0140  */
0141 #define LE_C0_ERR   0x8000  /* Error = BABL | CERR | MISS | MERR */
0142 #define LE_C0_BABL  0x4000  /* Babble: Transmitted too many bits */
0143 #define LE_C0_CERR  0x2000  /* No Heartbeat (10BASE-T) */
0144 #define LE_C0_MISS  0x1000  /* Missed Frame (no rx buffer to put it in) */
0145 #define LE_C0_MERR  0x0800  /* Memory Error */
0146 #define LE_C0_RINT  0x0400  /* Receive Interrupt */
0147 #define LE_C0_TINT  0x0200  /* Transmit Interrupt */
0148 #define LE_C0_IDON  0x0100  /* Initialization Done */
0149 #define LE_C0_INTR  0x0080  /* Interrupt Flag
0150                    = BABL | MISS | MERR | RINT | TINT | IDON */
0151 #define LE_C0_INEA  0x0040  /* Interrupt Enable */
0152 #define LE_C0_RXON  0x0020  /* Receive On */
0153 #define LE_C0_TXON  0x0010  /* Transmit On */
0154 #define LE_C0_TDMD  0x0008  /* Transmit Demand */
0155 #define LE_C0_STOP  0x0004  /* Stop */
0156 #define LE_C0_STRT  0x0002  /* Start */
0157 #define LE_C0_INIT  0x0001  /* Initialize */
0158
0159
0160 /*
0161  *      Bit definitions for CSR3
0162  */
0163 #define LE_C3_BSWP  0x0004  /* Byte Swap (on for big endian byte order) */
0164 #define LE_C3_ACON  0x0002  /* ALE Control (on for active low ALE) */
0165 #define LE_C3_BCON  0x0001  /* Byte Control */
0166
0167
0168 /*
0169  *      Mode Flags
0170  */
0171 #define LE_MO_PROM  0x8000  /* Promiscuous Mode */
0172 /* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
0173  * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips
0174  */
0175 #define LE_MO_DRCVBC    0x4000  /* disable receive broadcast */
0176 #define LE_MO_DRCVPA    0x2000  /* disable physical address detection */
0177 #define LE_MO_DLNKTST   0x1000  /* disable link status */
0178 #define LE_MO_DAPC  0x0800  /* disable automatic polarity correction */
0179 #define LE_MO_MENDECL   0x0400  /* MENDEC loopback mode */
0180 #define LE_MO_LRTTSEL   0x0200  /* lower RX threshold / TX mode selection */
0181 #define LE_MO_PSEL1 0x0100  /* port selection bit1 */
0182 #define LE_MO_PSEL0 0x0080  /* port selection bit0 */
0183 /* and this one is from the C-LANCE data sheet... */
0184 #define LE_MO_EMBA  0x0080  /* Enable Modified Backoff Algorithm
0185                    (C-LANCE, not original LANCE) */
0186 #define LE_MO_INTL  0x0040  /* Internal Loopback */
0187 #define LE_MO_DRTY  0x0020  /* Disable Retry */
0188 #define LE_MO_FCOLL 0x0010  /* Force Collision */
0189 #define LE_MO_DXMTFCS   0x0008  /* Disable Transmit CRC */
0190 #define LE_MO_LOOP  0x0004  /* Loopback Enable */
0191 #define LE_MO_DTX   0x0002  /* Disable Transmitter */
0192 #define LE_MO_DRX   0x0001  /* Disable Receiver */
0193
0194
0195 /*
0196  *      Receive Flags
0197  */
0198 #define LE_R1_OWN   0x80    /* LANCE owns the descriptor */
0199 #define LE_R1_ERR   0x40    /* Error */
0200 #define LE_R1_FRA   0x20    /* Framing Error */
0201 #define LE_R1_OFL   0x10    /* Overflow Error */
0202 #define LE_R1_CRC   0x08    /* CRC Error */
0203 #define LE_R1_BUF   0x04    /* Buffer Error */
0204 #define LE_R1_SOP   0x02    /* Start of Packet */
0205 #define LE_R1_EOP   0x01    /* End of Packet */
0206 #define LE_R1_POK   0x03    /* Packet is complete: SOP + EOP */
0207
0208
0209 /*
0210  *      Transmit Flags
0211  */
0212 #define LE_T1_OWN   0x80    /* LANCE owns the descriptor */
0213 #define LE_T1_ERR   0x40    /* Error */
0214 #define LE_T1_RES   0x20    /* Reserved, LANCE writes this with a zero */
0215 #define LE_T1_EMORE 0x10    /* More than one retry needed */
0216 #define LE_T1_EONE  0x08    /* One retry needed */
0217 #define LE_T1_EDEF  0x04    /* Deferred */
0218 #define LE_T1_SOP   0x02    /* Start of Packet */
0219 #define LE_T1_EOP   0x01    /* End of Packet */
0220 #define LE_T1_POK   0x03    /* Packet is complete: SOP + EOP */
0221
0222 /*
0223  *      Error Flags
0224  */
0225 #define LE_T3_BUF   0x8000  /* Buffer Error */
0226 #define LE_T3_UFL   0x4000  /* Underflow Error */
0227 #define LE_T3_LCOL  0x1000  /* Late Collision */
0228 #define LE_T3_CLOS  0x0800  /* Loss of Carrier */
0229 #define LE_T3_RTY   0x0400  /* Retry Error */
0230 #define LE_T3_TDR   0x03ff  /* Time Domain Reflectometry */
0231
0232 /* Miscellaneous useful macros */
0233
0234 #define TX_BUFFS_AVAIL ((lp->tx_old <= lp->tx_new) ? \
0235             lp->tx_old + lp->tx_ring_mod_mask - lp->tx_new : \
0236             lp->tx_old - lp->tx_new - 1)
0237
0238 /* The LANCE only uses 24 bit addresses. This does the obvious thing. */
0239 #define LANCE_ADDR(x) ((int)(x) & ~0xff000000)
0240
0241 /* Now the prototypes we export */
0242 int lance_open(struct net_device *dev);
0243 int lance_close(struct net_device *dev);
0244 netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev);
0245 void lance_set_multicast(struct net_device *dev);
0246 void lance_tx_timeout(struct net_device *dev, unsigned int txqueue);
0247 #ifdef CONFIG_NET_POLL_CONTROLLER
0248 void lance_poll(struct net_device *dev);
0249 #endif
0250
0251 #endif /* ndef _7990_H */