amazon/ena/ena_regs_defs.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /*
0003  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
0004  */
0005 #ifndef _ENA_REGS_H_
0006 #define _ENA_REGS_H_
0007
0008 enum ena_regs_reset_reason_types {
0009     ENA_REGS_RESET_NORMAL                       = 0,
0010     ENA_REGS_RESET_KEEP_ALIVE_TO                = 1,
0011     ENA_REGS_RESET_ADMIN_TO                     = 2,
0012     ENA_REGS_RESET_MISS_TX_CMPL                 = 3,
0013     ENA_REGS_RESET_INV_RX_REQ_ID                = 4,
0014     ENA_REGS_RESET_INV_TX_REQ_ID                = 5,
0015     ENA_REGS_RESET_TOO_MANY_RX_DESCS            = 6,
0016     ENA_REGS_RESET_INIT_ERR                     = 7,
0017     ENA_REGS_RESET_DRIVER_INVALID_STATE         = 8,
0018     ENA_REGS_RESET_OS_TRIGGER                   = 9,
0019     ENA_REGS_RESET_OS_NETDEV_WD                 = 10,
0020     ENA_REGS_RESET_SHUTDOWN                     = 11,
0021     ENA_REGS_RESET_USER_TRIGGER                 = 12,
0022     ENA_REGS_RESET_GENERIC                      = 13,
0023     ENA_REGS_RESET_MISS_INTERRUPT               = 14,
0024 };
0025
0026 /* ena_registers offsets */
0027
0028 /* 0 base */
0029 #define ENA_REGS_VERSION_OFF                                0x0
0030 #define ENA_REGS_CONTROLLER_VERSION_OFF                     0x4
0031 #define ENA_REGS_CAPS_OFF                                   0x8
0032 #define ENA_REGS_CAPS_EXT_OFF                               0xc
0033 #define ENA_REGS_AQ_BASE_LO_OFF                             0x10
0034 #define ENA_REGS_AQ_BASE_HI_OFF                             0x14
0035 #define ENA_REGS_AQ_CAPS_OFF                                0x18
0036 #define ENA_REGS_ACQ_BASE_LO_OFF                            0x20
0037 #define ENA_REGS_ACQ_BASE_HI_OFF                            0x24
0038 #define ENA_REGS_ACQ_CAPS_OFF                               0x28
0039 #define ENA_REGS_AQ_DB_OFF                                  0x2c
0040 #define ENA_REGS_ACQ_TAIL_OFF                               0x30
0041 #define ENA_REGS_AENQ_CAPS_OFF                              0x34
0042 #define ENA_REGS_AENQ_BASE_LO_OFF                           0x38
0043 #define ENA_REGS_AENQ_BASE_HI_OFF                           0x3c
0044 #define ENA_REGS_AENQ_HEAD_DB_OFF                           0x40
0045 #define ENA_REGS_AENQ_TAIL_OFF                              0x44
0046 #define ENA_REGS_INTR_MASK_OFF                              0x4c
0047 #define ENA_REGS_DEV_CTL_OFF                                0x54
0048 #define ENA_REGS_DEV_STS_OFF                                0x58
0049 #define ENA_REGS_MMIO_REG_READ_OFF                          0x5c
0050 #define ENA_REGS_MMIO_RESP_LO_OFF                           0x60
0051 #define ENA_REGS_MMIO_RESP_HI_OFF                           0x64
0052 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF                   0x68
0053
0054 /* version register */
0055 #define ENA_REGS_VERSION_MINOR_VERSION_MASK                 0xff
0056 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT                8
0057 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK                 0xff00
0058
0059 /* controller_version register */
0060 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK   0xff
0061 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT     8
0062 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK      0xff00
0063 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT     16
0064 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK      0xff0000
0065 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT           24
0066 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK            0xff000000
0067
0068 /* caps register */
0069 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK        0x1
0070 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT                   1
0071 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                    0x3e
0072 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT                  8
0073 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK                   0xff00
0074 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                    16
0075 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK                     0xf0000
0076
0077 /* aq_caps register */
0078 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK                      0xffff
0079 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT                16
0080 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK                 0xffff0000
0081
0082 /* acq_caps register */
0083 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                    0xffff
0084 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT              16
0085 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK               0xffff0000
0086
0087 /* aenq_caps register */
0088 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK                  0xffff
0089 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT            16
0090 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK             0xffff0000
0091
0092 /* dev_ctl register */
0093 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK                     0x1
0094 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT                   1
0095 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                    0x2
0096 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                    2
0097 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK                     0x4
0098 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                    3
0099 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK                     0x8
0100 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT                 28
0101 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK                  0xf0000000
0102
0103 /* dev_sts register */
0104 #define ENA_REGS_DEV_STS_READY_MASK                         0x1
0105 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT       1
0106 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK        0x2
0107 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT          2
0108 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK           0x4
0109 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT            3
0110 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK             0x8
0111 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT               4
0112 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK                0x10
0113 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT                  5
0114 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK                   0x20
0115 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT  6
0116 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK   0x40
0117 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT     7
0118 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK      0x80
0119
0120 /* mmio_reg_read register */
0121 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK                  0xffff
0122 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT                16
0123 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK                 0xffff0000
0124
0125 /* rss_ind_entry_update register */
0126 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK            0xffff
0127 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT          16
0128 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK           0xffff0000
0129
0130 #endif /* _ENA_REGS_H_ */