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0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /*
0003  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
0004  */
0005 #ifndef _ENA_ETH_IO_H_
0006 #define _ENA_ETH_IO_H_
0007 
0008 enum ena_eth_io_l3_proto_index {
0009     ENA_ETH_IO_L3_PROTO_UNKNOWN                 = 0,
0010     ENA_ETH_IO_L3_PROTO_IPV4                    = 8,
0011     ENA_ETH_IO_L3_PROTO_IPV6                    = 11,
0012     ENA_ETH_IO_L3_PROTO_FCOE                    = 21,
0013     ENA_ETH_IO_L3_PROTO_ROCE                    = 22,
0014 };
0015 
0016 enum ena_eth_io_l4_proto_index {
0017     ENA_ETH_IO_L4_PROTO_UNKNOWN                 = 0,
0018     ENA_ETH_IO_L4_PROTO_TCP                     = 12,
0019     ENA_ETH_IO_L4_PROTO_UDP                     = 13,
0020     ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE          = 23,
0021 };
0022 
0023 struct ena_eth_io_tx_desc {
0024     /* 15:0 : length - Buffer length in bytes, must
0025      *    include any packet trailers that the ENA supposed
0026      *    to update like End-to-End CRC, Authentication GMAC
0027      *    etc. This length must not include the
0028      *    'Push_Buffer' length. This length must not include
0029      *    the 4-byte added in the end for 802.3 Ethernet FCS
0030      * 21:16 : req_id_hi - Request ID[15:10]
0031      * 22 : reserved22 - MBZ
0032      * 23 : meta_desc - MBZ
0033      * 24 : phase
0034      * 25 : reserved1 - MBZ
0035      * 26 : first - Indicates first descriptor in
0036      *    transaction
0037      * 27 : last - Indicates last descriptor in
0038      *    transaction
0039      * 28 : comp_req - Indicates whether completion
0040      *    should be posted, after packet is transmitted.
0041      *    Valid only for first descriptor
0042      * 30:29 : reserved29 - MBZ
0043      * 31 : reserved31 - MBZ
0044      */
0045     u32 len_ctrl;
0046 
0047     /* 3:0 : l3_proto_idx - L3 protocol. This field
0048      *    required when l3_csum_en,l3_csum or tso_en are set.
0049      * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
0050      *    DF flags of the IPv4 header is 0. Otherwise must
0051      *    be set to 1
0052      * 6:5 : reserved5
0053      * 7 : tso_en - Enable TSO, For TCP only.
0054      * 12:8 : l4_proto_idx - L4 protocol. This field need
0055      *    to be set when l4_csum_en or tso_en are set.
0056      * 13 : l3_csum_en - enable IPv4 header checksum.
0057      * 14 : l4_csum_en - enable TCP/UDP checksum.
0058      * 15 : ethernet_fcs_dis - when set, the controller
0059      *    will not append the 802.3 Ethernet Frame Check
0060      *    Sequence to the packet
0061      * 16 : reserved16
0062      * 17 : l4_csum_partial - L4 partial checksum. when
0063      *    set to 0, the ENA calculates the L4 checksum,
0064      *    where the Destination Address required for the
0065      *    TCP/UDP pseudo-header is taken from the actual
0066      *    packet L3 header. when set to 1, the ENA doesn't
0067      *    calculate the sum of the pseudo-header, instead,
0068      *    the checksum field of the L4 is used instead. When
0069      *    TSO enabled, the checksum of the pseudo-header
0070      *    must not include the tcp length field. L4 partial
0071      *    checksum should be used for IPv6 packet that
0072      *    contains Routing Headers.
0073      * 20:18 : reserved18 - MBZ
0074      * 21 : reserved21 - MBZ
0075      * 31:22 : req_id_lo - Request ID[9:0]
0076      */
0077     u32 meta_ctrl;
0078 
0079     u32 buff_addr_lo;
0080 
0081     /* address high and header size
0082      * 15:0 : addr_hi - Buffer Pointer[47:32]
0083      * 23:16 : reserved16_w2
0084      * 31:24 : header_length - Header length. For Low
0085      *    Latency Queues, this fields indicates the number
0086      *    of bytes written to the headers' memory. For
0087      *    normal queues, if packet is TCP or UDP, and longer
0088      *    than max_header_size, then this field should be
0089      *    set to the sum of L4 header offset and L4 header
0090      *    size(without options), otherwise, this field
0091      *    should be set to 0. For both modes, this field
0092      *    must not exceed the max_header_size.
0093      *    max_header_size value is reported by the Max
0094      *    Queues Feature descriptor
0095      */
0096     u32 buff_addr_hi_hdr_sz;
0097 };
0098 
0099 struct ena_eth_io_tx_meta_desc {
0100     /* 9:0 : req_id_lo - Request ID[9:0]
0101      * 11:10 : reserved10 - MBZ
0102      * 12 : reserved12 - MBZ
0103      * 13 : reserved13 - MBZ
0104      * 14 : ext_valid - if set, offset fields in Word2
0105      *    are valid Also MSS High in Word 0 and bits [31:24]
0106      *    in Word 3
0107      * 15 : reserved15
0108      * 19:16 : mss_hi
0109      * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
0110      *    Extended Metadata Descriptor
0111      * 21 : meta_store - Store extended metadata in queue
0112      *    cache
0113      * 22 : reserved22 - MBZ
0114      * 23 : meta_desc - MBO
0115      * 24 : phase
0116      * 25 : reserved25 - MBZ
0117      * 26 : first - Indicates first descriptor in
0118      *    transaction
0119      * 27 : last - Indicates last descriptor in
0120      *    transaction
0121      * 28 : comp_req - Indicates whether completion
0122      *    should be posted, after packet is transmitted.
0123      *    Valid only for first descriptor
0124      * 30:29 : reserved29 - MBZ
0125      * 31 : reserved31 - MBZ
0126      */
0127     u32 len_ctrl;
0128 
0129     /* 5:0 : req_id_hi
0130      * 31:6 : reserved6 - MBZ
0131      */
0132     u32 word1;
0133 
0134     /* 7:0 : l3_hdr_len
0135      * 15:8 : l3_hdr_off
0136      * 21:16 : l4_hdr_len_in_words - counts the L4 header
0137      *    length in words. there is an explicit assumption
0138      *    that L4 header appears right after L3 header and
0139      *    L4 offset is based on l3_hdr_off+l3_hdr_len
0140      * 31:22 : mss_lo
0141      */
0142     u32 word2;
0143 
0144     u32 reserved;
0145 };
0146 
0147 struct ena_eth_io_tx_cdesc {
0148     /* Request ID[15:0] */
0149     u16 req_id;
0150 
0151     u8 status;
0152 
0153     /* flags
0154      * 0 : phase
0155      * 7:1 : reserved1
0156      */
0157     u8 flags;
0158 
0159     u16 sub_qid;
0160 
0161     u16 sq_head_idx;
0162 };
0163 
0164 struct ena_eth_io_rx_desc {
0165     /* In bytes. 0 means 64KB */
0166     u16 length;
0167 
0168     /* MBZ */
0169     u8 reserved2;
0170 
0171     /* 0 : phase
0172      * 1 : reserved1 - MBZ
0173      * 2 : first - Indicates first descriptor in
0174      *    transaction
0175      * 3 : last - Indicates last descriptor in transaction
0176      * 4 : comp_req
0177      * 5 : reserved5 - MBO
0178      * 7:6 : reserved6 - MBZ
0179      */
0180     u8 ctrl;
0181 
0182     u16 req_id;
0183 
0184     /* MBZ */
0185     u16 reserved6;
0186 
0187     u32 buff_addr_lo;
0188 
0189     u16 buff_addr_hi;
0190 
0191     /* MBZ */
0192     u16 reserved16_w3;
0193 };
0194 
0195 /* 4-word format Note: all ethernet parsing information are valid only when
0196  * last=1
0197  */
0198 struct ena_eth_io_rx_cdesc_base {
0199     /* 4:0 : l3_proto_idx
0200      * 6:5 : src_vlan_cnt
0201      * 7 : reserved7 - MBZ
0202      * 12:8 : l4_proto_idx
0203      * 13 : l3_csum_err - when set, either the L3
0204      *    checksum error detected, or, the controller didn't
0205      *    validate the checksum. This bit is valid only when
0206      *    l3_proto_idx indicates IPv4 packet
0207      * 14 : l4_csum_err - when set, either the L4
0208      *    checksum error detected, or, the controller didn't
0209      *    validate the checksum. This bit is valid only when
0210      *    l4_proto_idx indicates TCP/UDP packet, and,
0211      *    ipv4_frag is not set. This bit is valid only when
0212      *    l4_csum_checked below is set.
0213      * 15 : ipv4_frag - Indicates IPv4 fragmented packet
0214      * 16 : l4_csum_checked - L4 checksum was verified
0215      *    (could be OK or error), when cleared the status of
0216      *    checksum is unknown
0217      * 23:17 : reserved17 - MBZ
0218      * 24 : phase
0219      * 25 : l3_csum2 - second checksum engine result
0220      * 26 : first - Indicates first descriptor in
0221      *    transaction
0222      * 27 : last - Indicates last descriptor in
0223      *    transaction
0224      * 29:28 : reserved28
0225      * 30 : buffer - 0: Metadata descriptor. 1: Buffer
0226      *    Descriptor was used
0227      * 31 : reserved31
0228      */
0229     u32 status;
0230 
0231     u16 length;
0232 
0233     u16 req_id;
0234 
0235     /* 32-bit hash result */
0236     u32 hash;
0237 
0238     u16 sub_qid;
0239 
0240     u8 offset;
0241 
0242     u8 reserved;
0243 };
0244 
0245 /* 8-word format */
0246 struct ena_eth_io_rx_cdesc_ext {
0247     struct ena_eth_io_rx_cdesc_base base;
0248 
0249     u32 buff_addr_lo;
0250 
0251     u16 buff_addr_hi;
0252 
0253     u16 reserved16;
0254 
0255     u32 reserved_w6;
0256 
0257     u32 reserved_w7;
0258 };
0259 
0260 struct ena_eth_io_intr_reg {
0261     /* 14:0 : rx_intr_delay
0262      * 29:15 : tx_intr_delay
0263      * 30 : intr_unmask
0264      * 31 : reserved
0265      */
0266     u32 intr_control;
0267 };
0268 
0269 struct ena_eth_io_numa_node_cfg_reg {
0270     /* 7:0 : numa
0271      * 30:8 : reserved
0272      * 31 : enabled
0273      */
0274     u32 numa_cfg;
0275 };
0276 
0277 /* tx_desc */
0278 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK                      GENMASK(15, 0)
0279 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT                  16
0280 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK                   GENMASK(21, 16)
0281 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT                  23
0282 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK                   BIT(23)
0283 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT                      24
0284 #define ENA_ETH_IO_TX_DESC_PHASE_MASK                       BIT(24)
0285 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT                      26
0286 #define ENA_ETH_IO_TX_DESC_FIRST_MASK                       BIT(26)
0287 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT                       27
0288 #define ENA_ETH_IO_TX_DESC_LAST_MASK                        BIT(27)
0289 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT                   28
0290 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK                    BIT(28)
0291 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK                GENMASK(3, 0)
0292 #define ENA_ETH_IO_TX_DESC_DF_SHIFT                         4
0293 #define ENA_ETH_IO_TX_DESC_DF_MASK                          BIT(4)
0294 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT                     7
0295 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK                      BIT(7)
0296 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT               8
0297 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK                GENMASK(12, 8)
0298 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT                 13
0299 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK                  BIT(13)
0300 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT                 14
0301 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK                  BIT(14)
0302 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT           15
0303 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK            BIT(15)
0304 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT            17
0305 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK             BIT(17)
0306 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT                  22
0307 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK                   GENMASK(31, 22)
0308 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK                     GENMASK(15, 0)
0309 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT              24
0310 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK               GENMASK(31, 24)
0311 
0312 /* tx_meta_desc */
0313 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK              GENMASK(9, 0)
0314 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT             14
0315 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK              BIT(14)
0316 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT                16
0317 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK                 GENMASK(19, 16)
0318 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT         20
0319 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK          BIT(20)
0320 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT            21
0321 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK             BIT(21)
0322 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT             23
0323 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK              BIT(23)
0324 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT                 24
0325 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK                  BIT(24)
0326 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT                 26
0327 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK                  BIT(26)
0328 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT                  27
0329 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK                   BIT(27)
0330 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT              28
0331 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK               BIT(28)
0332 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK              GENMASK(5, 0)
0333 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK             GENMASK(7, 0)
0334 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT            8
0335 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK             GENMASK(15, 8)
0336 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT   16
0337 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK    GENMASK(21, 16)
0338 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT                22
0339 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK                 GENMASK(31, 22)
0340 
0341 /* tx_cdesc */
0342 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK                      BIT(0)
0343 
0344 /* rx_desc */
0345 #define ENA_ETH_IO_RX_DESC_PHASE_MASK                       BIT(0)
0346 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT                      2
0347 #define ENA_ETH_IO_RX_DESC_FIRST_MASK                       BIT(2)
0348 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT                       3
0349 #define ENA_ETH_IO_RX_DESC_LAST_MASK                        BIT(3)
0350 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT                   4
0351 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK                    BIT(4)
0352 
0353 /* rx_cdesc_base */
0354 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK          GENMASK(4, 0)
0355 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT         5
0356 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK          GENMASK(6, 5)
0357 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT         8
0358 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK          GENMASK(12, 8)
0359 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT          13
0360 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK           BIT(13)
0361 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT          14
0362 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK           BIT(14)
0363 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT            15
0364 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK             BIT(15)
0365 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT      16
0366 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK       BIT(16)
0367 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT                24
0368 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK                 BIT(24)
0369 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT             25
0370 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK              BIT(25)
0371 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT                26
0372 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK                 BIT(26)
0373 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT                 27
0374 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK                  BIT(27)
0375 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT               30
0376 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK                BIT(30)
0377 
0378 /* intr_reg */
0379 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK              GENMASK(14, 0)
0380 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT             15
0381 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK              GENMASK(29, 15)
0382 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT               30
0383 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK                BIT(30)
0384 
0385 /* numa_node_cfg_reg */
0386 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK              GENMASK(7, 0)
0387 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT          31
0388 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK           BIT(31)
0389 
0390 #endif /* _ENA_ETH_IO_H_ */
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