ethernet/altera/altera_tse.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Altera Triple-Speed Ethernet MAC driver
0003  * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
0004  *
0005  * Contributors:
0006  *   Dalon Westergreen
0007  *   Thomas Chou
0008  *   Ian Abbott
0009  *   Yuriy Kozlov
0010  *   Tobias Klauser
0011  *   Andriy Smolskyy
0012  *   Roman Bulgakov
0013  *   Dmytro Mytarchuk
0014  *   Matthew Gerlach
0015  *
0016  * Original driver contributed by SLS.
0017  * Major updates contributed by GlobalLogic
0018  */
0019
0020 #ifndef __ALTERA_TSE_H__
0021 #define __ALTERA_TSE_H__
0022
0023 #define ALTERA_TSE_RESOURCE_NAME    "altera_tse"
0024
0025 #include <linux/bitops.h>
0026 #include <linux/if_vlan.h>
0027 #include <linux/list.h>
0028 #include <linux/netdevice.h>
0029 #include <linux/phy.h>
0030
0031 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR   10000
0032 #define ALTERA_TSE_MAC_FIFO_WIDTH       4   /* TX/RX FIFO width in
0033                              * bytes
0034                              */
0035 /* Rx FIFO default settings */
0036 #define ALTERA_TSE_RX_SECTION_EMPTY 16
0037 #define ALTERA_TSE_RX_SECTION_FULL  0
0038 #define ALTERA_TSE_RX_ALMOST_EMPTY  8
0039 #define ALTERA_TSE_RX_ALMOST_FULL   8
0040
0041 /* Tx FIFO default settings */
0042 #define ALTERA_TSE_TX_SECTION_EMPTY 16
0043 #define ALTERA_TSE_TX_SECTION_FULL  0
0044 #define ALTERA_TSE_TX_ALMOST_EMPTY  8
0045 #define ALTERA_TSE_TX_ALMOST_FULL   3
0046
0047 /* MAC function configuration default settings */
0048 #define ALTERA_TSE_TX_IPG_LENGTH    12
0049
0050 #define ALTERA_TSE_PAUSE_QUANTA     0xffff
0051
0052 #define GET_BIT_VALUE(v, bit)       (((v) >> (bit)) & 0x1)
0053
0054 /* MAC Command_Config Register Bit Definitions
0055  */
0056 #define MAC_CMDCFG_TX_ENA           BIT(0)
0057 #define MAC_CMDCFG_RX_ENA           BIT(1)
0058 #define MAC_CMDCFG_XON_GEN          BIT(2)
0059 #define MAC_CMDCFG_ETH_SPEED            BIT(3)
0060 #define MAC_CMDCFG_PROMIS_EN            BIT(4)
0061 #define MAC_CMDCFG_PAD_EN           BIT(5)
0062 #define MAC_CMDCFG_CRC_FWD          BIT(6)
0063 #define MAC_CMDCFG_PAUSE_FWD            BIT(7)
0064 #define MAC_CMDCFG_PAUSE_IGNORE         BIT(8)
0065 #define MAC_CMDCFG_TX_ADDR_INS          BIT(9)
0066 #define MAC_CMDCFG_HD_ENA           BIT(10)
0067 #define MAC_CMDCFG_EXCESS_COL           BIT(11)
0068 #define MAC_CMDCFG_LATE_COL         BIT(12)
0069 #define MAC_CMDCFG_SW_RESET         BIT(13)
0070 #define MAC_CMDCFG_MHASH_SEL            BIT(14)
0071 #define MAC_CMDCFG_LOOP_ENA         BIT(15)
0072 #define MAC_CMDCFG_TX_ADDR_SEL(v)       (((v) & 0x7) << 16)
0073 #define MAC_CMDCFG_MAGIC_ENA            BIT(19)
0074 #define MAC_CMDCFG_SLEEP            BIT(20)
0075 #define MAC_CMDCFG_WAKEUP           BIT(21)
0076 #define MAC_CMDCFG_XOFF_GEN         BIT(22)
0077 #define MAC_CMDCFG_CNTL_FRM_ENA         BIT(23)
0078 #define MAC_CMDCFG_NO_LGTH_CHECK        BIT(24)
0079 #define MAC_CMDCFG_ENA_10           BIT(25)
0080 #define MAC_CMDCFG_RX_ERR_DISC          BIT(26)
0081 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT     BIT(27)
0082 #define MAC_CMDCFG_CNT_RESET            BIT(31)
0083
0084 #define MAC_CMDCFG_TX_ENA_GET(v)        GET_BIT_VALUE(v, 0)
0085 #define MAC_CMDCFG_RX_ENA_GET(v)        GET_BIT_VALUE(v, 1)
0086 #define MAC_CMDCFG_XON_GEN_GET(v)       GET_BIT_VALUE(v, 2)
0087 #define MAC_CMDCFG_ETH_SPEED_GET(v)     GET_BIT_VALUE(v, 3)
0088 #define MAC_CMDCFG_PROMIS_EN_GET(v)     GET_BIT_VALUE(v, 4)
0089 #define MAC_CMDCFG_PAD_EN_GET(v)        GET_BIT_VALUE(v, 5)
0090 #define MAC_CMDCFG_CRC_FWD_GET(v)       GET_BIT_VALUE(v, 6)
0091 #define MAC_CMDCFG_PAUSE_FWD_GET(v)     GET_BIT_VALUE(v, 7)
0092 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v)      GET_BIT_VALUE(v, 8)
0093 #define MAC_CMDCFG_TX_ADDR_INS_GET(v)       GET_BIT_VALUE(v, 9)
0094 #define MAC_CMDCFG_HD_ENA_GET(v)        GET_BIT_VALUE(v, 10)
0095 #define MAC_CMDCFG_EXCESS_COL_GET(v)        GET_BIT_VALUE(v, 11)
0096 #define MAC_CMDCFG_LATE_COL_GET(v)      GET_BIT_VALUE(v, 12)
0097 #define MAC_CMDCFG_SW_RESET_GET(v)      GET_BIT_VALUE(v, 13)
0098 #define MAC_CMDCFG_MHASH_SEL_GET(v)     GET_BIT_VALUE(v, 14)
0099 #define MAC_CMDCFG_LOOP_ENA_GET(v)      GET_BIT_VALUE(v, 15)
0100 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v)       (((v) >> 16) & 0x7)
0101 #define MAC_CMDCFG_MAGIC_ENA_GET(v)     GET_BIT_VALUE(v, 19)
0102 #define MAC_CMDCFG_SLEEP_GET(v)         GET_BIT_VALUE(v, 20)
0103 #define MAC_CMDCFG_WAKEUP_GET(v)        GET_BIT_VALUE(v, 21)
0104 #define MAC_CMDCFG_XOFF_GEN_GET(v)      GET_BIT_VALUE(v, 22)
0105 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v)      GET_BIT_VALUE(v, 23)
0106 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v)     GET_BIT_VALUE(v, 24)
0107 #define MAC_CMDCFG_ENA_10_GET(v)        GET_BIT_VALUE(v, 25)
0108 #define MAC_CMDCFG_RX_ERR_DISC_GET(v)       GET_BIT_VALUE(v, 26)
0109 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v)  GET_BIT_VALUE(v, 27)
0110 #define MAC_CMDCFG_CNT_RESET_GET(v)     GET_BIT_VALUE(v, 31)
0111
0112 /* SGMII PCS register addresses
0113  */
0114 #define SGMII_PCS_SCRATCH   0x10
0115 #define SGMII_PCS_REV       0x11
0116 #define SGMII_PCS_LINK_TIMER_0  0x12
0117 #define SGMII_PCS_LINK_TIMER_1  0x13
0118 #define SGMII_PCS_IF_MODE   0x14
0119 #define SGMII_PCS_DIS_READ_TO   0x15
0120 #define SGMII_PCS_READ_TO   0x16
0121 #define SGMII_PCS_SW_RESET_TIMEOUT 100 /* usecs */
0122
0123 /* MDIO registers within MAC register Space
0124  */
0125 struct altera_tse_mdio {
0126     u32 control;    /* PHY device operation control register */
0127     u32 status; /* PHY device operation status register */
0128     u32 phy_id1;    /* Bits 31:16 of PHY identifier */
0129     u32 phy_id2;    /* Bits 15:0 of PHY identifier */
0130     u32 auto_negotiation_advertisement; /* Auto-negotiation
0131                              * advertisement
0132                              * register
0133                              */
0134     u32 remote_partner_base_page_ability;
0135
0136     u32 reg6;
0137     u32 reg7;
0138     u32 reg8;
0139     u32 reg9;
0140     u32 rega;
0141     u32 regb;
0142     u32 regc;
0143     u32 regd;
0144     u32 rege;
0145     u32 regf;
0146     u32 reg10;
0147     u32 reg11;
0148     u32 reg12;
0149     u32 reg13;
0150     u32 reg14;
0151     u32 reg15;
0152     u32 reg16;
0153     u32 reg17;
0154     u32 reg18;
0155     u32 reg19;
0156     u32 reg1a;
0157     u32 reg1b;
0158     u32 reg1c;
0159     u32 reg1d;
0160     u32 reg1e;
0161     u32 reg1f;
0162 };
0163
0164 /* MAC register Space. Note that some of these registers may or may not be
0165  * present depending upon options chosen by the user when the core was
0166  * configured and built. Please consult the Altera Triple Speed Ethernet User
0167  * Guide for details.
0168  */
0169 struct altera_tse_mac {
0170     /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
0171      * specific revision
0172      */
0173     u32 megacore_revision;
0174     /* Provides a memory location for user applications to test the device
0175      * memory operation.
0176      */
0177     u32 scratch_pad;
0178     /* The host processor uses this register to control and configure the
0179      * MAC block
0180      */
0181     u32 command_config;
0182     /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
0183      * MAC address
0184      */
0185     u32 mac_addr_0;
0186     /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
0187      * MAC address
0188      */
0189     u32 mac_addr_1;
0190     /* 14-bit maximum frame length. The MAC receive logic */
0191     u32 frm_length;
0192     /* The pause quanta is used in each pause frame sent to a remote
0193      * Ethernet device, in increments of 512 Ethernet bit times
0194      */
0195     u32 pause_quanta;
0196     /* 12-bit receive FIFO section-empty threshold */
0197     u32 rx_section_empty;
0198     /* 12-bit receive FIFO section-full threshold */
0199     u32 rx_section_full;
0200     /* 12-bit transmit FIFO section-empty threshold */
0201     u32 tx_section_empty;
0202     /* 12-bit transmit FIFO section-full threshold */
0203     u32 tx_section_full;
0204     /* 12-bit receive FIFO almost-empty threshold */
0205     u32 rx_almost_empty;
0206     /* 12-bit receive FIFO almost-full threshold */
0207     u32 rx_almost_full;
0208     /* 12-bit transmit FIFO almost-empty threshold */
0209     u32 tx_almost_empty;
0210     /* 12-bit transmit FIFO almost-full threshold */
0211     u32 tx_almost_full;
0212     /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
0213     u32 mdio_phy0_addr;
0214     /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
0215     u32 mdio_phy1_addr;
0216
0217     /* Bit[15:0]—16-bit holdoff quanta */
0218     u32 holdoff_quant;
0219
0220     /* only if 100/1000 BaseX PCS, reserved otherwise */
0221     u32 reserved1[5];
0222
0223     /* Minimum IPG between consecutive transmit frame in terms of bytes */
0224     u32 tx_ipg_length;
0225
0226     /* IEEE 802.3 oEntity Managed Object Support */
0227
0228     /* The MAC addresses */
0229     u32 mac_id_1;
0230     u32 mac_id_2;
0231
0232     /* Number of frames transmitted without error including pause frames */
0233     u32 frames_transmitted_ok;
0234     /* Number of frames received without error including pause frames */
0235     u32 frames_received_ok;
0236     /* Number of frames received with a CRC error */
0237     u32 frames_check_sequence_errors;
0238     /* Frame received with an alignment error */
0239     u32 alignment_errors;
0240     /* Sum of payload and padding octets of frames transmitted without
0241      * error
0242      */
0243     u32 octets_transmitted_ok;
0244     /* Sum of payload and padding octets of frames received without error */
0245     u32 octets_received_ok;
0246
0247     /* IEEE 802.3 oPausedEntity Managed Object Support */
0248
0249     /* Number of transmitted pause frames */
0250     u32 tx_pause_mac_ctrl_frames;
0251     /* Number of Received pause frames */
0252     u32 rx_pause_mac_ctrl_frames;
0253
0254     /* IETF MIB (MIB-II) Object Support */
0255
0256     /* Number of frames received with error */
0257     u32 if_in_errors;
0258     /* Number of frames transmitted with error */
0259     u32 if_out_errors;
0260     /* Number of valid received unicast frames */
0261     u32 if_in_ucast_pkts;
0262     /* Number of valid received multicasts frames (without pause) */
0263     u32 if_in_multicast_pkts;
0264     /* Number of valid received broadcast frames */
0265     u32 if_in_broadcast_pkts;
0266     u32 if_out_discards;
0267     /* The number of valid unicast frames transmitted */
0268     u32 if_out_ucast_pkts;
0269     /* The number of valid multicast frames transmitted,
0270      * excluding pause frames
0271      */
0272     u32 if_out_multicast_pkts;
0273     u32 if_out_broadcast_pkts;
0274
0275     /* IETF RMON MIB Object Support */
0276
0277     /* Counts the number of dropped packets due to internal errors
0278      * of the MAC client.
0279      */
0280     u32 ether_stats_drop_events;
0281     /* Total number of bytes received. Good and bad frames. */
0282     u32 ether_stats_octets;
0283     /* Total number of packets received. Counts good and bad packets. */
0284     u32 ether_stats_pkts;
0285     /* Number of packets received with less than 64 bytes. */
0286     u32 ether_stats_undersize_pkts;
0287     /* The number of frames received that are longer than the
0288      * value configured in the frm_length register
0289      */
0290     u32 ether_stats_oversize_pkts;
0291     /* Number of received packet with 64 bytes */
0292     u32 ether_stats_pkts_64_octets;
0293     /* Frames (good and bad) with 65 to 127 bytes */
0294     u32 ether_stats_pkts_65to127_octets;
0295     /* Frames (good and bad) with 128 to 255 bytes */
0296     u32 ether_stats_pkts_128to255_octets;
0297     /* Frames (good and bad) with 256 to 511 bytes */
0298     u32 ether_stats_pkts_256to511_octets;
0299     /* Frames (good and bad) with 512 to 1023 bytes */
0300     u32 ether_stats_pkts_512to1023_octets;
0301     /* Frames (good and bad) with 1024 to 1518 bytes */
0302     u32 ether_stats_pkts_1024to1518_octets;
0303
0304     /* Any frame length from 1519 to the maximum length configured in the
0305      * frm_length register, if it is greater than 1518
0306      */
0307     u32 ether_stats_pkts_1519tox_octets;
0308     /* Too long frames with CRC error */
0309     u32 ether_stats_jabbers;
0310     /* Too short frames with CRC error */
0311     u32 ether_stats_fragments;
0312
0313     u32 reserved2;
0314
0315     /* FIFO control register */
0316     u32 tx_cmd_stat;
0317     u32 rx_cmd_stat;
0318
0319     /* Extended Statistics Counters */
0320     u32 msb_octets_transmitted_ok;
0321     u32 msb_octets_received_ok;
0322     u32 msb_ether_stats_octets;
0323
0324     u32 reserved3;
0325
0326     /* Multicast address resolution table, mapped in the controller address
0327      * space
0328      */
0329     u32 hash_table[64];
0330
0331     /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
0332      * management interface
0333      */
0334     struct altera_tse_mdio mdio_phy0;
0335     struct altera_tse_mdio mdio_phy1;
0336
0337     /* 4 Supplemental MAC Addresses */
0338     u32 supp_mac_addr_0_0;
0339     u32 supp_mac_addr_0_1;
0340     u32 supp_mac_addr_1_0;
0341     u32 supp_mac_addr_1_1;
0342     u32 supp_mac_addr_2_0;
0343     u32 supp_mac_addr_2_1;
0344     u32 supp_mac_addr_3_0;
0345     u32 supp_mac_addr_3_1;
0346
0347     u32 reserved4[8];
0348
0349     /* IEEE 1588v2 Feature */
0350     u32 tx_period;
0351     u32 tx_adjust_fns;
0352     u32 tx_adjust_ns;
0353     u32 rx_period;
0354     u32 rx_adjust_fns;
0355     u32 rx_adjust_ns;
0356
0357     u32 reserved5[42];
0358 };
0359
0360 #define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
0361
0362 /* Transmit and Receive Command Registers Bit Definitions
0363  */
0364 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC     BIT(17)
0365 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16   BIT(18)
0366 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16   BIT(25)
0367
0368 /* Wrapper around a pointer to a socket buffer,
0369  * so a DMA handle can be stored along with the buffer
0370  */
0371 struct tse_buffer {
0372     struct list_head lh;
0373     struct sk_buff *skb;
0374     dma_addr_t dma_addr;
0375     u32 len;
0376     int mapped_as_page;
0377 };
0378
0379 struct altera_tse_private;
0380
0381 #define ALTERA_DTYPE_SGDMA 1
0382 #define ALTERA_DTYPE_MSGDMA 2
0383
0384 /* standard DMA interface for SGDMA and MSGDMA */
0385 struct altera_dmaops {
0386     int altera_dtype;
0387     int dmamask;
0388     void (*reset_dma)(struct altera_tse_private *);
0389     void (*enable_txirq)(struct altera_tse_private *);
0390     void (*enable_rxirq)(struct altera_tse_private *);
0391     void (*disable_txirq)(struct altera_tse_private *);
0392     void (*disable_rxirq)(struct altera_tse_private *);
0393     void (*clear_txirq)(struct altera_tse_private *);
0394     void (*clear_rxirq)(struct altera_tse_private *);
0395     int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
0396     u32 (*tx_completions)(struct altera_tse_private *);
0397     void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
0398     u32 (*get_rx_status)(struct altera_tse_private *);
0399     int (*init_dma)(struct altera_tse_private *);
0400     void (*uninit_dma)(struct altera_tse_private *);
0401     void (*start_rxdma)(struct altera_tse_private *);
0402 };
0403
0404 /* This structure is private to each device.
0405  */
0406 struct altera_tse_private {
0407     struct net_device *dev;
0408     struct device *device;
0409     struct napi_struct napi;
0410
0411     /* MAC address space */
0412     struct altera_tse_mac __iomem *mac_dev;
0413
0414     /* TSE Revision */
0415     u32 revision;
0416
0417     /* mSGDMA Rx Dispatcher address space */
0418     void __iomem *rx_dma_csr;
0419     void __iomem *rx_dma_desc;
0420     void __iomem *rx_dma_resp;
0421
0422     /* mSGDMA Tx Dispatcher address space */
0423     void __iomem *tx_dma_csr;
0424     void __iomem *tx_dma_desc;
0425
0426     /* Rx buffers queue */
0427     struct tse_buffer *rx_ring;
0428     u32 rx_cons;
0429     u32 rx_prod;
0430     u32 rx_ring_size;
0431     u32 rx_dma_buf_sz;
0432
0433     /* Tx ring buffer */
0434     struct tse_buffer *tx_ring;
0435     u32 tx_prod;
0436     u32 tx_cons;
0437     u32 tx_ring_size;
0438
0439     /* Interrupts */
0440     u32 tx_irq;
0441     u32 rx_irq;
0442
0443     /* RX/TX MAC FIFO configs */
0444     u32 tx_fifo_depth;
0445     u32 rx_fifo_depth;
0446
0447     /* Hash filter settings */
0448     u32 hash_filter;
0449     u32 added_unicast;
0450
0451     /* Descriptor memory info for managing SGDMA */
0452     u32 txdescmem;
0453     u32 rxdescmem;
0454     dma_addr_t rxdescmem_busaddr;
0455     dma_addr_t txdescmem_busaddr;
0456     u32 txctrlreg;
0457     u32 rxctrlreg;
0458     dma_addr_t rxdescphys;
0459     dma_addr_t txdescphys;
0460
0461     struct list_head txlisthd;
0462     struct list_head rxlisthd;
0463
0464     /* MAC command_config register protection */
0465     spinlock_t mac_cfg_lock;
0466     /* Tx path protection */
0467     spinlock_t tx_lock;
0468     /* Rx DMA & interrupt control protection */
0469     spinlock_t rxdma_irq_lock;
0470
0471     /* PHY */
0472     int phy_addr;       /* PHY's MDIO address, -1 for autodetection */
0473     phy_interface_t phy_iface;
0474     struct mii_bus *mdio;
0475     int oldspeed;
0476     int oldduplex;
0477     int oldlink;
0478
0479     /* ethtool msglvl option */
0480     u32 msg_enable;
0481
0482     struct altera_dmaops *dmaops;
0483 };
0484
0485 /* Function prototypes
0486  */
0487 void altera_tse_set_ethtool_ops(struct net_device *);
0488
0489 static inline
0490 u32 csrrd32(void __iomem *mac, size_t offs)
0491 {
0492     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0493     return readl(paddr);
0494 }
0495
0496 static inline
0497 u16 csrrd16(void __iomem *mac, size_t offs)
0498 {
0499     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0500     return readw(paddr);
0501 }
0502
0503 static inline
0504 u8 csrrd8(void __iomem *mac, size_t offs)
0505 {
0506     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0507     return readb(paddr);
0508 }
0509
0510 static inline
0511 void csrwr32(u32 val, void __iomem *mac, size_t offs)
0512 {
0513     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0514
0515     writel(val, paddr);
0516 }
0517
0518 static inline
0519 void csrwr16(u16 val, void __iomem *mac, size_t offs)
0520 {
0521     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0522
0523     writew(val, paddr);
0524 }
0525
0526 static inline
0527 void csrwr8(u8 val, void __iomem *mac, size_t offs)
0528 {
0529     void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
0530
0531     writeb(val, paddr);
0532 }
0533
0534 #endif /* __ALTERA_TSE_H__ */