ethernet/altera/altera_sgdmahw.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Altera TSE SGDMA and MSGDMA Linux driver
0003  * Copyright (C) 2014 Altera Corporation. All rights reserved
0004  */
0005
0006 #ifndef __ALTERA_SGDMAHW_H__
0007 #define __ALTERA_SGDMAHW_H__
0008
0009 /* SGDMA descriptor structure */
0010 struct sgdma_descrip {
0011     u32 raddr; /* address of data to be read */
0012     u32 pad1;
0013     u32 waddr;
0014     u32 pad2;
0015     u32 next;
0016     u32 pad3;
0017     u16 bytes;
0018     u8  rburst;
0019     u8  wburst;
0020     u16 bytes_xferred;  /* 16 bits, bytes xferred */
0021
0022     /* bit 0: error
0023      * bit 1: length error
0024      * bit 2: crc error
0025      * bit 3: truncated error
0026      * bit 4: phy error
0027      * bit 5: collision error
0028      * bit 6: reserved
0029      * bit 7: status eop for recv case
0030      */
0031     u8  status;
0032
0033     /* bit 0: eop
0034      * bit 1: read_fixed
0035      * bit 2: write fixed
0036      * bits 3,4,5,6: Channel (always 0)
0037      * bit 7: hardware owned
0038      */
0039     u8  control;
0040 } __packed;
0041
0042 #define SGDMA_DESC_LEN  sizeof(struct sgdma_descrip)
0043
0044 #define SGDMA_STATUS_ERR        BIT(0)
0045 #define SGDMA_STATUS_LENGTH_ERR     BIT(1)
0046 #define SGDMA_STATUS_CRC_ERR        BIT(2)
0047 #define SGDMA_STATUS_TRUNC_ERR      BIT(3)
0048 #define SGDMA_STATUS_PHY_ERR        BIT(4)
0049 #define SGDMA_STATUS_COLL_ERR       BIT(5)
0050 #define SGDMA_STATUS_EOP        BIT(7)
0051
0052 #define SGDMA_CONTROL_EOP       BIT(0)
0053 #define SGDMA_CONTROL_RD_FIXED      BIT(1)
0054 #define SGDMA_CONTROL_WR_FIXED      BIT(2)
0055
0056 /* Channel is always 0, so just zero initialize it */
0057
0058 #define SGDMA_CONTROL_HW_OWNED      BIT(7)
0059
0060 /* SGDMA register space */
0061 struct sgdma_csr {
0062     /* bit 0: error
0063      * bit 1: eop
0064      * bit 2: descriptor completed
0065      * bit 3: chain completed
0066      * bit 4: busy
0067      * remainder reserved
0068      */
0069     u32 status;
0070     u32 pad1[3];
0071
0072     /* bit 0: interrupt on error
0073      * bit 1: interrupt on eop
0074      * bit 2: interrupt after every descriptor
0075      * bit 3: interrupt after last descrip in a chain
0076      * bit 4: global interrupt enable
0077      * bit 5: starts descriptor processing
0078      * bit 6: stop core on dma error
0079      * bit 7: interrupt on max descriptors
0080      * bits 8-15: max descriptors to generate interrupt
0081      * bit 16: Software reset
0082      * bit 17: clears owned by hardware if 0, does not clear otherwise
0083      * bit 18: enables descriptor polling mode
0084      * bit 19-26: clocks before polling again
0085      * bit 27-30: reserved
0086      * bit 31: clear interrupt
0087      */
0088     u32 control;
0089     u32 pad2[3];
0090     u32 next_descrip;
0091     u32 pad3[3];
0092 };
0093
0094 #define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a))
0095 #define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a))
0096
0097 #define SGDMA_STSREG_ERR    BIT(0) /* Error */
0098 #define SGDMA_STSREG_EOP    BIT(1) /* EOP */
0099 #define SGDMA_STSREG_DESCRIP    BIT(2) /* Descriptor completed */
0100 #define SGDMA_STSREG_CHAIN  BIT(3) /* Chain completed */
0101 #define SGDMA_STSREG_BUSY   BIT(4) /* Controller busy */
0102
0103 #define SGDMA_CTRLREG_IOE   BIT(0) /* Interrupt on error */
0104 #define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */
0105 #define SGDMA_CTRLREG_IDESCRIP  BIT(2) /* Interrupt after every descriptor */
0106 #define SGDMA_CTRLREG_ILASTD    BIT(3) /* Interrupt after last descriptor */
0107 #define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */
0108 #define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */
0109 #define SGDMA_CTRLREG_STOPERR   BIT(6) /* stop on dma error */
0110 #define SGDMA_CTRLREG_INTMAX    BIT(7) /* Interrupt on max descriptors */
0111 #define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */
0112 #define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */
0113 #define SGDMA_CTRLREG_POLL  BIT(18)/* enables descriptor polling mode */
0114 #define SGDMA_CTRLREG_CLRINT    BIT(31)/* Clears interrupt */
0115
0116 #endif /* __ALTERA_SGDMAHW_H__ */