ethernet/altera/altera_msgdmahw.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Altera TSE SGDMA and MSGDMA Linux driver
0003  * Copyright (C) 2014 Altera Corporation. All rights reserved
0004  */
0005
0006 #ifndef __ALTERA_MSGDMAHW_H__
0007 #define __ALTERA_MSGDMAHW_H__
0008
0009 /* mSGDMA extended descriptor format
0010  */
0011 struct msgdma_extended_desc {
0012     u32 read_addr_lo;   /* data buffer source address low bits */
0013     u32 write_addr_lo;  /* data buffer destination address low bits */
0014     u32 len;        /* the number of bytes to transfer
0015                  * per descriptor
0016                  */
0017     u32 burst_seq_num;  /* bit 31:24 write burst
0018                  * bit 23:16 read burst
0019                  * bit 15:0  sequence number
0020                  */
0021     u32 stride;     /* bit 31:16 write stride
0022                  * bit 15:0  read stride
0023                  */
0024     u32 read_addr_hi;   /* data buffer source address high bits */
0025     u32 write_addr_hi;  /* data buffer destination address high bits */
0026     u32 control;        /* characteristics of the transfer */
0027 };
0028
0029 /* mSGDMA descriptor control field bit definitions
0030  */
0031 #define MSGDMA_DESC_CTL_SET_CH(x)   ((x) & 0xff)
0032 #define MSGDMA_DESC_CTL_GEN_SOP     BIT(8)
0033 #define MSGDMA_DESC_CTL_GEN_EOP     BIT(9)
0034 #define MSGDMA_DESC_CTL_PARK_READS  BIT(10)
0035 #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
0036 #define MSGDMA_DESC_CTL_END_ON_EOP  BIT(12)
0037 #define MSGDMA_DESC_CTL_END_ON_LEN  BIT(13)
0038 #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
0039 #define MSGDMA_DESC_CTL_EARLY_IRQ   BIT(15)
0040 #define MSGDMA_DESC_CTL_TR_ERR_IRQ  (0xff << 16)
0041 #define MSGDMA_DESC_CTL_EARLY_DONE  BIT(24)
0042 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
0043  * descriptor FIFO(s)
0044  */
0045 #define MSGDMA_DESC_CTL_GO      BIT(31)
0046
0047 /* Tx buffer control flags
0048  */
0049 #define MSGDMA_DESC_CTL_TX_FIRST    (MSGDMA_DESC_CTL_GEN_SOP |  \
0050                      MSGDMA_DESC_CTL_GO)
0051
0052 #define MSGDMA_DESC_CTL_TX_MIDDLE   (MSGDMA_DESC_CTL_GO)
0053
0054 #define MSGDMA_DESC_CTL_TX_LAST     (MSGDMA_DESC_CTL_GEN_EOP |  \
0055                      MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
0056                      MSGDMA_DESC_CTL_GO)
0057
0058 #define MSGDMA_DESC_CTL_TX_SINGLE   (MSGDMA_DESC_CTL_GEN_SOP |  \
0059                      MSGDMA_DESC_CTL_GEN_EOP |  \
0060                      MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
0061                      MSGDMA_DESC_CTL_GO)
0062
0063 #define MSGDMA_DESC_CTL_RX_SINGLE   (MSGDMA_DESC_CTL_END_ON_EOP |   \
0064                      MSGDMA_DESC_CTL_END_ON_LEN |   \
0065                      MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
0066                      MSGDMA_DESC_CTL_EARLY_IRQ |    \
0067                      MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
0068                      MSGDMA_DESC_CTL_GO)
0069
0070 /* mSGDMA extended descriptor stride definitions
0071  */
0072 #define MSGDMA_DESC_TX_STRIDE       (0x00010001)
0073 #define MSGDMA_DESC_RX_STRIDE       (0x00010001)
0074
0075 /* mSGDMA dispatcher control and status register map
0076  */
0077 struct msgdma_csr {
0078     u32 status;     /* Read/Clear */
0079     u32 control;        /* Read/Write */
0080     u32 rw_fill_level;  /* bit 31:16 - write fill level
0081                  * bit 15:0  - read fill level
0082                  */
0083     u32 resp_fill_level;    /* bit 15:0 */
0084     u32 rw_seq_num;     /* bit 31:16 - write sequence number
0085                  * bit 15:0  - read sequence number
0086                  */
0087     u32 pad[3];     /* reserved */
0088 };
0089
0090 /* mSGDMA CSR status register bit definitions
0091  */
0092 #define MSGDMA_CSR_STAT_BUSY            BIT(0)
0093 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY      BIT(1)
0094 #define MSGDMA_CSR_STAT_DESC_BUF_FULL       BIT(2)
0095 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY      BIT(3)
0096 #define MSGDMA_CSR_STAT_RESP_BUF_FULL       BIT(4)
0097 #define MSGDMA_CSR_STAT_STOPPED         BIT(5)
0098 #define MSGDMA_CSR_STAT_RESETTING       BIT(6)
0099 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR      BIT(7)
0100 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY    BIT(8)
0101 #define MSGDMA_CSR_STAT_IRQ         BIT(9)
0102 #define MSGDMA_CSR_STAT_MASK            0x3FF
0103 #define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ    0x1FF
0104
0105 #define MSGDMA_CSR_STAT_BUSY_GET(v)         GET_BIT_VALUE(v, 0)
0106 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v)       GET_BIT_VALUE(v, 1)
0107 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v)        GET_BIT_VALUE(v, 2)
0108 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v)       GET_BIT_VALUE(v, 3)
0109 #define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v)        GET_BIT_VALUE(v, 4)
0110 #define MSGDMA_CSR_STAT_STOPPED_GET(v)          GET_BIT_VALUE(v, 5)
0111 #define MSGDMA_CSR_STAT_RESETTING_GET(v)        GET_BIT_VALUE(v, 6)
0112 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v)       GET_BIT_VALUE(v, 7)
0113 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v)     GET_BIT_VALUE(v, 8)
0114 #define MSGDMA_CSR_STAT_IRQ_GET(v)          GET_BIT_VALUE(v, 9)
0115
0116 /* mSGDMA CSR control register bit definitions
0117  */
0118 #define MSGDMA_CSR_CTL_STOP         BIT(0)
0119 #define MSGDMA_CSR_CTL_RESET            BIT(1)
0120 #define MSGDMA_CSR_CTL_STOP_ON_ERR      BIT(2)
0121 #define MSGDMA_CSR_CTL_STOP_ON_EARLY        BIT(3)
0122 #define MSGDMA_CSR_CTL_GLOBAL_INTR      BIT(4)
0123 #define MSGDMA_CSR_CTL_STOP_DESCS       BIT(5)
0124
0125 /* mSGDMA CSR fill level bits
0126  */
0127 #define MSGDMA_CSR_WR_FILL_LEVEL_GET(v)     (((v) & 0xffff0000) >> 16)
0128 #define MSGDMA_CSR_RD_FILL_LEVEL_GET(v)     ((v) & 0x0000ffff)
0129 #define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v)   ((v) & 0x0000ffff)
0130
0131 /* mSGDMA response register map
0132  */
0133 struct msgdma_response {
0134     u32 bytes_transferred;
0135     u32 status;
0136 };
0137
0138 #define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
0139 #define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
0140 #define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
0141
0142 /* mSGDMA response register bit definitions
0143  */
0144 #define MSGDMA_RESP_EARLY_TERM  BIT(8)
0145 #define MSGDMA_RESP_ERR_MASK    0xFF
0146
0147 #endif /* __ALTERA_MSGDMA_H__*/