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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Altera TSE SGDMA and MSGDMA Linux driver
0003  * Copyright (C) 2014 Altera Corporation. All rights reserved
0004  */
0005 
0006 #include <linux/netdevice.h>
0007 #include "altera_utils.h"
0008 #include "altera_tse.h"
0009 #include "altera_msgdmahw.h"
0010 #include "altera_msgdma.h"
0011 
0012 /* No initialization work to do for MSGDMA */
0013 int msgdma_initialize(struct altera_tse_private *priv)
0014 {
0015     return 0;
0016 }
0017 
0018 void msgdma_uninitialize(struct altera_tse_private *priv)
0019 {
0020 }
0021 
0022 void msgdma_start_rxdma(struct altera_tse_private *priv)
0023 {
0024 }
0025 
0026 void msgdma_reset(struct altera_tse_private *priv)
0027 {
0028     int counter;
0029 
0030     /* Reset Rx mSGDMA */
0031     csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
0032         msgdma_csroffs(status));
0033     csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
0034         msgdma_csroffs(control));
0035 
0036     counter = 0;
0037     while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
0038         if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
0039                      MSGDMA_CSR_STAT_RESETTING))
0040             break;
0041         udelay(1);
0042     }
0043 
0044     if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
0045         netif_warn(priv, drv, priv->dev,
0046                "TSE Rx mSGDMA resetting bit never cleared!\n");
0047 
0048     /* clear all status bits */
0049     csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
0050 
0051     /* Reset Tx mSGDMA */
0052     csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
0053         msgdma_csroffs(status));
0054 
0055     csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
0056         msgdma_csroffs(control));
0057 
0058     counter = 0;
0059     while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
0060         if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
0061                      MSGDMA_CSR_STAT_RESETTING))
0062             break;
0063         udelay(1);
0064     }
0065 
0066     if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
0067         netif_warn(priv, drv, priv->dev,
0068                "TSE Tx mSGDMA resetting bit never cleared!\n");
0069 
0070     /* clear all status bits */
0071     csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
0072 }
0073 
0074 void msgdma_disable_rxirq(struct altera_tse_private *priv)
0075 {
0076     tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
0077               MSGDMA_CSR_CTL_GLOBAL_INTR);
0078 }
0079 
0080 void msgdma_enable_rxirq(struct altera_tse_private *priv)
0081 {
0082     tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
0083             MSGDMA_CSR_CTL_GLOBAL_INTR);
0084 }
0085 
0086 void msgdma_disable_txirq(struct altera_tse_private *priv)
0087 {
0088     tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
0089               MSGDMA_CSR_CTL_GLOBAL_INTR);
0090 }
0091 
0092 void msgdma_enable_txirq(struct altera_tse_private *priv)
0093 {
0094     tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
0095             MSGDMA_CSR_CTL_GLOBAL_INTR);
0096 }
0097 
0098 void msgdma_clear_rxirq(struct altera_tse_private *priv)
0099 {
0100     csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
0101 }
0102 
0103 void msgdma_clear_txirq(struct altera_tse_private *priv)
0104 {
0105     csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
0106 }
0107 
0108 /* return 0 to indicate transmit is pending */
0109 int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
0110 {
0111     csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
0112         msgdma_descroffs(read_addr_lo));
0113     csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
0114         msgdma_descroffs(read_addr_hi));
0115     csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
0116     csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
0117     csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
0118     csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
0119     csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
0120         msgdma_descroffs(stride));
0121     csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
0122         msgdma_descroffs(control));
0123     return 0;
0124 }
0125 
0126 u32 msgdma_tx_completions(struct altera_tse_private *priv)
0127 {
0128     u32 ready = 0;
0129     u32 inuse;
0130     u32 status;
0131 
0132     /* Get number of sent descriptors */
0133     inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
0134             & 0xffff;
0135 
0136     if (inuse) { /* Tx FIFO is not empty */
0137         ready = max_t(int,
0138                   priv->tx_prod - priv->tx_cons - inuse - 1, 0);
0139     } else {
0140         /* Check for buffered last packet */
0141         status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
0142         if (status & MSGDMA_CSR_STAT_BUSY)
0143             ready = priv->tx_prod - priv->tx_cons - 1;
0144         else
0145             ready = priv->tx_prod - priv->tx_cons;
0146     }
0147     return ready;
0148 }
0149 
0150 /* Put buffer to the mSGDMA RX FIFO
0151  */
0152 void msgdma_add_rx_desc(struct altera_tse_private *priv,
0153             struct tse_buffer *rxbuffer)
0154 {
0155     u32 len = priv->rx_dma_buf_sz;
0156     dma_addr_t dma_addr = rxbuffer->dma_addr;
0157     u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
0158             | MSGDMA_DESC_CTL_END_ON_LEN
0159             | MSGDMA_DESC_CTL_TR_COMP_IRQ
0160             | MSGDMA_DESC_CTL_EARLY_IRQ
0161             | MSGDMA_DESC_CTL_TR_ERR_IRQ
0162             | MSGDMA_DESC_CTL_GO);
0163 
0164     csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
0165     csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
0166     csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
0167         msgdma_descroffs(write_addr_lo));
0168     csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
0169         msgdma_descroffs(write_addr_hi));
0170     csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
0171     csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
0172     csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
0173     csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
0174 }
0175 
0176 /* status is returned on upper 16 bits,
0177  * length is returned in lower 16 bits
0178  */
0179 u32 msgdma_rx_status(struct altera_tse_private *priv)
0180 {
0181     u32 rxstatus = 0;
0182     u32 pktlength;
0183     u32 pktstatus;
0184 
0185     if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
0186         & 0xffff) {
0187         pktlength = csrrd32(priv->rx_dma_resp,
0188                     msgdma_respoffs(bytes_transferred));
0189         pktstatus = csrrd32(priv->rx_dma_resp,
0190                     msgdma_respoffs(status));
0191         rxstatus = pktstatus;
0192         rxstatus = rxstatus << 16;
0193         rxstatus |= (pktlength & 0xffff);
0194     }
0195     return rxstatus;
0196 }
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