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0001 /*
0002  * Allwinner EMAC Fast Ethernet driver for Linux.
0003  *
0004  * Copyright 2012-2013 Stefan Roese <sr@denx.de>
0005  * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
0006  *
0007  * Based on the Linux driver provided by Allwinner:
0008  * Copyright (C) 1997  Sten Wang
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2. This program is licensed "as is" without any
0012  * warranty of any kind, whether express or implied.
0013  */
0014 
0015 #include <linux/clk.h>
0016 #include <linux/etherdevice.h>
0017 #include <linux/ethtool.h>
0018 #include <linux/gpio.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/irq.h>
0021 #include <linux/mii.h>
0022 #include <linux/module.h>
0023 #include <linux/netdevice.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_irq.h>
0026 #include <linux/of_mdio.h>
0027 #include <linux/of_net.h>
0028 #include <linux/of_platform.h>
0029 #include <linux/platform_device.h>
0030 #include <linux/phy.h>
0031 #include <linux/soc/sunxi/sunxi_sram.h>
0032 #include <linux/dmaengine.h>
0033 
0034 #include "sun4i-emac.h"
0035 
0036 #define DRV_NAME        "sun4i-emac"
0037 
0038 #define EMAC_MAX_FRAME_LEN  0x0600
0039 
0040 #define EMAC_DEFAULT_MSG_ENABLE 0x0000
0041 static int debug = -1;     /* defaults above */;
0042 module_param(debug, int, 0);
0043 MODULE_PARM_DESC(debug, "debug message flags");
0044 
0045 /* Transmit timeout, default 5 seconds. */
0046 static int watchdog = 5000;
0047 module_param(watchdog, int, 0400);
0048 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
0049 
0050 /* EMAC register address locking.
0051  *
0052  * The EMAC uses an address register to control where data written
0053  * to the data register goes. This means that the address register
0054  * must be preserved over interrupts or similar calls.
0055  *
0056  * During interrupt and other critical calls, a spinlock is used to
0057  * protect the system, but the calls themselves save the address
0058  * in the address register in case they are interrupting another
0059  * access to the device.
0060  *
0061  * For general accesses a lock is provided so that calls which are
0062  * allowed to sleep are serialised so that the address register does
0063  * not need to be saved. This lock also serves to serialise access
0064  * to the EEPROM and PHY access registers which are shared between
0065  * these two devices.
0066  */
0067 
0068 /* The driver supports the original EMACE, and now the two newer
0069  * devices, EMACA and EMACB.
0070  */
0071 
0072 struct emac_board_info {
0073     struct clk      *clk;
0074     struct device       *dev;
0075     struct platform_device  *pdev;
0076     spinlock_t      lock;
0077     void __iomem        *membase;
0078     u32         msg_enable;
0079     struct net_device   *ndev;
0080     u16         tx_fifo_stat;
0081 
0082     int         emacrx_completed_flag;
0083 
0084     struct device_node  *phy_node;
0085     unsigned int        link;
0086     unsigned int        speed;
0087     unsigned int        duplex;
0088 
0089     phy_interface_t     phy_interface;
0090     struct dma_chan *rx_chan;
0091     phys_addr_t emac_rx_fifo;
0092 };
0093 
0094 struct emac_dma_req {
0095     struct emac_board_info *db;
0096     struct dma_async_tx_descriptor *desc;
0097     struct sk_buff *skb;
0098     dma_addr_t rxbuf;
0099     int count;
0100 };
0101 
0102 static void emac_update_speed(struct net_device *dev)
0103 {
0104     struct emac_board_info *db = netdev_priv(dev);
0105     unsigned int reg_val;
0106 
0107     /* set EMAC SPEED, depend on PHY  */
0108     reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
0109     reg_val &= ~EMAC_MAC_SUPP_100M;
0110     if (db->speed == SPEED_100)
0111         reg_val |= EMAC_MAC_SUPP_100M;
0112     writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
0113 }
0114 
0115 static void emac_update_duplex(struct net_device *dev)
0116 {
0117     struct emac_board_info *db = netdev_priv(dev);
0118     unsigned int reg_val;
0119 
0120     /* set duplex depend on phy */
0121     reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
0122     reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
0123     if (db->duplex)
0124         reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
0125     writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
0126 }
0127 
0128 static void emac_handle_link_change(struct net_device *dev)
0129 {
0130     struct emac_board_info *db = netdev_priv(dev);
0131     struct phy_device *phydev = dev->phydev;
0132     unsigned long flags;
0133     int status_change = 0;
0134 
0135     if (phydev->link) {
0136         if (db->speed != phydev->speed) {
0137             spin_lock_irqsave(&db->lock, flags);
0138             db->speed = phydev->speed;
0139             emac_update_speed(dev);
0140             spin_unlock_irqrestore(&db->lock, flags);
0141             status_change = 1;
0142         }
0143 
0144         if (db->duplex != phydev->duplex) {
0145             spin_lock_irqsave(&db->lock, flags);
0146             db->duplex = phydev->duplex;
0147             emac_update_duplex(dev);
0148             spin_unlock_irqrestore(&db->lock, flags);
0149             status_change = 1;
0150         }
0151     }
0152 
0153     if (phydev->link != db->link) {
0154         if (!phydev->link) {
0155             db->speed = 0;
0156             db->duplex = -1;
0157         }
0158         db->link = phydev->link;
0159 
0160         status_change = 1;
0161     }
0162 
0163     if (status_change)
0164         phy_print_status(phydev);
0165 }
0166 
0167 static int emac_mdio_probe(struct net_device *dev)
0168 {
0169     struct emac_board_info *db = netdev_priv(dev);
0170     struct phy_device *phydev;
0171 
0172     /* to-do: PHY interrupts are currently not supported */
0173 
0174     /* attach the mac to the phy */
0175     phydev = of_phy_connect(db->ndev, db->phy_node,
0176                 &emac_handle_link_change, 0,
0177                 db->phy_interface);
0178     if (!phydev) {
0179         netdev_err(db->ndev, "could not find the PHY\n");
0180         return -ENODEV;
0181     }
0182 
0183     /* mask with MAC supported features */
0184     phy_set_max_speed(phydev, SPEED_100);
0185 
0186     db->link = 0;
0187     db->speed = 0;
0188     db->duplex = -1;
0189 
0190     return 0;
0191 }
0192 
0193 static void emac_mdio_remove(struct net_device *dev)
0194 {
0195     phy_disconnect(dev->phydev);
0196 }
0197 
0198 static void emac_reset(struct emac_board_info *db)
0199 {
0200     dev_dbg(db->dev, "resetting device\n");
0201 
0202     /* RESET device */
0203     writel(0, db->membase + EMAC_CTL_REG);
0204     udelay(200);
0205     writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
0206     udelay(200);
0207 }
0208 
0209 static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
0210 {
0211     writesl(reg, data, round_up(count, 4) / 4);
0212 }
0213 
0214 static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
0215 {
0216     readsl(reg, data, round_up(count, 4) / 4);
0217 }
0218 
0219 static struct emac_dma_req *
0220 emac_alloc_dma_req(struct emac_board_info *db,
0221            struct dma_async_tx_descriptor *desc, struct sk_buff *skb,
0222            dma_addr_t rxbuf, int count)
0223 {
0224     struct emac_dma_req *req;
0225 
0226     req = kzalloc(sizeof(struct emac_dma_req), GFP_ATOMIC);
0227     if (!req)
0228         return NULL;
0229 
0230     req->db = db;
0231     req->desc = desc;
0232     req->skb = skb;
0233     req->rxbuf = rxbuf;
0234     req->count = count;
0235     return req;
0236 }
0237 
0238 static void emac_free_dma_req(struct emac_dma_req *req)
0239 {
0240     kfree(req);
0241 }
0242 
0243 static void emac_dma_done_callback(void *arg)
0244 {
0245     struct emac_dma_req *req = arg;
0246     struct emac_board_info *db = req->db;
0247     struct sk_buff *skb = req->skb;
0248     struct net_device *dev = db->ndev;
0249     int rxlen = req->count;
0250     u32 reg_val;
0251 
0252     dma_unmap_single(db->dev, req->rxbuf, rxlen, DMA_FROM_DEVICE);
0253 
0254     skb->protocol = eth_type_trans(skb, dev);
0255     netif_rx(skb);
0256     dev->stats.rx_bytes += rxlen;
0257     /* Pass to upper layer */
0258     dev->stats.rx_packets++;
0259 
0260     /* re enable cpu receive */
0261     reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0262     reg_val &= ~EMAC_RX_CTL_DMA_EN;
0263     writel(reg_val, db->membase + EMAC_RX_CTL_REG);
0264 
0265     /* re enable interrupt */
0266     reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0267     reg_val |= EMAC_INT_CTL_RX_EN;
0268     writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0269 
0270     db->emacrx_completed_flag = 1;
0271     emac_free_dma_req(req);
0272 }
0273 
0274 static int emac_dma_inblk_32bit(struct emac_board_info *db,
0275         struct sk_buff *skb, void *rdptr, int count)
0276 {
0277     struct dma_async_tx_descriptor *desc;
0278     dma_cookie_t cookie;
0279     dma_addr_t rxbuf;
0280     struct emac_dma_req *req;
0281     int ret = 0;
0282 
0283     rxbuf = dma_map_single(db->dev, rdptr, count, DMA_FROM_DEVICE);
0284     ret = dma_mapping_error(db->dev, rxbuf);
0285     if (ret) {
0286         dev_err(db->dev, "dma mapping error.\n");
0287         return ret;
0288     }
0289 
0290     desc = dmaengine_prep_slave_single(db->rx_chan, rxbuf, count,
0291                        DMA_DEV_TO_MEM,
0292                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0293     if (!desc) {
0294         dev_err(db->dev, "prepare slave single failed\n");
0295         ret = -ENOMEM;
0296         goto prepare_err;
0297     }
0298 
0299     req = emac_alloc_dma_req(db, desc, skb, rxbuf, count);
0300     if (!req) {
0301         dev_err(db->dev, "alloc emac dma req error.\n");
0302         ret = -ENOMEM;
0303         goto alloc_req_err;
0304     }
0305 
0306     desc->callback_param = req;
0307     desc->callback = emac_dma_done_callback;
0308 
0309     cookie = dmaengine_submit(desc);
0310     ret = dma_submit_error(cookie);
0311     if (ret) {
0312         dev_err(db->dev, "dma submit error.\n");
0313         goto submit_err;
0314     }
0315 
0316     dma_async_issue_pending(db->rx_chan);
0317     return ret;
0318 
0319 submit_err:
0320     emac_free_dma_req(req);
0321 
0322 alloc_req_err:
0323     dmaengine_desc_free(desc);
0324 
0325 prepare_err:
0326     dma_unmap_single(db->dev, rxbuf, count, DMA_FROM_DEVICE);
0327     return ret;
0328 }
0329 
0330 /* ethtool ops */
0331 static void emac_get_drvinfo(struct net_device *dev,
0332                   struct ethtool_drvinfo *info)
0333 {
0334     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0335     strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
0336 }
0337 
0338 static u32 emac_get_msglevel(struct net_device *dev)
0339 {
0340     struct emac_board_info *db = netdev_priv(dev);
0341 
0342     return db->msg_enable;
0343 }
0344 
0345 static void emac_set_msglevel(struct net_device *dev, u32 value)
0346 {
0347     struct emac_board_info *db = netdev_priv(dev);
0348 
0349     db->msg_enable = value;
0350 }
0351 
0352 static const struct ethtool_ops emac_ethtool_ops = {
0353     .get_drvinfo    = emac_get_drvinfo,
0354     .get_link   = ethtool_op_get_link,
0355     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0356     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0357     .get_msglevel   = emac_get_msglevel,
0358     .set_msglevel   = emac_set_msglevel,
0359 };
0360 
0361 static unsigned int emac_setup(struct net_device *ndev)
0362 {
0363     struct emac_board_info *db = netdev_priv(ndev);
0364     unsigned int reg_val;
0365 
0366     /* set up TX */
0367     reg_val = readl(db->membase + EMAC_TX_MODE_REG);
0368 
0369     writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
0370         db->membase + EMAC_TX_MODE_REG);
0371 
0372     /* set MAC */
0373     /* set MAC CTL0 */
0374     reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
0375     writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
0376         EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
0377         db->membase + EMAC_MAC_CTL0_REG);
0378 
0379     /* set MAC CTL1 */
0380     reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
0381     reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
0382     reg_val |= EMAC_MAC_CTL1_CRC_EN;
0383     reg_val |= EMAC_MAC_CTL1_PAD_EN;
0384     writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
0385 
0386     /* set up IPGT */
0387     writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
0388 
0389     /* set up IPGR */
0390     writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
0391         db->membase + EMAC_MAC_IPGR_REG);
0392 
0393     /* set up Collison window */
0394     writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
0395         db->membase + EMAC_MAC_CLRT_REG);
0396 
0397     /* set up Max Frame Length */
0398     writel(EMAC_MAX_FRAME_LEN,
0399         db->membase + EMAC_MAC_MAXF_REG);
0400 
0401     return 0;
0402 }
0403 
0404 static void emac_set_rx_mode(struct net_device *ndev)
0405 {
0406     struct emac_board_info *db = netdev_priv(ndev);
0407     unsigned int reg_val;
0408 
0409     /* set up RX */
0410     reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0411 
0412     if (ndev->flags & IFF_PROMISC)
0413         reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
0414     else
0415         reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
0416 
0417     writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
0418         EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
0419         EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
0420         EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
0421         db->membase + EMAC_RX_CTL_REG);
0422 }
0423 
0424 static unsigned int emac_powerup(struct net_device *ndev)
0425 {
0426     struct emac_board_info *db = netdev_priv(ndev);
0427     unsigned int reg_val;
0428 
0429     /* initial EMAC */
0430     /* flush RX FIFO */
0431     reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0432     reg_val |= EMAC_RX_CTL_FLUSH_FIFO;
0433     writel(reg_val, db->membase + EMAC_RX_CTL_REG);
0434     udelay(1);
0435 
0436     /* initial MAC */
0437     /* soft reset MAC */
0438     reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
0439     reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
0440     writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
0441 
0442     /* set MII clock */
0443     reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
0444     reg_val &= ~EMAC_MAC_MCFG_MII_CLKD_MASK;
0445     reg_val |= EMAC_MAC_MCFG_MII_CLKD_72;
0446     writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
0447 
0448     /* clear RX counter */
0449     writel(0x0, db->membase + EMAC_RX_FBC_REG);
0450 
0451     /* disable all interrupt and clear interrupt status */
0452     writel(0, db->membase + EMAC_INT_CTL_REG);
0453     reg_val = readl(db->membase + EMAC_INT_STA_REG);
0454     writel(reg_val, db->membase + EMAC_INT_STA_REG);
0455 
0456     udelay(1);
0457 
0458     /* set up EMAC */
0459     emac_setup(ndev);
0460 
0461     /* set mac_address to chip */
0462     writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
0463            dev_addr[2], db->membase + EMAC_MAC_A1_REG);
0464     writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
0465            dev_addr[5], db->membase + EMAC_MAC_A0_REG);
0466 
0467     mdelay(1);
0468 
0469     return 0;
0470 }
0471 
0472 static int emac_set_mac_address(struct net_device *dev, void *p)
0473 {
0474     struct sockaddr *addr = p;
0475     struct emac_board_info *db = netdev_priv(dev);
0476 
0477     if (netif_running(dev))
0478         return -EBUSY;
0479 
0480     eth_hw_addr_set(dev, addr->sa_data);
0481 
0482     writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
0483            dev_addr[2], db->membase + EMAC_MAC_A1_REG);
0484     writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
0485            dev_addr[5], db->membase + EMAC_MAC_A0_REG);
0486 
0487     return 0;
0488 }
0489 
0490 /* Initialize emac board */
0491 static void emac_init_device(struct net_device *dev)
0492 {
0493     struct emac_board_info *db = netdev_priv(dev);
0494     unsigned long flags;
0495     unsigned int reg_val;
0496 
0497     spin_lock_irqsave(&db->lock, flags);
0498 
0499     emac_update_speed(dev);
0500     emac_update_duplex(dev);
0501 
0502     /* enable RX/TX */
0503     reg_val = readl(db->membase + EMAC_CTL_REG);
0504     writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
0505         db->membase + EMAC_CTL_REG);
0506 
0507     /* enable RX/TX0/RX Hlevel interrup */
0508     reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0509     reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN);
0510     writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0511 
0512     spin_unlock_irqrestore(&db->lock, flags);
0513 }
0514 
0515 /* Our watchdog timed out. Called by the networking layer */
0516 static void emac_timeout(struct net_device *dev, unsigned int txqueue)
0517 {
0518     struct emac_board_info *db = netdev_priv(dev);
0519     unsigned long flags;
0520 
0521     if (netif_msg_timer(db))
0522         dev_err(db->dev, "tx time out.\n");
0523 
0524     /* Save previous register address */
0525     spin_lock_irqsave(&db->lock, flags);
0526 
0527     netif_stop_queue(dev);
0528     emac_reset(db);
0529     emac_init_device(dev);
0530     /* We can accept TX packets again */
0531     netif_trans_update(dev);
0532     netif_wake_queue(dev);
0533 
0534     /* Restore previous register address */
0535     spin_unlock_irqrestore(&db->lock, flags);
0536 }
0537 
0538 /* Hardware start transmission.
0539  * Send a packet to media from the upper layer.
0540  */
0541 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
0542 {
0543     struct emac_board_info *db = netdev_priv(dev);
0544     unsigned long channel;
0545     unsigned long flags;
0546 
0547     channel = db->tx_fifo_stat & 3;
0548     if (channel == 3)
0549         return NETDEV_TX_BUSY;
0550 
0551     channel = (channel == 1 ? 1 : 0);
0552 
0553     spin_lock_irqsave(&db->lock, flags);
0554 
0555     writel(channel, db->membase + EMAC_TX_INS_REG);
0556 
0557     emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
0558             skb->data, skb->len);
0559     dev->stats.tx_bytes += skb->len;
0560 
0561     db->tx_fifo_stat |= 1 << channel;
0562     /* TX control: First packet immediately send, second packet queue */
0563     if (channel == 0) {
0564         /* set TX len */
0565         writel(skb->len, db->membase + EMAC_TX_PL0_REG);
0566         /* start translate from fifo to phy */
0567         writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
0568                db->membase + EMAC_TX_CTL0_REG);
0569 
0570         /* save the time stamp */
0571         netif_trans_update(dev);
0572     } else if (channel == 1) {
0573         /* set TX len */
0574         writel(skb->len, db->membase + EMAC_TX_PL1_REG);
0575         /* start translate from fifo to phy */
0576         writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
0577                db->membase + EMAC_TX_CTL1_REG);
0578 
0579         /* save the time stamp */
0580         netif_trans_update(dev);
0581     }
0582 
0583     if ((db->tx_fifo_stat & 3) == 3) {
0584         /* Second packet */
0585         netif_stop_queue(dev);
0586     }
0587 
0588     spin_unlock_irqrestore(&db->lock, flags);
0589 
0590     /* free this SKB */
0591     dev_consume_skb_any(skb);
0592 
0593     return NETDEV_TX_OK;
0594 }
0595 
0596 /* EMAC interrupt handler
0597  * receive the packet to upper layer, free the transmitted packet
0598  */
0599 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
0600               unsigned int tx_status)
0601 {
0602     /* One packet sent complete */
0603     db->tx_fifo_stat &= ~(tx_status & 3);
0604     if (3 == (tx_status & 3))
0605         dev->stats.tx_packets += 2;
0606     else
0607         dev->stats.tx_packets++;
0608 
0609     if (netif_msg_tx_done(db))
0610         dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
0611 
0612     netif_wake_queue(dev);
0613 }
0614 
0615 /* Received a packet and pass to upper layer
0616  */
0617 static void emac_rx(struct net_device *dev)
0618 {
0619     struct emac_board_info *db = netdev_priv(dev);
0620     struct sk_buff *skb;
0621     u8 *rdptr;
0622     bool good_packet;
0623     unsigned int reg_val;
0624     u32 rxhdr, rxstatus, rxcount, rxlen;
0625 
0626     /* Check packet ready or not */
0627     while (1) {
0628         /* race warning: the first packet might arrive with
0629          * the interrupts disabled, but the second will fix
0630          * it
0631          */
0632         rxcount = readl(db->membase + EMAC_RX_FBC_REG);
0633 
0634         if (netif_msg_rx_status(db))
0635             dev_dbg(db->dev, "RXCount: %x\n", rxcount);
0636 
0637         if (!rxcount) {
0638             db->emacrx_completed_flag = 1;
0639             reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0640             reg_val |= (EMAC_INT_CTL_TX_EN |
0641                     EMAC_INT_CTL_TX_ABRT_EN |
0642                     EMAC_INT_CTL_RX_EN);
0643             writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0644 
0645             /* had one stuck? */
0646             rxcount = readl(db->membase + EMAC_RX_FBC_REG);
0647             if (!rxcount)
0648                 return;
0649         }
0650 
0651         reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
0652         if (netif_msg_rx_status(db))
0653             dev_dbg(db->dev, "receive header: %x\n", reg_val);
0654         if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
0655             /* disable RX */
0656             reg_val = readl(db->membase + EMAC_CTL_REG);
0657             writel(reg_val & ~EMAC_CTL_RX_EN,
0658                    db->membase + EMAC_CTL_REG);
0659 
0660             /* Flush RX FIFO */
0661             reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0662             writel(reg_val | (1 << 3),
0663                    db->membase + EMAC_RX_CTL_REG);
0664 
0665             do {
0666                 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0667             } while (reg_val & (1 << 3));
0668 
0669             /* enable RX */
0670             reg_val = readl(db->membase + EMAC_CTL_REG);
0671             writel(reg_val | EMAC_CTL_RX_EN,
0672                    db->membase + EMAC_CTL_REG);
0673             reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0674             reg_val |= (EMAC_INT_CTL_TX_EN |
0675                     EMAC_INT_CTL_TX_ABRT_EN |
0676                     EMAC_INT_CTL_RX_EN);
0677             writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0678 
0679             db->emacrx_completed_flag = 1;
0680 
0681             return;
0682         }
0683 
0684         /* A packet ready now  & Get status/length */
0685         good_packet = true;
0686 
0687         rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG);
0688 
0689         if (netif_msg_rx_status(db))
0690             dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
0691 
0692         rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
0693         rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
0694 
0695         if (netif_msg_rx_status(db))
0696             dev_dbg(db->dev, "RX: status %02x, length %04x\n",
0697                 rxstatus, rxlen);
0698 
0699         /* Packet Status check */
0700         if (rxlen < 0x40) {
0701             good_packet = false;
0702             if (netif_msg_rx_err(db))
0703                 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
0704         }
0705 
0706         if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
0707             good_packet = false;
0708 
0709             if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
0710                 if (netif_msg_rx_err(db))
0711                     dev_dbg(db->dev, "crc error\n");
0712                 dev->stats.rx_crc_errors++;
0713             }
0714 
0715             if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
0716                 if (netif_msg_rx_err(db))
0717                     dev_dbg(db->dev, "length error\n");
0718                 dev->stats.rx_length_errors++;
0719             }
0720         }
0721 
0722         /* Move data from EMAC */
0723         if (good_packet) {
0724             skb = netdev_alloc_skb(dev, rxlen + 4);
0725             if (!skb)
0726                 continue;
0727             skb_reserve(skb, 2);
0728             rdptr = skb_put(skb, rxlen - 4);
0729 
0730             /* Read received packet from RX SRAM */
0731             if (netif_msg_rx_status(db))
0732                 dev_dbg(db->dev, "RxLen %x\n", rxlen);
0733 
0734             if (rxlen >= dev->mtu && db->rx_chan) {
0735                 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0736                 reg_val |= EMAC_RX_CTL_DMA_EN;
0737                 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
0738                 if (!emac_dma_inblk_32bit(db, skb, rdptr, rxlen))
0739                     break;
0740 
0741                 /* re enable cpu receive. then try to receive by emac_inblk_32bit */
0742                 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
0743                 reg_val &= ~EMAC_RX_CTL_DMA_EN;
0744                 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
0745             }
0746 
0747             emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
0748                     rdptr, rxlen);
0749             dev->stats.rx_bytes += rxlen;
0750 
0751             /* Pass to upper layer */
0752             skb->protocol = eth_type_trans(skb, dev);
0753             netif_rx(skb);
0754             dev->stats.rx_packets++;
0755         }
0756     }
0757 }
0758 
0759 static irqreturn_t emac_interrupt(int irq, void *dev_id)
0760 {
0761     struct net_device *dev = dev_id;
0762     struct emac_board_info *db = netdev_priv(dev);
0763     int int_status;
0764     unsigned int reg_val;
0765 
0766     /* A real interrupt coming */
0767 
0768     spin_lock(&db->lock);
0769 
0770     /* Disable all interrupts */
0771     writel(0, db->membase + EMAC_INT_CTL_REG);
0772 
0773     /* Got EMAC interrupt status */
0774     /* Got ISR */
0775     int_status = readl(db->membase + EMAC_INT_STA_REG);
0776     /* Clear ISR status */
0777     writel(int_status, db->membase + EMAC_INT_STA_REG);
0778 
0779     if (netif_msg_intr(db))
0780         dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
0781 
0782     /* Received the coming packet */
0783     if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
0784         /* carrier lost */
0785         db->emacrx_completed_flag = 0;
0786         emac_rx(dev);
0787     }
0788 
0789     /* Transmit Interrupt check */
0790     if (int_status & EMAC_INT_STA_TX_COMPLETE)
0791         emac_tx_done(dev, db, int_status);
0792 
0793     if (int_status & EMAC_INT_STA_TX_ABRT)
0794         netdev_info(dev, " ab : %x\n", int_status);
0795 
0796     /* Re-enable interrupt mask */
0797     if (db->emacrx_completed_flag == 1) {
0798         reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0799         reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN);
0800         writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0801     } else {
0802         reg_val = readl(db->membase + EMAC_INT_CTL_REG);
0803         reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN);
0804         writel(reg_val, db->membase + EMAC_INT_CTL_REG);
0805     }
0806 
0807     spin_unlock(&db->lock);
0808 
0809     return IRQ_HANDLED;
0810 }
0811 
0812 #ifdef CONFIG_NET_POLL_CONTROLLER
0813 /*
0814  * Used by netconsole
0815  */
0816 static void emac_poll_controller(struct net_device *dev)
0817 {
0818     disable_irq(dev->irq);
0819     emac_interrupt(dev->irq, dev);
0820     enable_irq(dev->irq);
0821 }
0822 #endif
0823 
0824 /*  Open the interface.
0825  *  The interface is opened whenever "ifconfig" actives it.
0826  */
0827 static int emac_open(struct net_device *dev)
0828 {
0829     struct emac_board_info *db = netdev_priv(dev);
0830     int ret;
0831 
0832     if (netif_msg_ifup(db))
0833         dev_dbg(db->dev, "enabling %s\n", dev->name);
0834 
0835     if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
0836         return -EAGAIN;
0837 
0838     /* Initialize EMAC board */
0839     emac_reset(db);
0840     emac_init_device(dev);
0841 
0842     ret = emac_mdio_probe(dev);
0843     if (ret < 0) {
0844         free_irq(dev->irq, dev);
0845         netdev_err(dev, "cannot probe MDIO bus\n");
0846         return ret;
0847     }
0848 
0849     phy_start(dev->phydev);
0850     netif_start_queue(dev);
0851 
0852     return 0;
0853 }
0854 
0855 static void emac_shutdown(struct net_device *dev)
0856 {
0857     unsigned int reg_val;
0858     struct emac_board_info *db = netdev_priv(dev);
0859 
0860     /* Disable all interrupt */
0861     writel(0, db->membase + EMAC_INT_CTL_REG);
0862 
0863     /* clear interrupt status */
0864     reg_val = readl(db->membase + EMAC_INT_STA_REG);
0865     writel(reg_val, db->membase + EMAC_INT_STA_REG);
0866 
0867     /* Disable RX/TX */
0868     reg_val = readl(db->membase + EMAC_CTL_REG);
0869     reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
0870     writel(reg_val, db->membase + EMAC_CTL_REG);
0871 }
0872 
0873 /* Stop the interface.
0874  * The interface is stopped when it is brought.
0875  */
0876 static int emac_stop(struct net_device *ndev)
0877 {
0878     struct emac_board_info *db = netdev_priv(ndev);
0879 
0880     if (netif_msg_ifdown(db))
0881         dev_dbg(db->dev, "shutting down %s\n", ndev->name);
0882 
0883     netif_stop_queue(ndev);
0884     netif_carrier_off(ndev);
0885 
0886     phy_stop(ndev->phydev);
0887 
0888     emac_mdio_remove(ndev);
0889 
0890     emac_shutdown(ndev);
0891 
0892     free_irq(ndev->irq, ndev);
0893 
0894     return 0;
0895 }
0896 
0897 static const struct net_device_ops emac_netdev_ops = {
0898     .ndo_open       = emac_open,
0899     .ndo_stop       = emac_stop,
0900     .ndo_start_xmit     = emac_start_xmit,
0901     .ndo_tx_timeout     = emac_timeout,
0902     .ndo_set_rx_mode    = emac_set_rx_mode,
0903     .ndo_eth_ioctl      = phy_do_ioctl_running,
0904     .ndo_validate_addr  = eth_validate_addr,
0905     .ndo_set_mac_address    = emac_set_mac_address,
0906 #ifdef CONFIG_NET_POLL_CONTROLLER
0907     .ndo_poll_controller    = emac_poll_controller,
0908 #endif
0909 };
0910 
0911 static int emac_configure_dma(struct emac_board_info *db)
0912 {
0913     struct platform_device *pdev = db->pdev;
0914     struct net_device *ndev = db->ndev;
0915     struct dma_slave_config conf = {};
0916     struct resource *regs;
0917     int err = 0;
0918 
0919     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0920     if (!regs) {
0921         netdev_err(ndev, "get io resource from device failed.\n");
0922         err = -ENOMEM;
0923         goto out_clear_chan;
0924     }
0925 
0926     netdev_info(ndev, "get io resource from device: %pa, size = %u\n",
0927             &regs->start, (unsigned int)resource_size(regs));
0928     db->emac_rx_fifo = regs->start + EMAC_RX_IO_DATA_REG;
0929 
0930     db->rx_chan = dma_request_chan(&pdev->dev, "rx");
0931     if (IS_ERR(db->rx_chan)) {
0932         netdev_err(ndev,
0933                "failed to request dma channel. dma is disabled\n");
0934         err = PTR_ERR(db->rx_chan);
0935         goto out_clear_chan;
0936     }
0937 
0938     conf.direction = DMA_DEV_TO_MEM;
0939     conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0940     conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0941     conf.src_addr = db->emac_rx_fifo;
0942     conf.dst_maxburst = 4;
0943     conf.src_maxburst = 4;
0944     conf.device_fc = false;
0945 
0946     err = dmaengine_slave_config(db->rx_chan, &conf);
0947     if (err) {
0948         netdev_err(ndev, "config dma slave failed\n");
0949         err = -EINVAL;
0950         goto out_slave_configure_err;
0951     }
0952 
0953     return err;
0954 
0955 out_slave_configure_err:
0956     dma_release_channel(db->rx_chan);
0957 
0958 out_clear_chan:
0959     db->rx_chan = NULL;
0960     return err;
0961 }
0962 
0963 /* Search EMAC board, allocate space and register it
0964  */
0965 static int emac_probe(struct platform_device *pdev)
0966 {
0967     struct device_node *np = pdev->dev.of_node;
0968     struct emac_board_info *db;
0969     struct net_device *ndev;
0970     int ret = 0;
0971 
0972     ndev = alloc_etherdev(sizeof(struct emac_board_info));
0973     if (!ndev) {
0974         dev_err(&pdev->dev, "could not allocate device.\n");
0975         return -ENOMEM;
0976     }
0977 
0978     SET_NETDEV_DEV(ndev, &pdev->dev);
0979 
0980     db = netdev_priv(ndev);
0981 
0982     db->dev = &pdev->dev;
0983     db->ndev = ndev;
0984     db->pdev = pdev;
0985     db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE);
0986 
0987     spin_lock_init(&db->lock);
0988 
0989     db->membase = of_iomap(np, 0);
0990     if (!db->membase) {
0991         dev_err(&pdev->dev, "failed to remap registers\n");
0992         ret = -ENOMEM;
0993         goto out;
0994     }
0995 
0996     /* fill in parameters for net-dev structure */
0997     ndev->base_addr = (unsigned long)db->membase;
0998     ndev->irq = irq_of_parse_and_map(np, 0);
0999     if (ndev->irq == -ENXIO) {
1000         netdev_err(ndev, "No irq resource\n");
1001         ret = ndev->irq;
1002         goto out_iounmap;
1003     }
1004 
1005     if (emac_configure_dma(db))
1006         netdev_info(ndev, "configure dma failed. disable dma.\n");
1007 
1008     db->clk = devm_clk_get(&pdev->dev, NULL);
1009     if (IS_ERR(db->clk)) {
1010         ret = PTR_ERR(db->clk);
1011         goto out_dispose_mapping;
1012     }
1013 
1014     ret = clk_prepare_enable(db->clk);
1015     if (ret) {
1016         dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret);
1017         goto out_dispose_mapping;
1018     }
1019 
1020     ret = sunxi_sram_claim(&pdev->dev);
1021     if (ret) {
1022         dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
1023         goto out_clk_disable_unprepare;
1024     }
1025 
1026     db->phy_node = of_parse_phandle(np, "phy-handle", 0);
1027     if (!db->phy_node)
1028         db->phy_node = of_parse_phandle(np, "phy", 0);
1029     if (!db->phy_node) {
1030         dev_err(&pdev->dev, "no associated PHY\n");
1031         ret = -ENODEV;
1032         goto out_release_sram;
1033     }
1034 
1035     /* Read MAC-address from DT */
1036     ret = of_get_ethdev_address(np, ndev);
1037     if (ret) {
1038         /* if the MAC address is invalid get a random one */
1039         eth_hw_addr_random(ndev);
1040         dev_warn(&pdev->dev, "using random MAC address %pM\n",
1041              ndev->dev_addr);
1042     }
1043 
1044     db->emacrx_completed_flag = 1;
1045     emac_powerup(ndev);
1046     emac_reset(db);
1047 
1048     ndev->netdev_ops = &emac_netdev_ops;
1049     ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1050     ndev->ethtool_ops = &emac_ethtool_ops;
1051 
1052     platform_set_drvdata(pdev, ndev);
1053 
1054     /* Carrier starts down, phylib will bring it up */
1055     netif_carrier_off(ndev);
1056 
1057     ret = register_netdev(ndev);
1058     if (ret) {
1059         dev_err(&pdev->dev, "Registering netdev failed!\n");
1060         ret = -ENODEV;
1061         goto out_release_sram;
1062     }
1063 
1064     dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
1065          ndev->name, db->membase, ndev->irq, ndev->dev_addr);
1066 
1067     return 0;
1068 
1069 out_release_sram:
1070     sunxi_sram_release(&pdev->dev);
1071 out_clk_disable_unprepare:
1072     clk_disable_unprepare(db->clk);
1073 out_dispose_mapping:
1074     irq_dispose_mapping(ndev->irq);
1075     dma_release_channel(db->rx_chan);
1076 out_iounmap:
1077     iounmap(db->membase);
1078 out:
1079     dev_err(db->dev, "not found (%d).\n", ret);
1080 
1081     free_netdev(ndev);
1082 
1083     return ret;
1084 }
1085 
1086 static int emac_remove(struct platform_device *pdev)
1087 {
1088     struct net_device *ndev = platform_get_drvdata(pdev);
1089     struct emac_board_info *db = netdev_priv(ndev);
1090 
1091     if (db->rx_chan) {
1092         dmaengine_terminate_all(db->rx_chan);
1093         dma_release_channel(db->rx_chan);
1094     }
1095 
1096     unregister_netdev(ndev);
1097     sunxi_sram_release(&pdev->dev);
1098     clk_disable_unprepare(db->clk);
1099     irq_dispose_mapping(ndev->irq);
1100     iounmap(db->membase);
1101     free_netdev(ndev);
1102 
1103     dev_dbg(&pdev->dev, "released and freed device\n");
1104     return 0;
1105 }
1106 
1107 static int emac_suspend(struct platform_device *dev, pm_message_t state)
1108 {
1109     struct net_device *ndev = platform_get_drvdata(dev);
1110 
1111     netif_carrier_off(ndev);
1112     netif_device_detach(ndev);
1113     emac_shutdown(ndev);
1114 
1115     return 0;
1116 }
1117 
1118 static int emac_resume(struct platform_device *dev)
1119 {
1120     struct net_device *ndev = platform_get_drvdata(dev);
1121     struct emac_board_info *db = netdev_priv(ndev);
1122 
1123     emac_reset(db);
1124     emac_init_device(ndev);
1125     netif_device_attach(ndev);
1126 
1127     return 0;
1128 }
1129 
1130 static const struct of_device_id emac_of_match[] = {
1131     {.compatible = "allwinner,sun4i-a10-emac",},
1132 
1133     /* Deprecated */
1134     {.compatible = "allwinner,sun4i-emac",},
1135     {},
1136 };
1137 
1138 MODULE_DEVICE_TABLE(of, emac_of_match);
1139 
1140 static struct platform_driver emac_driver = {
1141     .driver = {
1142         .name = "sun4i-emac",
1143         .of_match_table = emac_of_match,
1144     },
1145     .probe = emac_probe,
1146     .remove = emac_remove,
1147     .suspend = emac_suspend,
1148     .resume = emac_resume,
1149 };
1150 
1151 module_platform_driver(emac_driver);
1152 
1153 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
1154 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1155 MODULE_DESCRIPTION("Allwinner A10 emac network driver");
1156 MODULE_LICENSE("GPL");
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