Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Gigabit Ethernet adapters based on the Session Layer
0004  * Interface (SLIC) technology by Alacritech. The driver does not
0005  * support the hardware acceleration features provided by these cards.
0006  *
0007  * Copyright (C) 2016 Lino Sanfilippo <LinoSanfilippo@gmx.de>
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/pci.h>
0013 #include <linux/netdevice.h>
0014 #include <linux/etherdevice.h>
0015 #include <linux/if_ether.h>
0016 #include <linux/crc32.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/ethtool.h>
0019 #include <linux/mii.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/delay.h>
0022 #include <linux/firmware.h>
0023 #include <linux/list.h>
0024 #include <linux/u64_stats_sync.h>
0025 
0026 #include "slic.h"
0027 
0028 #define DRV_NAME            "slicoss"
0029 
0030 static const struct pci_device_id slic_id_tbl[] = {
0031     { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH,
0032              PCI_DEVICE_ID_ALACRITECH_MOJAVE) },
0033     { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH,
0034              PCI_DEVICE_ID_ALACRITECH_OASIS) },
0035     { 0 }
0036 };
0037 
0038 static const char slic_stats_strings[][ETH_GSTRING_LEN] = {
0039     "rx_packets",
0040     "rx_bytes",
0041     "rx_multicasts",
0042     "rx_errors",
0043     "rx_buff_miss",
0044     "rx_tp_csum",
0045     "rx_tp_oflow",
0046     "rx_tp_hlen",
0047     "rx_ip_csum",
0048     "rx_ip_len",
0049     "rx_ip_hdr_len",
0050     "rx_early",
0051     "rx_buff_oflow",
0052     "rx_lcode",
0053     "rx_drbl",
0054     "rx_crc",
0055     "rx_oflow_802",
0056     "rx_uflow_802",
0057     "tx_packets",
0058     "tx_bytes",
0059     "tx_carrier",
0060     "tx_dropped",
0061     "irq_errs",
0062 };
0063 
0064 static inline int slic_next_queue_idx(unsigned int idx, unsigned int qlen)
0065 {
0066     return (idx + 1) & (qlen - 1);
0067 }
0068 
0069 static inline int slic_get_free_queue_descs(unsigned int put_idx,
0070                         unsigned int done_idx,
0071                         unsigned int qlen)
0072 {
0073     if (put_idx >= done_idx)
0074         return (qlen - (put_idx - done_idx) - 1);
0075     return (done_idx - put_idx - 1);
0076 }
0077 
0078 static unsigned int slic_next_compl_idx(struct slic_device *sdev)
0079 {
0080     struct slic_stat_queue *stq = &sdev->stq;
0081     unsigned int active = stq->active_array;
0082     struct slic_stat_desc *descs;
0083     struct slic_stat_desc *stat;
0084     unsigned int idx;
0085 
0086     descs = stq->descs[active];
0087     stat = &descs[stq->done_idx];
0088 
0089     if (!stat->status)
0090         return SLIC_INVALID_STAT_DESC_IDX;
0091 
0092     idx = (le32_to_cpu(stat->hnd) & 0xffff) - 1;
0093     /* reset desc */
0094     stat->hnd = 0;
0095     stat->status = 0;
0096 
0097     stq->done_idx = slic_next_queue_idx(stq->done_idx, stq->len);
0098     /* check for wraparound */
0099     if (!stq->done_idx) {
0100         dma_addr_t paddr = stq->paddr[active];
0101 
0102         slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
0103                         stq->len);
0104         /* make sure new status descriptors are immediately available */
0105         slic_flush_write(sdev);
0106         active++;
0107         active &= (SLIC_NUM_STAT_DESC_ARRAYS - 1);
0108         stq->active_array = active;
0109     }
0110     return idx;
0111 }
0112 
0113 static unsigned int slic_get_free_tx_descs(struct slic_tx_queue *txq)
0114 {
0115     /* ensure tail idx is updated */
0116     smp_mb();
0117     return slic_get_free_queue_descs(txq->put_idx, txq->done_idx, txq->len);
0118 }
0119 
0120 static unsigned int slic_get_free_rx_descs(struct slic_rx_queue *rxq)
0121 {
0122     return slic_get_free_queue_descs(rxq->put_idx, rxq->done_idx, rxq->len);
0123 }
0124 
0125 static void slic_clear_upr_list(struct slic_upr_list *upr_list)
0126 {
0127     struct slic_upr *upr;
0128     struct slic_upr *tmp;
0129 
0130     spin_lock_bh(&upr_list->lock);
0131     list_for_each_entry_safe(upr, tmp, &upr_list->list, list) {
0132         list_del(&upr->list);
0133         kfree(upr);
0134     }
0135     upr_list->pending = false;
0136     spin_unlock_bh(&upr_list->lock);
0137 }
0138 
0139 static void slic_start_upr(struct slic_device *sdev, struct slic_upr *upr)
0140 {
0141     u32 reg;
0142 
0143     reg = (upr->type == SLIC_UPR_CONFIG) ? SLIC_REG_RCONFIG :
0144                            SLIC_REG_LSTAT;
0145     slic_write(sdev, reg, lower_32_bits(upr->paddr));
0146     slic_flush_write(sdev);
0147 }
0148 
0149 static void slic_queue_upr(struct slic_device *sdev, struct slic_upr *upr)
0150 {
0151     struct slic_upr_list *upr_list = &sdev->upr_list;
0152     bool pending;
0153 
0154     spin_lock_bh(&upr_list->lock);
0155     pending = upr_list->pending;
0156     INIT_LIST_HEAD(&upr->list);
0157     list_add_tail(&upr->list, &upr_list->list);
0158     upr_list->pending = true;
0159     spin_unlock_bh(&upr_list->lock);
0160 
0161     if (!pending)
0162         slic_start_upr(sdev, upr);
0163 }
0164 
0165 static struct slic_upr *slic_dequeue_upr(struct slic_device *sdev)
0166 {
0167     struct slic_upr_list *upr_list = &sdev->upr_list;
0168     struct slic_upr *next_upr = NULL;
0169     struct slic_upr *upr = NULL;
0170 
0171     spin_lock_bh(&upr_list->lock);
0172     if (!list_empty(&upr_list->list)) {
0173         upr = list_first_entry(&upr_list->list, struct slic_upr, list);
0174         list_del(&upr->list);
0175 
0176         if (list_empty(&upr_list->list))
0177             upr_list->pending = false;
0178         else
0179             next_upr = list_first_entry(&upr_list->list,
0180                             struct slic_upr, list);
0181     }
0182     spin_unlock_bh(&upr_list->lock);
0183     /* trigger processing of the next upr in list */
0184     if (next_upr)
0185         slic_start_upr(sdev, next_upr);
0186 
0187     return upr;
0188 }
0189 
0190 static int slic_new_upr(struct slic_device *sdev, unsigned int type,
0191             dma_addr_t paddr)
0192 {
0193     struct slic_upr *upr;
0194 
0195     upr = kmalloc(sizeof(*upr), GFP_ATOMIC);
0196     if (!upr)
0197         return -ENOMEM;
0198     upr->type = type;
0199     upr->paddr = paddr;
0200 
0201     slic_queue_upr(sdev, upr);
0202 
0203     return 0;
0204 }
0205 
0206 static void slic_set_mcast_bit(u64 *mcmask, unsigned char const *addr)
0207 {
0208     u64 mask = *mcmask;
0209     u8 crc;
0210     /* Get the CRC polynomial for the mac address: we use bits 1-8 (lsb),
0211      * bitwise reversed, msb (= lsb bit 0 before bitrev) is automatically
0212      * discarded.
0213      */
0214     crc = ether_crc(ETH_ALEN, addr) >> 23;
0215      /* we only have space on the SLIC for 64 entries */
0216     crc &= 0x3F;
0217     mask |= (u64)1 << crc;
0218     *mcmask = mask;
0219 }
0220 
0221 /* must be called with link_lock held */
0222 static void slic_configure_rcv(struct slic_device *sdev)
0223 {
0224     u32 val;
0225 
0226     val = SLIC_GRCR_RESET | SLIC_GRCR_ADDRAEN | SLIC_GRCR_RCVEN |
0227           SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT | SLIC_GRCR_RCVBAD;
0228 
0229     if (sdev->duplex == DUPLEX_FULL)
0230         val |= SLIC_GRCR_CTLEN;
0231 
0232     if (sdev->promisc)
0233         val |= SLIC_GRCR_RCVALL;
0234 
0235     slic_write(sdev, SLIC_REG_WRCFG, val);
0236 }
0237 
0238 /* must be called with link_lock held */
0239 static void slic_configure_xmt(struct slic_device *sdev)
0240 {
0241     u32 val;
0242 
0243     val = SLIC_GXCR_RESET | SLIC_GXCR_XMTEN;
0244 
0245     if (sdev->duplex == DUPLEX_FULL)
0246         val |= SLIC_GXCR_PAUSEEN;
0247 
0248     slic_write(sdev, SLIC_REG_WXCFG, val);
0249 }
0250 
0251 /* must be called with link_lock held */
0252 static void slic_configure_mac(struct slic_device *sdev)
0253 {
0254     u32 val;
0255 
0256     if (sdev->speed == SPEED_1000) {
0257         val = SLIC_GMCR_GAPBB_1000 << SLIC_GMCR_GAPBB_SHIFT |
0258               SLIC_GMCR_GAPR1_1000 << SLIC_GMCR_GAPR1_SHIFT |
0259               SLIC_GMCR_GAPR2_1000 << SLIC_GMCR_GAPR2_SHIFT |
0260               SLIC_GMCR_GBIT; /* enable GMII */
0261     } else {
0262         val = SLIC_GMCR_GAPBB_100 << SLIC_GMCR_GAPBB_SHIFT |
0263               SLIC_GMCR_GAPR1_100 << SLIC_GMCR_GAPR1_SHIFT |
0264               SLIC_GMCR_GAPR2_100 << SLIC_GMCR_GAPR2_SHIFT;
0265     }
0266 
0267     if (sdev->duplex == DUPLEX_FULL)
0268         val |= SLIC_GMCR_FULLD;
0269 
0270     slic_write(sdev, SLIC_REG_WMCFG, val);
0271 }
0272 
0273 static void slic_configure_link_locked(struct slic_device *sdev, int speed,
0274                        unsigned int duplex)
0275 {
0276     struct net_device *dev = sdev->netdev;
0277 
0278     if (sdev->speed == speed && sdev->duplex == duplex)
0279         return;
0280 
0281     sdev->speed = speed;
0282     sdev->duplex = duplex;
0283 
0284     if (sdev->speed == SPEED_UNKNOWN) {
0285         if (netif_carrier_ok(dev))
0286             netif_carrier_off(dev);
0287     } else {
0288         /* (re)configure link settings */
0289         slic_configure_mac(sdev);
0290         slic_configure_xmt(sdev);
0291         slic_configure_rcv(sdev);
0292         slic_flush_write(sdev);
0293 
0294         if (!netif_carrier_ok(dev))
0295             netif_carrier_on(dev);
0296     }
0297 }
0298 
0299 static void slic_configure_link(struct slic_device *sdev, int speed,
0300                 unsigned int duplex)
0301 {
0302     spin_lock_bh(&sdev->link_lock);
0303     slic_configure_link_locked(sdev, speed, duplex);
0304     spin_unlock_bh(&sdev->link_lock);
0305 }
0306 
0307 static void slic_set_rx_mode(struct net_device *dev)
0308 {
0309     struct slic_device *sdev = netdev_priv(dev);
0310     struct netdev_hw_addr *hwaddr;
0311     bool set_promisc;
0312     u64 mcmask;
0313 
0314     if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
0315         /* Turn on all multicast addresses. We have to do this for
0316          * promiscuous mode as well as ALLMCAST mode (it saves the
0317          * microcode from having to keep state about the MAC
0318          * configuration).
0319          */
0320         mcmask = ~(u64)0;
0321     } else  {
0322         mcmask = 0;
0323 
0324         netdev_for_each_mc_addr(hwaddr, dev) {
0325             slic_set_mcast_bit(&mcmask, hwaddr->addr);
0326         }
0327     }
0328 
0329     slic_write(sdev, SLIC_REG_MCASTLOW, lower_32_bits(mcmask));
0330     slic_write(sdev, SLIC_REG_MCASTHIGH, upper_32_bits(mcmask));
0331 
0332     set_promisc = !!(dev->flags & IFF_PROMISC);
0333 
0334     spin_lock_bh(&sdev->link_lock);
0335     if (sdev->promisc != set_promisc) {
0336         sdev->promisc = set_promisc;
0337         slic_configure_rcv(sdev);
0338     }
0339     spin_unlock_bh(&sdev->link_lock);
0340 }
0341 
0342 static void slic_xmit_complete(struct slic_device *sdev)
0343 {
0344     struct slic_tx_queue *txq = &sdev->txq;
0345     struct net_device *dev = sdev->netdev;
0346     struct slic_tx_buffer *buff;
0347     unsigned int frames = 0;
0348     unsigned int bytes = 0;
0349     unsigned int idx;
0350 
0351     /* Limit processing to SLIC_MAX_TX_COMPLETIONS frames to avoid that new
0352      * completions during processing keeps the loop running endlessly.
0353      */
0354     do {
0355         idx = slic_next_compl_idx(sdev);
0356         if (idx == SLIC_INVALID_STAT_DESC_IDX)
0357             break;
0358 
0359         txq->done_idx = idx;
0360         buff = &txq->txbuffs[idx];
0361 
0362         if (unlikely(!buff->skb)) {
0363             netdev_warn(dev,
0364                     "no skb found for desc idx %i\n", idx);
0365             continue;
0366         }
0367         dma_unmap_single(&sdev->pdev->dev,
0368                  dma_unmap_addr(buff, map_addr),
0369                  dma_unmap_len(buff, map_len), DMA_TO_DEVICE);
0370 
0371         bytes += buff->skb->len;
0372         frames++;
0373 
0374         dev_kfree_skb_any(buff->skb);
0375         buff->skb = NULL;
0376     } while (frames < SLIC_MAX_TX_COMPLETIONS);
0377     /* make sure xmit sees the new value for done_idx */
0378     smp_wmb();
0379 
0380     u64_stats_update_begin(&sdev->stats.syncp);
0381     sdev->stats.tx_bytes += bytes;
0382     sdev->stats.tx_packets += frames;
0383     u64_stats_update_end(&sdev->stats.syncp);
0384 
0385     netif_tx_lock(dev);
0386     if (netif_queue_stopped(dev) &&
0387         (slic_get_free_tx_descs(txq) >= SLIC_MIN_TX_WAKEUP_DESCS))
0388         netif_wake_queue(dev);
0389     netif_tx_unlock(dev);
0390 }
0391 
0392 static void slic_refill_rx_queue(struct slic_device *sdev, gfp_t gfp)
0393 {
0394     const unsigned int ALIGN_MASK = SLIC_RX_BUFF_ALIGN - 1;
0395     unsigned int maplen = SLIC_RX_BUFF_SIZE;
0396     struct slic_rx_queue *rxq = &sdev->rxq;
0397     struct net_device *dev = sdev->netdev;
0398     struct slic_rx_buffer *buff;
0399     struct slic_rx_desc *desc;
0400     unsigned int misalign;
0401     unsigned int offset;
0402     struct sk_buff *skb;
0403     dma_addr_t paddr;
0404 
0405     while (slic_get_free_rx_descs(rxq) > SLIC_MAX_REQ_RX_DESCS) {
0406         skb = alloc_skb(maplen + ALIGN_MASK, gfp);
0407         if (!skb)
0408             break;
0409 
0410         paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen,
0411                        DMA_FROM_DEVICE);
0412         if (dma_mapping_error(&sdev->pdev->dev, paddr)) {
0413             netdev_err(dev, "mapping rx packet failed\n");
0414             /* drop skb */
0415             dev_kfree_skb_any(skb);
0416             break;
0417         }
0418         /* ensure head buffer descriptors are 256 byte aligned */
0419         offset = 0;
0420         misalign = paddr & ALIGN_MASK;
0421         if (misalign) {
0422             offset = SLIC_RX_BUFF_ALIGN - misalign;
0423             skb_reserve(skb, offset);
0424         }
0425         /* the HW expects dma chunks for descriptor + frame data */
0426         desc = (struct slic_rx_desc *)skb->data;
0427         /* temporarily sync descriptor for CPU to clear status */
0428         dma_sync_single_for_cpu(&sdev->pdev->dev, paddr,
0429                     offset + sizeof(*desc),
0430                     DMA_FROM_DEVICE);
0431         desc->status = 0;
0432         /* return it to HW again */
0433         dma_sync_single_for_device(&sdev->pdev->dev, paddr,
0434                        offset + sizeof(*desc),
0435                        DMA_FROM_DEVICE);
0436 
0437         buff = &rxq->rxbuffs[rxq->put_idx];
0438         buff->skb = skb;
0439         dma_unmap_addr_set(buff, map_addr, paddr);
0440         dma_unmap_len_set(buff, map_len, maplen);
0441         buff->addr_offset = offset;
0442         /* complete write to descriptor before it is handed to HW */
0443         wmb();
0444         /* head buffer descriptors are placed immediately before skb */
0445         slic_write(sdev, SLIC_REG_HBAR, lower_32_bits(paddr) + offset);
0446         rxq->put_idx = slic_next_queue_idx(rxq->put_idx, rxq->len);
0447     }
0448 }
0449 
0450 static void slic_handle_frame_error(struct slic_device *sdev,
0451                     struct sk_buff *skb)
0452 {
0453     struct slic_stats *stats = &sdev->stats;
0454 
0455     if (sdev->model == SLIC_MODEL_OASIS) {
0456         struct slic_rx_info_oasis *info;
0457         u32 status_b;
0458         u32 status;
0459 
0460         info = (struct slic_rx_info_oasis *)skb->data;
0461         status = le32_to_cpu(info->frame_status);
0462         status_b = le32_to_cpu(info->frame_status_b);
0463         /* transport layer */
0464         if (status_b & SLIC_VRHSTATB_TPCSUM)
0465             SLIC_INC_STATS_COUNTER(stats, rx_tpcsum);
0466         if (status & SLIC_VRHSTAT_TPOFLO)
0467             SLIC_INC_STATS_COUNTER(stats, rx_tpoflow);
0468         if (status_b & SLIC_VRHSTATB_TPHLEN)
0469             SLIC_INC_STATS_COUNTER(stats, rx_tphlen);
0470         /* ip layer */
0471         if (status_b & SLIC_VRHSTATB_IPCSUM)
0472             SLIC_INC_STATS_COUNTER(stats, rx_ipcsum);
0473         if (status_b & SLIC_VRHSTATB_IPLERR)
0474             SLIC_INC_STATS_COUNTER(stats, rx_iplen);
0475         if (status_b & SLIC_VRHSTATB_IPHERR)
0476             SLIC_INC_STATS_COUNTER(stats, rx_iphlen);
0477         /* link layer */
0478         if (status_b & SLIC_VRHSTATB_RCVE)
0479             SLIC_INC_STATS_COUNTER(stats, rx_early);
0480         if (status_b & SLIC_VRHSTATB_BUFF)
0481             SLIC_INC_STATS_COUNTER(stats, rx_buffoflow);
0482         if (status_b & SLIC_VRHSTATB_CODE)
0483             SLIC_INC_STATS_COUNTER(stats, rx_lcode);
0484         if (status_b & SLIC_VRHSTATB_DRBL)
0485             SLIC_INC_STATS_COUNTER(stats, rx_drbl);
0486         if (status_b & SLIC_VRHSTATB_CRC)
0487             SLIC_INC_STATS_COUNTER(stats, rx_crc);
0488         if (status & SLIC_VRHSTAT_802OE)
0489             SLIC_INC_STATS_COUNTER(stats, rx_oflow802);
0490         if (status_b & SLIC_VRHSTATB_802UE)
0491             SLIC_INC_STATS_COUNTER(stats, rx_uflow802);
0492         if (status_b & SLIC_VRHSTATB_CARRE)
0493             SLIC_INC_STATS_COUNTER(stats, tx_carrier);
0494     } else { /* mojave */
0495         struct slic_rx_info_mojave *info;
0496         u32 status;
0497 
0498         info = (struct slic_rx_info_mojave *)skb->data;
0499         status = le32_to_cpu(info->frame_status);
0500         /* transport layer */
0501         if (status & SLIC_VGBSTAT_XPERR) {
0502             u32 xerr = status >> SLIC_VGBSTAT_XERRSHFT;
0503 
0504             if (xerr == SLIC_VGBSTAT_XCSERR)
0505                 SLIC_INC_STATS_COUNTER(stats, rx_tpcsum);
0506             if (xerr == SLIC_VGBSTAT_XUFLOW)
0507                 SLIC_INC_STATS_COUNTER(stats, rx_tpoflow);
0508             if (xerr == SLIC_VGBSTAT_XHLEN)
0509                 SLIC_INC_STATS_COUNTER(stats, rx_tphlen);
0510         }
0511         /* ip layer */
0512         if (status & SLIC_VGBSTAT_NETERR) {
0513             u32 nerr = status >> SLIC_VGBSTAT_NERRSHFT &
0514                    SLIC_VGBSTAT_NERRMSK;
0515 
0516             if (nerr == SLIC_VGBSTAT_NCSERR)
0517                 SLIC_INC_STATS_COUNTER(stats, rx_ipcsum);
0518             if (nerr == SLIC_VGBSTAT_NUFLOW)
0519                 SLIC_INC_STATS_COUNTER(stats, rx_iplen);
0520             if (nerr == SLIC_VGBSTAT_NHLEN)
0521                 SLIC_INC_STATS_COUNTER(stats, rx_iphlen);
0522         }
0523         /* link layer */
0524         if (status & SLIC_VGBSTAT_LNKERR) {
0525             u32 lerr = status & SLIC_VGBSTAT_LERRMSK;
0526 
0527             if (lerr == SLIC_VGBSTAT_LDEARLY)
0528                 SLIC_INC_STATS_COUNTER(stats, rx_early);
0529             if (lerr == SLIC_VGBSTAT_LBOFLO)
0530                 SLIC_INC_STATS_COUNTER(stats, rx_buffoflow);
0531             if (lerr == SLIC_VGBSTAT_LCODERR)
0532                 SLIC_INC_STATS_COUNTER(stats, rx_lcode);
0533             if (lerr == SLIC_VGBSTAT_LDBLNBL)
0534                 SLIC_INC_STATS_COUNTER(stats, rx_drbl);
0535             if (lerr == SLIC_VGBSTAT_LCRCERR)
0536                 SLIC_INC_STATS_COUNTER(stats, rx_crc);
0537             if (lerr == SLIC_VGBSTAT_LOFLO)
0538                 SLIC_INC_STATS_COUNTER(stats, rx_oflow802);
0539             if (lerr == SLIC_VGBSTAT_LUFLO)
0540                 SLIC_INC_STATS_COUNTER(stats, rx_uflow802);
0541         }
0542     }
0543     SLIC_INC_STATS_COUNTER(stats, rx_errors);
0544 }
0545 
0546 static void slic_handle_receive(struct slic_device *sdev, unsigned int todo,
0547                 unsigned int *done)
0548 {
0549     struct slic_rx_queue *rxq = &sdev->rxq;
0550     struct net_device *dev = sdev->netdev;
0551     struct slic_rx_buffer *buff;
0552     struct slic_rx_desc *desc;
0553     unsigned int frames = 0;
0554     unsigned int bytes = 0;
0555     struct sk_buff *skb;
0556     u32 status;
0557     u32 len;
0558 
0559     while (todo && (rxq->done_idx != rxq->put_idx)) {
0560         buff = &rxq->rxbuffs[rxq->done_idx];
0561 
0562         skb = buff->skb;
0563         if (!skb)
0564             break;
0565 
0566         desc = (struct slic_rx_desc *)skb->data;
0567 
0568         dma_sync_single_for_cpu(&sdev->pdev->dev,
0569                     dma_unmap_addr(buff, map_addr),
0570                     buff->addr_offset + sizeof(*desc),
0571                     DMA_FROM_DEVICE);
0572 
0573         status = le32_to_cpu(desc->status);
0574         if (!(status & SLIC_IRHDDR_SVALID)) {
0575             dma_sync_single_for_device(&sdev->pdev->dev,
0576                            dma_unmap_addr(buff,
0577                                   map_addr),
0578                            buff->addr_offset +
0579                            sizeof(*desc),
0580                            DMA_FROM_DEVICE);
0581             break;
0582         }
0583 
0584         buff->skb = NULL;
0585 
0586         dma_unmap_single(&sdev->pdev->dev,
0587                  dma_unmap_addr(buff, map_addr),
0588                  dma_unmap_len(buff, map_len),
0589                  DMA_FROM_DEVICE);
0590 
0591         /* skip rx descriptor that is placed before the frame data */
0592         skb_reserve(skb, SLIC_RX_BUFF_HDR_SIZE);
0593 
0594         if (unlikely(status & SLIC_IRHDDR_ERR)) {
0595             slic_handle_frame_error(sdev, skb);
0596             dev_kfree_skb_any(skb);
0597         } else {
0598             struct ethhdr *eh = (struct ethhdr *)skb->data;
0599 
0600             if (is_multicast_ether_addr(eh->h_dest))
0601                 SLIC_INC_STATS_COUNTER(&sdev->stats, rx_mcasts);
0602 
0603             len = le32_to_cpu(desc->length) & SLIC_IRHDDR_FLEN_MSK;
0604             skb_put(skb, len);
0605             skb->protocol = eth_type_trans(skb, dev);
0606             skb->ip_summed = CHECKSUM_UNNECESSARY;
0607 
0608             napi_gro_receive(&sdev->napi, skb);
0609 
0610             bytes += len;
0611             frames++;
0612         }
0613         rxq->done_idx = slic_next_queue_idx(rxq->done_idx, rxq->len);
0614         todo--;
0615     }
0616 
0617     u64_stats_update_begin(&sdev->stats.syncp);
0618     sdev->stats.rx_bytes += bytes;
0619     sdev->stats.rx_packets += frames;
0620     u64_stats_update_end(&sdev->stats.syncp);
0621 
0622     slic_refill_rx_queue(sdev, GFP_ATOMIC);
0623 }
0624 
0625 static void slic_handle_link_irq(struct slic_device *sdev)
0626 {
0627     struct slic_shmem *sm = &sdev->shmem;
0628     struct slic_shmem_data *sm_data = sm->shmem_data;
0629     unsigned int duplex;
0630     int speed;
0631     u32 link;
0632 
0633     link = le32_to_cpu(sm_data->link);
0634 
0635     if (link & SLIC_GIG_LINKUP) {
0636         if (link & SLIC_GIG_SPEED_1000)
0637             speed = SPEED_1000;
0638         else if (link & SLIC_GIG_SPEED_100)
0639             speed = SPEED_100;
0640         else
0641             speed = SPEED_10;
0642 
0643         duplex = (link & SLIC_GIG_FULLDUPLEX) ? DUPLEX_FULL :
0644                             DUPLEX_HALF;
0645     } else {
0646         duplex = DUPLEX_UNKNOWN;
0647         speed = SPEED_UNKNOWN;
0648     }
0649     slic_configure_link(sdev, speed, duplex);
0650 }
0651 
0652 static void slic_handle_upr_irq(struct slic_device *sdev, u32 irqs)
0653 {
0654     struct slic_upr *upr;
0655 
0656     /* remove upr that caused this irq (always the first entry in list) */
0657     upr = slic_dequeue_upr(sdev);
0658     if (!upr) {
0659         netdev_warn(sdev->netdev, "no upr found on list\n");
0660         return;
0661     }
0662 
0663     if (upr->type == SLIC_UPR_LSTAT) {
0664         if (unlikely(irqs & SLIC_ISR_UPCERR_MASK)) {
0665             /* try again */
0666             slic_queue_upr(sdev, upr);
0667             return;
0668         }
0669         slic_handle_link_irq(sdev);
0670     }
0671     kfree(upr);
0672 }
0673 
0674 static int slic_handle_link_change(struct slic_device *sdev)
0675 {
0676     return slic_new_upr(sdev, SLIC_UPR_LSTAT, sdev->shmem.link_paddr);
0677 }
0678 
0679 static void slic_handle_err_irq(struct slic_device *sdev, u32 isr)
0680 {
0681     struct slic_stats *stats = &sdev->stats;
0682 
0683     if (isr & SLIC_ISR_RMISS)
0684         SLIC_INC_STATS_COUNTER(stats, rx_buff_miss);
0685     if (isr & SLIC_ISR_XDROP)
0686         SLIC_INC_STATS_COUNTER(stats, tx_dropped);
0687     if (!(isr & (SLIC_ISR_RMISS | SLIC_ISR_XDROP)))
0688         SLIC_INC_STATS_COUNTER(stats, irq_errs);
0689 }
0690 
0691 static void slic_handle_irq(struct slic_device *sdev, u32 isr,
0692                 unsigned int todo, unsigned int *done)
0693 {
0694     if (isr & SLIC_ISR_ERR)
0695         slic_handle_err_irq(sdev, isr);
0696 
0697     if (isr & SLIC_ISR_LEVENT)
0698         slic_handle_link_change(sdev);
0699 
0700     if (isr & SLIC_ISR_UPC_MASK)
0701         slic_handle_upr_irq(sdev, isr);
0702 
0703     if (isr & SLIC_ISR_RCV)
0704         slic_handle_receive(sdev, todo, done);
0705 
0706     if (isr & SLIC_ISR_CMD)
0707         slic_xmit_complete(sdev);
0708 }
0709 
0710 static int slic_poll(struct napi_struct *napi, int todo)
0711 {
0712     struct slic_device *sdev = container_of(napi, struct slic_device, napi);
0713     struct slic_shmem *sm = &sdev->shmem;
0714     struct slic_shmem_data *sm_data = sm->shmem_data;
0715     u32 isr = le32_to_cpu(sm_data->isr);
0716     int done = 0;
0717 
0718     slic_handle_irq(sdev, isr, todo, &done);
0719 
0720     if (done < todo) {
0721         napi_complete_done(napi, done);
0722         /* reenable irqs */
0723         sm_data->isr = 0;
0724         /* make sure sm_data->isr is cleard before irqs are reenabled */
0725         wmb();
0726         slic_write(sdev, SLIC_REG_ISR, 0);
0727         slic_flush_write(sdev);
0728     }
0729 
0730     return done;
0731 }
0732 
0733 static irqreturn_t slic_irq(int irq, void *dev_id)
0734 {
0735     struct slic_device *sdev = dev_id;
0736     struct slic_shmem *sm = &sdev->shmem;
0737     struct slic_shmem_data *sm_data = sm->shmem_data;
0738 
0739     slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_MASK);
0740     slic_flush_write(sdev);
0741     /* make sure sm_data->isr is read after ICR_INT_MASK is set */
0742     wmb();
0743 
0744     if (!sm_data->isr) {
0745         dma_rmb();
0746         /* spurious interrupt */
0747         slic_write(sdev, SLIC_REG_ISR, 0);
0748         slic_flush_write(sdev);
0749         return IRQ_NONE;
0750     }
0751 
0752     napi_schedule_irqoff(&sdev->napi);
0753 
0754     return IRQ_HANDLED;
0755 }
0756 
0757 static void slic_card_reset(struct slic_device *sdev)
0758 {
0759     u16 cmd;
0760 
0761     slic_write(sdev, SLIC_REG_RESET, SLIC_RESET_MAGIC);
0762     /* flush write by means of config space */
0763     pci_read_config_word(sdev->pdev, PCI_COMMAND, &cmd);
0764     mdelay(1);
0765 }
0766 
0767 static int slic_init_stat_queue(struct slic_device *sdev)
0768 {
0769     const unsigned int DESC_ALIGN_MASK = SLIC_STATS_DESC_ALIGN - 1;
0770     struct slic_stat_queue *stq = &sdev->stq;
0771     struct slic_stat_desc *descs;
0772     unsigned int misalign;
0773     unsigned int offset;
0774     dma_addr_t paddr;
0775     size_t size;
0776     int err;
0777     int i;
0778 
0779     stq->len = SLIC_NUM_STAT_DESCS;
0780     stq->active_array = 0;
0781     stq->done_idx = 0;
0782 
0783     size = stq->len * sizeof(*descs) + DESC_ALIGN_MASK;
0784 
0785     for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) {
0786         descs = dma_alloc_coherent(&sdev->pdev->dev, size, &paddr,
0787                        GFP_KERNEL);
0788         if (!descs) {
0789             netdev_err(sdev->netdev,
0790                    "failed to allocate status descriptors\n");
0791             err = -ENOMEM;
0792             goto free_descs;
0793         }
0794         /* ensure correct alignment */
0795         offset = 0;
0796         misalign = paddr & DESC_ALIGN_MASK;
0797         if (misalign) {
0798             offset = SLIC_STATS_DESC_ALIGN - misalign;
0799             descs += offset;
0800             paddr += offset;
0801         }
0802 
0803         slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
0804                         stq->len);
0805         stq->descs[i] = descs;
0806         stq->paddr[i] = paddr;
0807         stq->addr_offset[i] = offset;
0808     }
0809 
0810     stq->mem_size = size;
0811 
0812     return 0;
0813 
0814 free_descs:
0815     while (i--) {
0816         dma_free_coherent(&sdev->pdev->dev, stq->mem_size,
0817                   stq->descs[i] - stq->addr_offset[i],
0818                   stq->paddr[i] - stq->addr_offset[i]);
0819     }
0820 
0821     return err;
0822 }
0823 
0824 static void slic_free_stat_queue(struct slic_device *sdev)
0825 {
0826     struct slic_stat_queue *stq = &sdev->stq;
0827     int i;
0828 
0829     for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) {
0830         dma_free_coherent(&sdev->pdev->dev, stq->mem_size,
0831                   stq->descs[i] - stq->addr_offset[i],
0832                   stq->paddr[i] - stq->addr_offset[i]);
0833     }
0834 }
0835 
0836 static int slic_init_tx_queue(struct slic_device *sdev)
0837 {
0838     struct slic_tx_queue *txq = &sdev->txq;
0839     struct slic_tx_buffer *buff;
0840     struct slic_tx_desc *desc;
0841     unsigned int i;
0842     int err;
0843 
0844     txq->len = SLIC_NUM_TX_DESCS;
0845     txq->put_idx = 0;
0846     txq->done_idx = 0;
0847 
0848     txq->txbuffs = kcalloc(txq->len, sizeof(*buff), GFP_KERNEL);
0849     if (!txq->txbuffs)
0850         return -ENOMEM;
0851 
0852     txq->dma_pool = dma_pool_create("slic_pool", &sdev->pdev->dev,
0853                     sizeof(*desc), SLIC_TX_DESC_ALIGN,
0854                     4096);
0855     if (!txq->dma_pool) {
0856         err = -ENOMEM;
0857         netdev_err(sdev->netdev, "failed to create dma pool\n");
0858         goto free_buffs;
0859     }
0860 
0861     for (i = 0; i < txq->len; i++) {
0862         buff = &txq->txbuffs[i];
0863         desc = dma_pool_zalloc(txq->dma_pool, GFP_KERNEL,
0864                        &buff->desc_paddr);
0865         if (!desc) {
0866             netdev_err(sdev->netdev,
0867                    "failed to alloc pool chunk (%i)\n", i);
0868             err = -ENOMEM;
0869             goto free_descs;
0870         }
0871 
0872         desc->hnd = cpu_to_le32((u32)(i + 1));
0873         desc->cmd = SLIC_CMD_XMT_REQ;
0874         desc->flags = 0;
0875         desc->type = cpu_to_le32(SLIC_CMD_TYPE_DUMB);
0876         buff->desc = desc;
0877     }
0878 
0879     return 0;
0880 
0881 free_descs:
0882     while (i--) {
0883         buff = &txq->txbuffs[i];
0884         dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr);
0885     }
0886     dma_pool_destroy(txq->dma_pool);
0887 
0888 free_buffs:
0889     kfree(txq->txbuffs);
0890 
0891     return err;
0892 }
0893 
0894 static void slic_free_tx_queue(struct slic_device *sdev)
0895 {
0896     struct slic_tx_queue *txq = &sdev->txq;
0897     struct slic_tx_buffer *buff;
0898     unsigned int i;
0899 
0900     for (i = 0; i < txq->len; i++) {
0901         buff = &txq->txbuffs[i];
0902         dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr);
0903         if (!buff->skb)
0904             continue;
0905 
0906         dma_unmap_single(&sdev->pdev->dev,
0907                  dma_unmap_addr(buff, map_addr),
0908                  dma_unmap_len(buff, map_len), DMA_TO_DEVICE);
0909         consume_skb(buff->skb);
0910     }
0911     dma_pool_destroy(txq->dma_pool);
0912 
0913     kfree(txq->txbuffs);
0914 }
0915 
0916 static int slic_init_rx_queue(struct slic_device *sdev)
0917 {
0918     struct slic_rx_queue *rxq = &sdev->rxq;
0919     struct slic_rx_buffer *buff;
0920 
0921     rxq->len = SLIC_NUM_RX_LES;
0922     rxq->done_idx = 0;
0923     rxq->put_idx = 0;
0924 
0925     buff = kcalloc(rxq->len, sizeof(*buff), GFP_KERNEL);
0926     if (!buff)
0927         return -ENOMEM;
0928 
0929     rxq->rxbuffs = buff;
0930     slic_refill_rx_queue(sdev, GFP_KERNEL);
0931 
0932     return 0;
0933 }
0934 
0935 static void slic_free_rx_queue(struct slic_device *sdev)
0936 {
0937     struct slic_rx_queue *rxq = &sdev->rxq;
0938     struct slic_rx_buffer *buff;
0939     unsigned int i;
0940 
0941     /* free rx buffers */
0942     for (i = 0; i < rxq->len; i++) {
0943         buff = &rxq->rxbuffs[i];
0944 
0945         if (!buff->skb)
0946             continue;
0947 
0948         dma_unmap_single(&sdev->pdev->dev,
0949                  dma_unmap_addr(buff, map_addr),
0950                  dma_unmap_len(buff, map_len),
0951                  DMA_FROM_DEVICE);
0952         consume_skb(buff->skb);
0953     }
0954     kfree(rxq->rxbuffs);
0955 }
0956 
0957 static void slic_set_link_autoneg(struct slic_device *sdev)
0958 {
0959     unsigned int subid = sdev->pdev->subsystem_device;
0960     u32 val;
0961 
0962     if (sdev->is_fiber) {
0963         /* We've got a fiber gigabit interface, and register 4 is
0964          * different in fiber mode than in copper mode.
0965          */
0966         /* advertise FD only @1000 Mb */
0967         val = MII_ADVERTISE << 16 | ADVERTISE_1000XFULL |
0968               ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
0969         /* enable PAUSE frames */
0970         slic_write(sdev, SLIC_REG_WPHY, val);
0971         /* reset phy, enable auto-neg  */
0972         val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
0973               BMCR_ANRESTART;
0974         slic_write(sdev, SLIC_REG_WPHY, val);
0975     } else {    /* copper gigabit */
0976         /* We've got a copper gigabit interface, and register 4 is
0977          * different in copper mode than in fiber mode.
0978          */
0979         /* advertise 10/100 Mb modes   */
0980         val = MII_ADVERTISE << 16 | ADVERTISE_100FULL |
0981               ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF;
0982         /* enable PAUSE frames  */
0983         val |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
0984         /* required by the Cicada PHY  */
0985         val |= ADVERTISE_CSMA;
0986         slic_write(sdev, SLIC_REG_WPHY, val);
0987 
0988         /* advertise FD only @1000 Mb  */
0989         val = MII_CTRL1000 << 16 | ADVERTISE_1000FULL;
0990         slic_write(sdev, SLIC_REG_WPHY, val);
0991 
0992         if (subid != PCI_SUBDEVICE_ID_ALACRITECH_CICADA) {
0993              /* if a Marvell PHY enable auto crossover */
0994             val = SLIC_MIICR_REG_16 | SLIC_MRV_REG16_XOVERON;
0995             slic_write(sdev, SLIC_REG_WPHY, val);
0996 
0997             /* reset phy, enable auto-neg  */
0998             val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
0999                   BMCR_ANRESTART;
1000             slic_write(sdev, SLIC_REG_WPHY, val);
1001         } else {
1002             /* enable and restart auto-neg (don't reset)  */
1003             val = MII_BMCR << 16 | BMCR_ANENABLE | BMCR_ANRESTART;
1004             slic_write(sdev, SLIC_REG_WPHY, val);
1005         }
1006     }
1007 }
1008 
1009 static void slic_set_mac_address(struct slic_device *sdev)
1010 {
1011     const u8 *addr = sdev->netdev->dev_addr;
1012     u32 val;
1013 
1014     val = addr[5] | addr[4] << 8 | addr[3] << 16 | addr[2] << 24;
1015 
1016     slic_write(sdev, SLIC_REG_WRADDRAL, val);
1017     slic_write(sdev, SLIC_REG_WRADDRBL, val);
1018 
1019     val = addr[0] << 8 | addr[1];
1020 
1021     slic_write(sdev, SLIC_REG_WRADDRAH, val);
1022     slic_write(sdev, SLIC_REG_WRADDRBH, val);
1023     slic_flush_write(sdev);
1024 }
1025 
1026 static u32 slic_read_dword_from_firmware(const struct firmware *fw, int *offset)
1027 {
1028     int idx = *offset;
1029     __le32 val;
1030 
1031     memcpy(&val, fw->data + *offset, sizeof(val));
1032     idx += 4;
1033     *offset = idx;
1034 
1035     return le32_to_cpu(val);
1036 }
1037 
1038 MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_MOJAVE);
1039 MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_OASIS);
1040 
1041 static int slic_load_rcvseq_firmware(struct slic_device *sdev)
1042 {
1043     const struct firmware *fw;
1044     const char *file;
1045     u32 codelen;
1046     int idx = 0;
1047     u32 instr;
1048     u32 addr;
1049     int err;
1050 
1051     file = (sdev->model == SLIC_MODEL_OASIS) ?  SLIC_RCV_FIRMWARE_OASIS :
1052                             SLIC_RCV_FIRMWARE_MOJAVE;
1053     err = request_firmware(&fw, file, &sdev->pdev->dev);
1054     if (err) {
1055         dev_err(&sdev->pdev->dev,
1056             "failed to load receive sequencer firmware %s\n", file);
1057         return err;
1058     }
1059     /* Do an initial sanity check concerning firmware size now. A further
1060      * check follows below.
1061      */
1062     if (fw->size < SLIC_FIRMWARE_MIN_SIZE) {
1063         dev_err(&sdev->pdev->dev,
1064             "invalid firmware size %zu (min %u expected)\n",
1065             fw->size, SLIC_FIRMWARE_MIN_SIZE);
1066         err = -EINVAL;
1067         goto release;
1068     }
1069 
1070     codelen = slic_read_dword_from_firmware(fw, &idx);
1071 
1072     /* do another sanity check against firmware size */
1073     if ((codelen + 4) > fw->size) {
1074         dev_err(&sdev->pdev->dev,
1075             "invalid rcv-sequencer firmware size %zu\n", fw->size);
1076         err = -EINVAL;
1077         goto release;
1078     }
1079 
1080     /* download sequencer code to card */
1081     slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_BEGIN);
1082     for (addr = 0; addr < codelen; addr++) {
1083         __le32 val;
1084         /* write out instruction address */
1085         slic_write(sdev, SLIC_REG_RCV_WCS, addr);
1086 
1087         instr = slic_read_dword_from_firmware(fw, &idx);
1088         /* write out the instruction data low addr */
1089         slic_write(sdev, SLIC_REG_RCV_WCS, instr);
1090 
1091         val = (__le32)fw->data[idx];
1092         instr = le32_to_cpu(val);
1093         idx++;
1094         /* write out the instruction data high addr */
1095         slic_write(sdev, SLIC_REG_RCV_WCS, instr);
1096     }
1097     /* finish download */
1098     slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_FINISH);
1099     slic_flush_write(sdev);
1100 release:
1101     release_firmware(fw);
1102 
1103     return err;
1104 }
1105 
1106 MODULE_FIRMWARE(SLIC_FIRMWARE_MOJAVE);
1107 MODULE_FIRMWARE(SLIC_FIRMWARE_OASIS);
1108 
1109 static int slic_load_firmware(struct slic_device *sdev)
1110 {
1111     u32 sectstart[SLIC_FIRMWARE_MAX_SECTIONS];
1112     u32 sectsize[SLIC_FIRMWARE_MAX_SECTIONS];
1113     const struct firmware *fw;
1114     unsigned int datalen;
1115     const char *file;
1116     int code_start;
1117     unsigned int i;
1118     u32 numsects;
1119     int idx = 0;
1120     u32 sect;
1121     u32 instr;
1122     u32 addr;
1123     u32 base;
1124     int err;
1125 
1126     file = (sdev->model == SLIC_MODEL_OASIS) ?  SLIC_FIRMWARE_OASIS :
1127                             SLIC_FIRMWARE_MOJAVE;
1128     err = request_firmware(&fw, file, &sdev->pdev->dev);
1129     if (err) {
1130         dev_err(&sdev->pdev->dev, "failed to load firmware %s\n", file);
1131         return err;
1132     }
1133     /* Do an initial sanity check concerning firmware size now. A further
1134      * check follows below.
1135      */
1136     if (fw->size < SLIC_FIRMWARE_MIN_SIZE) {
1137         dev_err(&sdev->pdev->dev,
1138             "invalid firmware size %zu (min is %u)\n", fw->size,
1139             SLIC_FIRMWARE_MIN_SIZE);
1140         err = -EINVAL;
1141         goto release;
1142     }
1143 
1144     numsects = slic_read_dword_from_firmware(fw, &idx);
1145     if (numsects == 0 || numsects > SLIC_FIRMWARE_MAX_SECTIONS) {
1146         dev_err(&sdev->pdev->dev,
1147             "invalid number of sections in firmware: %u", numsects);
1148         err = -EINVAL;
1149         goto release;
1150     }
1151 
1152     datalen = numsects * 8 + 4;
1153     for (i = 0; i < numsects; i++) {
1154         sectsize[i] = slic_read_dword_from_firmware(fw, &idx);
1155         datalen += sectsize[i];
1156     }
1157 
1158     /* do another sanity check against firmware size */
1159     if (datalen > fw->size) {
1160         dev_err(&sdev->pdev->dev,
1161             "invalid firmware size %zu (expected >= %u)\n",
1162             fw->size, datalen);
1163         err = -EINVAL;
1164         goto release;
1165     }
1166     /* get sections */
1167     for (i = 0; i < numsects; i++)
1168         sectstart[i] = slic_read_dword_from_firmware(fw, &idx);
1169 
1170     code_start = idx;
1171     instr = slic_read_dword_from_firmware(fw, &idx);
1172 
1173     for (sect = 0; sect < numsects; sect++) {
1174         unsigned int ssize = sectsize[sect] >> 3;
1175 
1176         base = sectstart[sect];
1177 
1178         for (addr = 0; addr < ssize; addr++) {
1179             /* write out instruction address */
1180             slic_write(sdev, SLIC_REG_WCS, base + addr);
1181             /* write out instruction to low addr */
1182             slic_write(sdev, SLIC_REG_WCS, instr);
1183             instr = slic_read_dword_from_firmware(fw, &idx);
1184             /* write out instruction to high addr */
1185             slic_write(sdev, SLIC_REG_WCS, instr);
1186             instr = slic_read_dword_from_firmware(fw, &idx);
1187         }
1188     }
1189 
1190     idx = code_start;
1191 
1192     for (sect = 0; sect < numsects; sect++) {
1193         unsigned int ssize = sectsize[sect] >> 3;
1194 
1195         instr = slic_read_dword_from_firmware(fw, &idx);
1196         base = sectstart[sect];
1197         if (base < 0x8000)
1198             continue;
1199 
1200         for (addr = 0; addr < ssize; addr++) {
1201             /* write out instruction address */
1202             slic_write(sdev, SLIC_REG_WCS,
1203                    SLIC_WCS_COMPARE | (base + addr));
1204             /* write out instruction to low addr */
1205             slic_write(sdev, SLIC_REG_WCS, instr);
1206             instr = slic_read_dword_from_firmware(fw, &idx);
1207             /* write out instruction to high addr */
1208             slic_write(sdev, SLIC_REG_WCS, instr);
1209             instr = slic_read_dword_from_firmware(fw, &idx);
1210         }
1211     }
1212     slic_flush_write(sdev);
1213     mdelay(10);
1214     /* everything OK, kick off the card */
1215     slic_write(sdev, SLIC_REG_WCS, SLIC_WCS_START);
1216     slic_flush_write(sdev);
1217     /* wait long enough for ucode to init card and reach the mainloop */
1218     mdelay(20);
1219 release:
1220     release_firmware(fw);
1221 
1222     return err;
1223 }
1224 
1225 static int slic_init_shmem(struct slic_device *sdev)
1226 {
1227     struct slic_shmem *sm = &sdev->shmem;
1228     struct slic_shmem_data *sm_data;
1229     dma_addr_t paddr;
1230 
1231     sm_data = dma_alloc_coherent(&sdev->pdev->dev, sizeof(*sm_data),
1232                      &paddr, GFP_KERNEL);
1233     if (!sm_data) {
1234         dev_err(&sdev->pdev->dev, "failed to allocate shared memory\n");
1235         return -ENOMEM;
1236     }
1237 
1238     sm->shmem_data = sm_data;
1239     sm->isr_paddr = paddr;
1240     sm->link_paddr = paddr + offsetof(struct slic_shmem_data, link);
1241 
1242     return 0;
1243 }
1244 
1245 static void slic_free_shmem(struct slic_device *sdev)
1246 {
1247     struct slic_shmem *sm = &sdev->shmem;
1248     struct slic_shmem_data *sm_data = sm->shmem_data;
1249 
1250     dma_free_coherent(&sdev->pdev->dev, sizeof(*sm_data), sm_data,
1251               sm->isr_paddr);
1252 }
1253 
1254 static int slic_init_iface(struct slic_device *sdev)
1255 {
1256     struct slic_shmem *sm = &sdev->shmem;
1257     int err;
1258 
1259     sdev->upr_list.pending = false;
1260 
1261     err = slic_init_shmem(sdev);
1262     if (err) {
1263         netdev_err(sdev->netdev, "failed to init shared memory\n");
1264         return err;
1265     }
1266 
1267     err = slic_load_firmware(sdev);
1268     if (err) {
1269         netdev_err(sdev->netdev, "failed to load firmware\n");
1270         goto free_sm;
1271     }
1272 
1273     err = slic_load_rcvseq_firmware(sdev);
1274     if (err) {
1275         netdev_err(sdev->netdev,
1276                "failed to load firmware for receive sequencer\n");
1277         goto free_sm;
1278     }
1279 
1280     slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1281     slic_flush_write(sdev);
1282     mdelay(1);
1283 
1284     err = slic_init_rx_queue(sdev);
1285     if (err) {
1286         netdev_err(sdev->netdev, "failed to init rx queue: %u\n", err);
1287         goto free_sm;
1288     }
1289 
1290     err = slic_init_tx_queue(sdev);
1291     if (err) {
1292         netdev_err(sdev->netdev, "failed to init tx queue: %u\n", err);
1293         goto free_rxq;
1294     }
1295 
1296     err = slic_init_stat_queue(sdev);
1297     if (err) {
1298         netdev_err(sdev->netdev, "failed to init status queue: %u\n",
1299                err);
1300         goto free_txq;
1301     }
1302 
1303     slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
1304     napi_enable(&sdev->napi);
1305     /* disable irq mitigation */
1306     slic_write(sdev, SLIC_REG_INTAGG, 0);
1307     slic_write(sdev, SLIC_REG_ISR, 0);
1308     slic_flush_write(sdev);
1309 
1310     slic_set_mac_address(sdev);
1311 
1312     spin_lock_bh(&sdev->link_lock);
1313     sdev->duplex = DUPLEX_UNKNOWN;
1314     sdev->speed = SPEED_UNKNOWN;
1315     spin_unlock_bh(&sdev->link_lock);
1316 
1317     slic_set_link_autoneg(sdev);
1318 
1319     err = request_irq(sdev->pdev->irq, slic_irq, IRQF_SHARED, DRV_NAME,
1320               sdev);
1321     if (err) {
1322         netdev_err(sdev->netdev, "failed to request irq: %u\n", err);
1323         goto disable_napi;
1324     }
1325 
1326     slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_ON);
1327     slic_flush_write(sdev);
1328     /* request initial link status */
1329     err = slic_handle_link_change(sdev);
1330     if (err)
1331         netdev_warn(sdev->netdev,
1332                 "failed to set initial link state: %u\n", err);
1333     return 0;
1334 
1335 disable_napi:
1336     napi_disable(&sdev->napi);
1337     slic_free_stat_queue(sdev);
1338 free_txq:
1339     slic_free_tx_queue(sdev);
1340 free_rxq:
1341     slic_free_rx_queue(sdev);
1342 free_sm:
1343     slic_free_shmem(sdev);
1344     slic_card_reset(sdev);
1345 
1346     return err;
1347 }
1348 
1349 static int slic_open(struct net_device *dev)
1350 {
1351     struct slic_device *sdev = netdev_priv(dev);
1352     int err;
1353 
1354     netif_carrier_off(dev);
1355 
1356     err = slic_init_iface(sdev);
1357     if (err) {
1358         netdev_err(dev, "failed to initialize interface: %i\n", err);
1359         return err;
1360     }
1361 
1362     netif_start_queue(dev);
1363 
1364     return 0;
1365 }
1366 
1367 static int slic_close(struct net_device *dev)
1368 {
1369     struct slic_device *sdev = netdev_priv(dev);
1370     u32 val;
1371 
1372     netif_stop_queue(dev);
1373 
1374     /* stop irq handling */
1375     napi_disable(&sdev->napi);
1376     slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1377     slic_write(sdev, SLIC_REG_ISR, 0);
1378     slic_flush_write(sdev);
1379 
1380     free_irq(sdev->pdev->irq, sdev);
1381     /* turn off RCV and XMT and power down PHY */
1382     val = SLIC_GXCR_RESET | SLIC_GXCR_PAUSEEN;
1383     slic_write(sdev, SLIC_REG_WXCFG, val);
1384 
1385     val = SLIC_GRCR_RESET | SLIC_GRCR_CTLEN | SLIC_GRCR_ADDRAEN |
1386           SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT;
1387     slic_write(sdev, SLIC_REG_WRCFG, val);
1388 
1389     val = MII_BMCR << 16 | BMCR_PDOWN;
1390     slic_write(sdev, SLIC_REG_WPHY, val);
1391     slic_flush_write(sdev);
1392 
1393     slic_clear_upr_list(&sdev->upr_list);
1394     slic_write(sdev, SLIC_REG_QUIESCE, 0);
1395 
1396     slic_free_stat_queue(sdev);
1397     slic_free_tx_queue(sdev);
1398     slic_free_rx_queue(sdev);
1399     slic_free_shmem(sdev);
1400 
1401     slic_card_reset(sdev);
1402     netif_carrier_off(dev);
1403 
1404     return 0;
1405 }
1406 
1407 static netdev_tx_t slic_xmit(struct sk_buff *skb, struct net_device *dev)
1408 {
1409     struct slic_device *sdev = netdev_priv(dev);
1410     struct slic_tx_queue *txq = &sdev->txq;
1411     struct slic_tx_buffer *buff;
1412     struct slic_tx_desc *desc;
1413     dma_addr_t paddr;
1414     u32 cbar_val;
1415     u32 maplen;
1416 
1417     if (unlikely(slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS)) {
1418         netdev_err(dev, "BUG! not enough tx LEs left: %u\n",
1419                slic_get_free_tx_descs(txq));
1420         return NETDEV_TX_BUSY;
1421     }
1422 
1423     maplen = skb_headlen(skb);
1424     paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen,
1425                    DMA_TO_DEVICE);
1426     if (dma_mapping_error(&sdev->pdev->dev, paddr)) {
1427         netdev_err(dev, "failed to map tx buffer\n");
1428         goto drop_skb;
1429     }
1430 
1431     buff = &txq->txbuffs[txq->put_idx];
1432     buff->skb = skb;
1433     dma_unmap_addr_set(buff, map_addr, paddr);
1434     dma_unmap_len_set(buff, map_len, maplen);
1435 
1436     desc = buff->desc;
1437     desc->totlen = cpu_to_le32(maplen);
1438     desc->paddrl = cpu_to_le32(lower_32_bits(paddr));
1439     desc->paddrh = cpu_to_le32(upper_32_bits(paddr));
1440     desc->len = cpu_to_le32(maplen);
1441 
1442     txq->put_idx = slic_next_queue_idx(txq->put_idx, txq->len);
1443 
1444     cbar_val = lower_32_bits(buff->desc_paddr) | 1;
1445     /* complete writes to RAM and DMA before hardware is informed */
1446     wmb();
1447 
1448     slic_write(sdev, SLIC_REG_CBAR, cbar_val);
1449 
1450     if (slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS)
1451         netif_stop_queue(dev);
1452 
1453     return NETDEV_TX_OK;
1454 drop_skb:
1455     dev_kfree_skb_any(skb);
1456 
1457     return NETDEV_TX_OK;
1458 }
1459 
1460 static void slic_get_stats(struct net_device *dev,
1461                struct rtnl_link_stats64 *lst)
1462 {
1463     struct slic_device *sdev = netdev_priv(dev);
1464     struct slic_stats *stats = &sdev->stats;
1465 
1466     SLIC_GET_STATS_COUNTER(lst->rx_packets, stats, rx_packets);
1467     SLIC_GET_STATS_COUNTER(lst->tx_packets, stats, tx_packets);
1468     SLIC_GET_STATS_COUNTER(lst->rx_bytes, stats, rx_bytes);
1469     SLIC_GET_STATS_COUNTER(lst->tx_bytes, stats, tx_bytes);
1470     SLIC_GET_STATS_COUNTER(lst->rx_errors, stats, rx_errors);
1471     SLIC_GET_STATS_COUNTER(lst->rx_dropped, stats, rx_buff_miss);
1472     SLIC_GET_STATS_COUNTER(lst->tx_dropped, stats, tx_dropped);
1473     SLIC_GET_STATS_COUNTER(lst->multicast, stats, rx_mcasts);
1474     SLIC_GET_STATS_COUNTER(lst->rx_over_errors, stats, rx_buffoflow);
1475     SLIC_GET_STATS_COUNTER(lst->rx_crc_errors, stats, rx_crc);
1476     SLIC_GET_STATS_COUNTER(lst->rx_fifo_errors, stats, rx_oflow802);
1477     SLIC_GET_STATS_COUNTER(lst->tx_carrier_errors, stats, tx_carrier);
1478 }
1479 
1480 static int slic_get_sset_count(struct net_device *dev, int sset)
1481 {
1482     switch (sset) {
1483     case ETH_SS_STATS:
1484         return ARRAY_SIZE(slic_stats_strings);
1485     default:
1486         return -EOPNOTSUPP;
1487     }
1488 }
1489 
1490 static void slic_get_ethtool_stats(struct net_device *dev,
1491                    struct ethtool_stats *eth_stats, u64 *data)
1492 {
1493     struct slic_device *sdev = netdev_priv(dev);
1494     struct slic_stats *stats = &sdev->stats;
1495 
1496     SLIC_GET_STATS_COUNTER(data[0], stats, rx_packets);
1497     SLIC_GET_STATS_COUNTER(data[1], stats, rx_bytes);
1498     SLIC_GET_STATS_COUNTER(data[2], stats, rx_mcasts);
1499     SLIC_GET_STATS_COUNTER(data[3], stats, rx_errors);
1500     SLIC_GET_STATS_COUNTER(data[4], stats, rx_buff_miss);
1501     SLIC_GET_STATS_COUNTER(data[5], stats, rx_tpcsum);
1502     SLIC_GET_STATS_COUNTER(data[6], stats, rx_tpoflow);
1503     SLIC_GET_STATS_COUNTER(data[7], stats, rx_tphlen);
1504     SLIC_GET_STATS_COUNTER(data[8], stats, rx_ipcsum);
1505     SLIC_GET_STATS_COUNTER(data[9], stats, rx_iplen);
1506     SLIC_GET_STATS_COUNTER(data[10], stats, rx_iphlen);
1507     SLIC_GET_STATS_COUNTER(data[11], stats, rx_early);
1508     SLIC_GET_STATS_COUNTER(data[12], stats, rx_buffoflow);
1509     SLIC_GET_STATS_COUNTER(data[13], stats, rx_lcode);
1510     SLIC_GET_STATS_COUNTER(data[14], stats, rx_drbl);
1511     SLIC_GET_STATS_COUNTER(data[15], stats, rx_crc);
1512     SLIC_GET_STATS_COUNTER(data[16], stats, rx_oflow802);
1513     SLIC_GET_STATS_COUNTER(data[17], stats, rx_uflow802);
1514     SLIC_GET_STATS_COUNTER(data[18], stats, tx_packets);
1515     SLIC_GET_STATS_COUNTER(data[19], stats, tx_bytes);
1516     SLIC_GET_STATS_COUNTER(data[20], stats, tx_carrier);
1517     SLIC_GET_STATS_COUNTER(data[21], stats, tx_dropped);
1518     SLIC_GET_STATS_COUNTER(data[22], stats, irq_errs);
1519 }
1520 
1521 static void slic_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1522 {
1523     if (stringset == ETH_SS_STATS) {
1524         memcpy(data, slic_stats_strings, sizeof(slic_stats_strings));
1525         data += sizeof(slic_stats_strings);
1526     }
1527 }
1528 
1529 static void slic_get_drvinfo(struct net_device *dev,
1530                  struct ethtool_drvinfo *info)
1531 {
1532     struct slic_device *sdev = netdev_priv(dev);
1533 
1534     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1535     strlcpy(info->bus_info, pci_name(sdev->pdev), sizeof(info->bus_info));
1536 }
1537 
1538 static const struct ethtool_ops slic_ethtool_ops = {
1539     .get_drvinfo        = slic_get_drvinfo,
1540     .get_link       = ethtool_op_get_link,
1541     .get_strings        = slic_get_strings,
1542     .get_ethtool_stats  = slic_get_ethtool_stats,
1543     .get_sset_count     = slic_get_sset_count,
1544 };
1545 
1546 static const struct net_device_ops slic_netdev_ops = {
1547     .ndo_open       = slic_open,
1548     .ndo_stop       = slic_close,
1549     .ndo_start_xmit     = slic_xmit,
1550     .ndo_set_mac_address    = eth_mac_addr,
1551     .ndo_get_stats64    = slic_get_stats,
1552     .ndo_set_rx_mode    = slic_set_rx_mode,
1553     .ndo_validate_addr  = eth_validate_addr,
1554 };
1555 
1556 static u16 slic_eeprom_csum(unsigned char *eeprom, unsigned int len)
1557 {
1558     unsigned char *ptr = eeprom;
1559     u32 csum = 0;
1560     __le16 data;
1561 
1562     while (len > 1) {
1563         memcpy(&data, ptr, sizeof(data));
1564         csum += le16_to_cpu(data);
1565         ptr += 2;
1566         len -= 2;
1567     }
1568     if (len > 0)
1569         csum += *(u8 *)ptr;
1570     while (csum >> 16)
1571         csum = (csum & 0xFFFF) + ((csum >> 16) & 0xFFFF);
1572     return ~csum;
1573 }
1574 
1575 /* check eeprom size, magic and checksum */
1576 static bool slic_eeprom_valid(unsigned char *eeprom, unsigned int size)
1577 {
1578     const unsigned int MAX_SIZE = 128;
1579     const unsigned int MIN_SIZE = 98;
1580     __le16 magic;
1581     __le16 csum;
1582 
1583     if (size < MIN_SIZE || size > MAX_SIZE)
1584         return false;
1585     memcpy(&magic, eeprom, sizeof(magic));
1586     if (le16_to_cpu(magic) != SLIC_EEPROM_MAGIC)
1587         return false;
1588     /* cut checksum bytes */
1589     size -= 2;
1590     memcpy(&csum, eeprom + size, sizeof(csum));
1591 
1592     return (le16_to_cpu(csum) == slic_eeprom_csum(eeprom, size));
1593 }
1594 
1595 static int slic_read_eeprom(struct slic_device *sdev)
1596 {
1597     unsigned int devfn = PCI_FUNC(sdev->pdev->devfn);
1598     struct slic_shmem *sm = &sdev->shmem;
1599     struct slic_shmem_data *sm_data = sm->shmem_data;
1600     const unsigned int MAX_LOOPS = 5000;
1601     unsigned int codesize;
1602     unsigned char *eeprom;
1603     struct slic_upr *upr;
1604     unsigned int i = 0;
1605     dma_addr_t paddr;
1606     int err = 0;
1607     u8 *mac[2];
1608 
1609     eeprom = dma_alloc_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE,
1610                     &paddr, GFP_KERNEL);
1611     if (!eeprom)
1612         return -ENOMEM;
1613 
1614     slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1615     /* setup ISP temporarily */
1616     slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
1617 
1618     err = slic_new_upr(sdev, SLIC_UPR_CONFIG, paddr);
1619     if (!err) {
1620         for (i = 0; i < MAX_LOOPS; i++) {
1621             if (le32_to_cpu(sm_data->isr) & SLIC_ISR_UPC)
1622                 break;
1623             mdelay(1);
1624         }
1625         if (i == MAX_LOOPS) {
1626             dev_err(&sdev->pdev->dev,
1627                 "timed out while waiting for eeprom data\n");
1628             err = -ETIMEDOUT;
1629         }
1630         upr = slic_dequeue_upr(sdev);
1631         kfree(upr);
1632     }
1633 
1634     slic_write(sdev, SLIC_REG_ISP, 0);
1635     slic_write(sdev, SLIC_REG_ISR, 0);
1636     slic_flush_write(sdev);
1637 
1638     if (err)
1639         goto free_eeprom;
1640 
1641     if (sdev->model == SLIC_MODEL_OASIS) {
1642         struct slic_oasis_eeprom *oee;
1643 
1644         oee = (struct slic_oasis_eeprom *)eeprom;
1645         mac[0] = oee->mac;
1646         mac[1] = oee->mac2;
1647         codesize = le16_to_cpu(oee->eeprom_code_size);
1648     } else {
1649         struct slic_mojave_eeprom *mee;
1650 
1651         mee = (struct slic_mojave_eeprom *)eeprom;
1652         mac[0] = mee->mac;
1653         mac[1] = mee->mac2;
1654         codesize = le16_to_cpu(mee->eeprom_code_size);
1655     }
1656 
1657     if (!slic_eeprom_valid(eeprom, codesize)) {
1658         dev_err(&sdev->pdev->dev, "invalid checksum in eeprom\n");
1659         err = -EINVAL;
1660         goto free_eeprom;
1661     }
1662     /* set mac address */
1663     eth_hw_addr_set(sdev->netdev, mac[devfn]);
1664 free_eeprom:
1665     dma_free_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE, eeprom, paddr);
1666 
1667     return err;
1668 }
1669 
1670 static int slic_init(struct slic_device *sdev)
1671 {
1672     int err;
1673 
1674     spin_lock_init(&sdev->upper_lock);
1675     spin_lock_init(&sdev->link_lock);
1676     INIT_LIST_HEAD(&sdev->upr_list.list);
1677     spin_lock_init(&sdev->upr_list.lock);
1678     u64_stats_init(&sdev->stats.syncp);
1679 
1680     slic_card_reset(sdev);
1681 
1682     err = slic_load_firmware(sdev);
1683     if (err) {
1684         dev_err(&sdev->pdev->dev, "failed to load firmware\n");
1685         return err;
1686     }
1687 
1688     /* we need the shared memory to read EEPROM so set it up temporarily */
1689     err = slic_init_shmem(sdev);
1690     if (err) {
1691         dev_err(&sdev->pdev->dev, "failed to init shared memory\n");
1692         return err;
1693     }
1694 
1695     err = slic_read_eeprom(sdev);
1696     if (err) {
1697         dev_err(&sdev->pdev->dev, "failed to read eeprom\n");
1698         goto free_sm;
1699     }
1700 
1701     slic_card_reset(sdev);
1702     slic_free_shmem(sdev);
1703 
1704     return 0;
1705 free_sm:
1706     slic_free_shmem(sdev);
1707 
1708     return err;
1709 }
1710 
1711 static bool slic_is_fiber(unsigned short subdev)
1712 {
1713     switch (subdev) {
1714     /* Mojave */
1715     case PCI_SUBDEVICE_ID_ALACRITECH_1000X1F:
1716     case PCI_SUBDEVICE_ID_ALACRITECH_SES1001F: fallthrough;
1717     /* Oasis */
1718     case PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF:
1719     case PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF:
1720     case PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF:
1721     case PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF:
1722         return true;
1723     }
1724     return false;
1725 }
1726 
1727 static void slic_configure_pci(struct pci_dev *pdev)
1728 {
1729     u16 old;
1730     u16 cmd;
1731 
1732     pci_read_config_word(pdev, PCI_COMMAND, &old);
1733 
1734     cmd = old | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
1735     if (old != cmd)
1736         pci_write_config_word(pdev, PCI_COMMAND, cmd);
1737 }
1738 
1739 static int slic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1740 {
1741     struct slic_device *sdev;
1742     struct net_device *dev;
1743     int err;
1744 
1745     err = pci_enable_device(pdev);
1746     if (err) {
1747         dev_err(&pdev->dev, "failed to enable PCI device\n");
1748         return err;
1749     }
1750 
1751     pci_set_master(pdev);
1752     pci_try_set_mwi(pdev);
1753 
1754     slic_configure_pci(pdev);
1755 
1756     err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1757     if (err) {
1758         dev_err(&pdev->dev, "failed to setup DMA\n");
1759         goto disable;
1760     }
1761 
1762     dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1763 
1764     err = pci_request_regions(pdev, DRV_NAME);
1765     if (err) {
1766         dev_err(&pdev->dev, "failed to obtain PCI regions\n");
1767         goto disable;
1768     }
1769 
1770     dev = alloc_etherdev(sizeof(*sdev));
1771     if (!dev) {
1772         dev_err(&pdev->dev, "failed to alloc ethernet device\n");
1773         err = -ENOMEM;
1774         goto free_regions;
1775     }
1776 
1777     SET_NETDEV_DEV(dev, &pdev->dev);
1778     pci_set_drvdata(pdev, dev);
1779     dev->irq = pdev->irq;
1780     dev->netdev_ops = &slic_netdev_ops;
1781     dev->hw_features = NETIF_F_RXCSUM;
1782     dev->features |= dev->hw_features;
1783 
1784     dev->ethtool_ops = &slic_ethtool_ops;
1785 
1786     sdev = netdev_priv(dev);
1787     sdev->model = (pdev->device == PCI_DEVICE_ID_ALACRITECH_OASIS) ?
1788               SLIC_MODEL_OASIS : SLIC_MODEL_MOJAVE;
1789     sdev->is_fiber = slic_is_fiber(pdev->subsystem_device);
1790     sdev->pdev = pdev;
1791     sdev->netdev = dev;
1792     sdev->regs = ioremap(pci_resource_start(pdev, 0),
1793                      pci_resource_len(pdev, 0));
1794     if (!sdev->regs) {
1795         dev_err(&pdev->dev, "failed to map registers\n");
1796         err = -ENOMEM;
1797         goto free_netdev;
1798     }
1799 
1800     err = slic_init(sdev);
1801     if (err) {
1802         dev_err(&pdev->dev, "failed to initialize driver\n");
1803         goto unmap;
1804     }
1805 
1806     netif_napi_add(dev, &sdev->napi, slic_poll, NAPI_POLL_WEIGHT);
1807     netif_carrier_off(dev);
1808 
1809     err = register_netdev(dev);
1810     if (err) {
1811         dev_err(&pdev->dev, "failed to register net device: %i\n", err);
1812         goto unmap;
1813     }
1814 
1815     return 0;
1816 
1817 unmap:
1818     iounmap(sdev->regs);
1819 free_netdev:
1820     free_netdev(dev);
1821 free_regions:
1822     pci_release_regions(pdev);
1823 disable:
1824     pci_disable_device(pdev);
1825 
1826     return err;
1827 }
1828 
1829 static void slic_remove(struct pci_dev *pdev)
1830 {
1831     struct net_device *dev = pci_get_drvdata(pdev);
1832     struct slic_device *sdev = netdev_priv(dev);
1833 
1834     unregister_netdev(dev);
1835     iounmap(sdev->regs);
1836     free_netdev(dev);
1837     pci_release_regions(pdev);
1838     pci_disable_device(pdev);
1839 }
1840 
1841 static struct pci_driver slic_driver = {
1842     .name = DRV_NAME,
1843     .id_table = slic_id_tbl,
1844     .probe = slic_probe,
1845     .remove = slic_remove,
1846 };
1847 
1848 module_pci_driver(slic_driver);
1849 
1850 MODULE_DESCRIPTION("Alacritech non-accelerated SLIC driver");
1851 MODULE_AUTHOR("Lino Sanfilippo <LinoSanfilippo@gmx.de>");
1852 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!