ethernet/alacritech/slic.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef _SLIC_H
0004 #define _SLIC_H
0005
0006 #include <linux/types.h>
0007 #include <linux/netdevice.h>
0008 #include <linux/spinlock_types.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/pci.h>
0011 #include <linux/list.h>
0012 #include <linux/u64_stats_sync.h>
0013
0014 #define SLIC_VGBSTAT_XPERR      0x40000000
0015 #define SLIC_VGBSTAT_XERRSHFT       25
0016 #define SLIC_VGBSTAT_XCSERR     0x23
0017 #define SLIC_VGBSTAT_XUFLOW     0x22
0018 #define SLIC_VGBSTAT_XHLEN      0x20
0019 #define SLIC_VGBSTAT_NETERR     0x01000000
0020 #define SLIC_VGBSTAT_NERRSHFT       16
0021 #define SLIC_VGBSTAT_NERRMSK        0x1ff
0022 #define SLIC_VGBSTAT_NCSERR     0x103
0023 #define SLIC_VGBSTAT_NUFLOW     0x102
0024 #define SLIC_VGBSTAT_NHLEN      0x100
0025 #define SLIC_VGBSTAT_LNKERR     0x00000080
0026 #define SLIC_VGBSTAT_LERRMSK        0xff
0027 #define SLIC_VGBSTAT_LDEARLY        0x86
0028 #define SLIC_VGBSTAT_LBOFLO     0x85
0029 #define SLIC_VGBSTAT_LCODERR        0x84
0030 #define SLIC_VGBSTAT_LDBLNBL        0x83
0031 #define SLIC_VGBSTAT_LCRCERR        0x82
0032 #define SLIC_VGBSTAT_LOFLO      0x81
0033 #define SLIC_VGBSTAT_LUFLO      0x80
0034
0035 #define SLIC_IRHDDR_FLEN_MSK        0x0000ffff
0036 #define SLIC_IRHDDR_SVALID      0x80000000
0037 #define SLIC_IRHDDR_ERR         0x10000000
0038
0039 #define SLIC_VRHSTAT_802OE      0x80000000
0040 #define SLIC_VRHSTAT_TPOFLO     0x10000000
0041 #define SLIC_VRHSTATB_802UE     0x80000000
0042 #define SLIC_VRHSTATB_RCVE      0x40000000
0043 #define SLIC_VRHSTATB_BUFF      0x20000000
0044 #define SLIC_VRHSTATB_CARRE     0x08000000
0045 #define SLIC_VRHSTATB_LONGE     0x02000000
0046 #define SLIC_VRHSTATB_PREA      0x01000000
0047 #define SLIC_VRHSTATB_CRC       0x00800000
0048 #define SLIC_VRHSTATB_DRBL      0x00400000
0049 #define SLIC_VRHSTATB_CODE      0x00200000
0050 #define SLIC_VRHSTATB_TPCSUM        0x00100000
0051 #define SLIC_VRHSTATB_TPHLEN        0x00080000
0052 #define SLIC_VRHSTATB_IPCSUM        0x00040000
0053 #define SLIC_VRHSTATB_IPLERR        0x00020000
0054 #define SLIC_VRHSTATB_IPHERR        0x00010000
0055
0056 #define SLIC_CMD_XMT_REQ        0x01
0057 #define SLIC_CMD_TYPE_DUMB      3
0058
0059 #define SLIC_RESET_MAGIC        0xDEAD
0060 #define SLIC_ICR_INT_OFF        0
0061 #define SLIC_ICR_INT_ON         1
0062 #define SLIC_ICR_INT_MASK       2
0063
0064 #define SLIC_ISR_ERR            0x80000000
0065 #define SLIC_ISR_RCV            0x40000000
0066 #define SLIC_ISR_CMD            0x20000000
0067 #define SLIC_ISR_IO         0x60000000
0068 #define SLIC_ISR_UPC            0x10000000
0069 #define SLIC_ISR_LEVENT         0x08000000
0070 #define SLIC_ISR_RMISS          0x02000000
0071 #define SLIC_ISR_UPCERR         0x01000000
0072 #define SLIC_ISR_XDROP          0x00800000
0073 #define SLIC_ISR_UPCBSY         0x00020000
0074
0075 #define SLIC_ISR_PING_MASK      0x00700000
0076 #define SLIC_ISR_UPCERR_MASK        (SLIC_ISR_UPCERR | SLIC_ISR_UPCBSY)
0077 #define SLIC_ISR_UPC_MASK       (SLIC_ISR_UPC | SLIC_ISR_UPCERR_MASK)
0078 #define SLIC_WCS_START          0x80000000
0079 #define SLIC_WCS_COMPARE        0x40000000
0080 #define SLIC_RCVWCS_BEGIN       0x40000000
0081 #define SLIC_RCVWCS_FINISH      0x80000000
0082
0083 #define SLIC_MIICR_REG_16       0x00100000
0084 #define SLIC_MRV_REG16_XOVERON      0x0068
0085
0086 #define SLIC_GIG_LINKUP         0x0001
0087 #define SLIC_GIG_FULLDUPLEX     0x0002
0088 #define SLIC_GIG_SPEED_MASK     0x000C
0089 #define SLIC_GIG_SPEED_1000     0x0008
0090 #define SLIC_GIG_SPEED_100      0x0004
0091 #define SLIC_GIG_SPEED_10       0x0000
0092
0093 #define SLIC_GMCR_RESET         0x80000000
0094 #define SLIC_GMCR_GBIT          0x20000000
0095 #define SLIC_GMCR_FULLD         0x10000000
0096 #define SLIC_GMCR_GAPBB_SHIFT       14
0097 #define SLIC_GMCR_GAPR1_SHIFT       7
0098 #define SLIC_GMCR_GAPR2_SHIFT       0
0099 #define SLIC_GMCR_GAPBB_1000        0x60
0100 #define SLIC_GMCR_GAPR1_1000        0x2C
0101 #define SLIC_GMCR_GAPR2_1000        0x40
0102 #define SLIC_GMCR_GAPBB_100     0x70
0103 #define SLIC_GMCR_GAPR1_100     0x2C
0104 #define SLIC_GMCR_GAPR2_100     0x40
0105
0106 #define SLIC_XCR_RESET          0x80000000
0107 #define SLIC_XCR_XMTEN          0x40000000
0108 #define SLIC_XCR_PAUSEEN        0x20000000
0109 #define SLIC_XCR_LOADRNG        0x10000000
0110
0111 #define SLIC_GXCR_RESET         0x80000000
0112 #define SLIC_GXCR_XMTEN         0x40000000
0113 #define SLIC_GXCR_PAUSEEN       0x20000000
0114
0115 #define SLIC_GRCR_RESET         0x80000000
0116 #define SLIC_GRCR_RCVEN         0x40000000
0117 #define SLIC_GRCR_RCVALL        0x20000000
0118 #define SLIC_GRCR_RCVBAD        0x10000000
0119 #define SLIC_GRCR_CTLEN         0x08000000
0120 #define SLIC_GRCR_ADDRAEN       0x02000000
0121 #define SLIC_GRCR_HASHSIZE_SHIFT    17
0122 #define SLIC_GRCR_HASHSIZE      14
0123
0124 /* Reset Register */
0125 #define SLIC_REG_RESET          0x0000
0126 /* Interrupt Control Register */
0127 #define SLIC_REG_ICR            0x0008
0128 /* Interrupt status pointer */
0129 #define SLIC_REG_ISP            0x0010
0130 /* Interrupt status */
0131 #define SLIC_REG_ISR            0x0018
0132 /* Header buffer address reg
0133  * 31-8 - phy addr of set of contiguous hdr buffers
0134  *  7-0 - number of buffers passed
0135  * Buffers are 256 bytes long on 256-byte boundaries.
0136  */
0137 #define SLIC_REG_HBAR           0x0020
0138 /* Data buffer handle & address reg
0139  * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.
0140  */
0141 #define SLIC_REG_DBAR           0x0028
0142 /* Xmt Cmd buf addr regs.
0143  * 1 per XMT interface
0144  * 31-5 - phy addr of host command buffer
0145  *  4-0 - length of cmd in multiples of 32 bytes
0146  * Buffers are 32 bytes up to 512 bytes long
0147  */
0148 #define SLIC_REG_CBAR           0x0030
0149 /* Write control store */
0150 #define SLIC_REG_WCS            0x0034
0151 /*Response buffer address reg.
0152  * 31-8 - phy addr of set of contiguous response buffers
0153  * 7-0 - number of buffers passed
0154  * Buffers are 32 bytes long on 32-byte boundaries.
0155  */
0156 #define SLIC_REG_RBAR           0x0038
0157 /* Read statistics (UPR) */
0158 #define SLIC_REG_RSTAT          0x0040
0159 /* Read link status */
0160 #define SLIC_REG_LSTAT          0x0048
0161 /* Write Mac Config */
0162 #define SLIC_REG_WMCFG          0x0050
0163 /* Write phy register */
0164 #define SLIC_REG_WPHY           0x0058
0165 /* Rcv Cmd buf addr reg */
0166 #define SLIC_REG_RCBAR          0x0060
0167 /* Read SLIC Config*/
0168 #define SLIC_REG_RCONFIG        0x0068
0169 /* Interrupt aggregation time */
0170 #define SLIC_REG_INTAGG         0x0070
0171 /* Write XMIT config reg */
0172 #define SLIC_REG_WXCFG          0x0078
0173 /* Write RCV config reg */
0174 #define SLIC_REG_WRCFG          0x0080
0175 /* Write rcv addr a low */
0176 #define SLIC_REG_WRADDRAL       0x0088
0177 /* Write rcv addr a high */
0178 #define SLIC_REG_WRADDRAH       0x0090
0179 /* Write rcv addr b low */
0180 #define SLIC_REG_WRADDRBL       0x0098
0181 /* Write rcv addr b high */
0182 #define SLIC_REG_WRADDRBH       0x00a0
0183 /* Low bits of mcast mask */
0184 #define SLIC_REG_MCASTLOW       0x00a8
0185 /* High bits of mcast mask */
0186 #define SLIC_REG_MCASTHIGH      0x00b0
0187 /* Ping the card */
0188 #define SLIC_REG_PING           0x00b8
0189 /* Dump command */
0190 #define SLIC_REG_DUMP_CMD       0x00c0
0191 /* Dump data pointer */
0192 #define SLIC_REG_DUMP_DATA      0x00c8
0193 /* Read card's pci_status register */
0194 #define SLIC_REG_PCISTATUS      0x00d0
0195 /* Write hostid field */
0196 #define SLIC_REG_WRHOSTID       0x00d8
0197 /* Put card in a low power state */
0198 #define SLIC_REG_LOW_POWER      0x00e0
0199 /* Force slic into quiescent state  before soft reset */
0200 #define SLIC_REG_QUIESCE        0x00e8
0201 /* Reset interface queues */
0202 #define SLIC_REG_RESET_IFACE        0x00f0
0203 /* Register is only written when it has changed.
0204  * Bits 63-32 for host i/f addrs.
0205  */
0206 #define SLIC_REG_ADDR_UPPER     0x00f8
0207 /* 64 bit Header buffer address reg */
0208 #define SLIC_REG_HBAR64         0x0100
0209 /* 64 bit Data buffer handle & address reg */
0210 #define SLIC_REG_DBAR64         0x0108
0211 /* 64 bit Xmt Cmd buf addr regs. */
0212 #define SLIC_REG_CBAR64         0x0110
0213 /* 64 bit Response buffer address reg.*/
0214 #define SLIC_REG_RBAR64         0x0118
0215 /* 64 bit Rcv Cmd buf addr reg*/
0216 #define SLIC_REG_RCBAR64        0x0120
0217 /* Read statistics (64 bit UPR) */
0218 #define SLIC_REG_RSTAT64        0x0128
0219 /* Download Gigabit RCV sequencer ucode */
0220 #define SLIC_REG_RCV_WCS        0x0130
0221 /* Write VlanId field */
0222 #define SLIC_REG_WRVLANID       0x0138
0223 /* Read Transformer info */
0224 #define SLIC_REG_READ_XF_INFO       0x0140
0225 /* Write Transformer info */
0226 #define SLIC_REG_WRITE_XF_INFO      0x0148
0227 /* Write card ticks per second */
0228 #define SLIC_REG_TICKS_PER_SEC      0x0170
0229 #define SLIC_REG_HOSTID         0x1554
0230
0231 #define PCI_VENDOR_ID_ALACRITECH        0x139A
0232 #define PCI_DEVICE_ID_ALACRITECH_MOJAVE     0x0005
0233 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1  0x0005
0234 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2    0x0006
0235 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1F 0x0007
0236 #define PCI_SUBDEVICE_ID_ALACRITECH_CICADA  0x0008
0237 #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001T    0x2006
0238 #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001F    0x2007
0239 #define PCI_DEVICE_ID_ALACRITECH_OASIS      0x0007
0240 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT   0x000B
0241 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF   0x000C
0242 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT   0x000D
0243 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF   0x000E
0244 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF   0x000F
0245 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET   0x0010
0246 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF   0x0011
0247 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET   0x0012
0248
0249 /* Note: power of two required for number descriptors  */
0250 #define SLIC_NUM_RX_LES         256
0251 #define SLIC_RX_BUFF_SIZE       2048
0252 #define SLIC_RX_BUFF_ALIGN      256
0253 #define SLIC_RX_BUFF_HDR_SIZE       34
0254 #define SLIC_MAX_REQ_RX_DESCS       1
0255
0256 #define SLIC_NUM_TX_DESCS       256
0257 #define SLIC_TX_DESC_ALIGN      32
0258 #define SLIC_MIN_TX_WAKEUP_DESCS    10
0259 #define SLIC_MAX_REQ_TX_DESCS       1
0260 #define SLIC_MAX_TX_COMPLETIONS     100
0261
0262 #define SLIC_NUM_STAT_DESCS     128
0263 #define SLIC_STATS_DESC_ALIGN       256
0264
0265 #define SLIC_NUM_STAT_DESC_ARRAYS   4
0266 #define SLIC_INVALID_STAT_DESC_IDX  0xffffffff
0267
0268 #define SLIC_UPR_LSTAT          0
0269 #define SLIC_UPR_CONFIG         1
0270
0271 #define SLIC_EEPROM_SIZE        128
0272 #define SLIC_EEPROM_MAGIC       0xa5a5
0273
0274 #define SLIC_FIRMWARE_MOJAVE        "slicoss/gbdownload.sys"
0275 #define SLIC_FIRMWARE_OASIS     "slicoss/oasisdownload.sys"
0276 #define SLIC_RCV_FIRMWARE_MOJAVE    "slicoss/gbrcvucode.sys"
0277 #define SLIC_RCV_FIRMWARE_OASIS     "slicoss/oasisrcvucode.sys"
0278 #define SLIC_FIRMWARE_MIN_SIZE      64
0279 #define SLIC_FIRMWARE_MAX_SECTIONS  3
0280
0281 #define SLIC_MODEL_MOJAVE       0
0282 #define SLIC_MODEL_OASIS        1
0283
0284 #define SLIC_INC_STATS_COUNTER(st, counter) \
0285 do {                        \
0286     u64_stats_update_begin(&(st)->syncp);   \
0287     (st)->counter++;            \
0288     u64_stats_update_end(&(st)->syncp); \
0289 } while (0)
0290
0291 #define SLIC_GET_STATS_COUNTER(newst, st, counter)          \
0292 {                                   \
0293     unsigned int start;                     \
0294     do {                            \
0295         start = u64_stats_fetch_begin_irq(&(st)->syncp);    \
0296         newst = (st)->counter;                  \
0297     } while (u64_stats_fetch_retry_irq(&(st)->syncp, start));   \
0298 }
0299
0300 struct slic_upr {
0301     dma_addr_t paddr;
0302     unsigned int type;
0303     struct list_head list;
0304 };
0305
0306 struct slic_upr_list {
0307     bool pending;
0308     struct list_head list;
0309     /* upr list lock */
0310     spinlock_t lock;
0311 };
0312
0313 /* SLIC EEPROM structure for Mojave */
0314 struct slic_mojave_eeprom {
0315     __le16 id;      /* 00 EEPROM/FLASH Magic code 'A5A5'*/
0316     __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
0317     __le16 flash_size;  /* 02 Flash size */
0318     __le16 eeprom_size; /* 03 EEPROM Size */
0319     __le16 vendor_id;   /* 04 Vendor ID */
0320     __le16 dev_id;      /* 05 Device ID */
0321     u8 rev_id;      /* 06 Revision ID */
0322     u8 class_code[3];   /* 07 Class Code */
0323     u8 irqpin_dbg;      /* 08 Debug Interrupt pin */
0324     u8 irqpin;      /*    Network Interrupt Pin */
0325     u8 min_grant;       /* 09 Minimum grant */
0326     u8 max_lat;     /*    Maximum Latency */
0327     __le16 pci_stat;    /* 10 PCI Status */
0328     __le16 sub_vendor_id;   /* 11 Subsystem Vendor Id */
0329     __le16 sub_id;      /* 12 Subsystem ID */
0330     __le16 dev_id_dbg;  /* 13 Debug Device Id */
0331     __le16 ramrom;      /* 14 Dram/Rom function */
0332     __le16 dram_size2pci;   /* 15 DRAM size to PCI (bytes * 64K) */
0333     __le16 rom_size2pci;    /* 16 ROM extension size to PCI (bytes * 4k) */
0334     u8 pad[2];      /* 17 Padding */
0335     u8 freetime;        /* 18 FreeTime setting */
0336     u8 ifctrl;      /* 10-bit interface control (Mojave only) */
0337     __le16 dram_size;   /* 19 DRAM size (bytes * 64k) */
0338     u8 mac[ETH_ALEN];   /* 20 MAC addresses */
0339     u8 mac2[ETH_ALEN];
0340     u8 pad2[6];
0341     u16 dev_id2;        /* Device ID for 2nd PCI function */
0342     u8 irqpin2;     /* Interrupt pin for 2nd PCI function */
0343     u8 class_code2[3];  /* Class Code for 2nd PCI function */
0344     u16 cfg_byte6;      /* Config Byte 6 */
0345     u16 pme_cap;        /* Power Mgment capabilities */
0346     u16 nwclk_ctrl;     /* NetworkClockControls */
0347     u8 fru_format;      /* Alacritech FRU format type */
0348     u8 fru_assembly[6]; /* Alacritech FRU information */
0349     u8 fru_rev[2];
0350     u8 fru_serial[14];
0351     u8 fru_pad[3];
0352     u8 oem_fru[28];     /* optional OEM FRU format type */
0353     u8 pad3[4];     /* Pad to 128 bytes - includes 2 cksum bytes
0354                  * (if OEM FRU info exists) and two unusable
0355                  * bytes at the end
0356                  */
0357 };
0358
0359 /* SLIC EEPROM structure for Oasis */
0360 struct slic_oasis_eeprom {
0361     __le16 id;      /* 00 EEPROM/FLASH Magic code 'A5A5' */
0362     __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
0363     __le16 spidev0_cfg; /* 02 Flash Config for SPI device 0 */
0364     __le16 spidev1_cfg; /* 03 Flash Config for SPI device 1 */
0365     __le16 vendor_id;   /* 04 Vendor ID */
0366     __le16 dev_id;      /* 05 Device ID (function 0) */
0367     u8 rev_id;      /* 06 Revision ID */
0368     u8 class_code0[3];  /* 07 Class Code for PCI function 0 */
0369     u8 irqpin1;     /* 08 Interrupt pin for PCI function 1*/
0370     u8 class_code1[3];  /* 09 Class Code for PCI function 1 */
0371     u8 irqpin2;     /* 10 Interrupt pin for PCI function 2*/
0372     u8 irqpin0;     /*    Interrupt pin for PCI function 0*/
0373     u8 min_grant;       /* 11 Minimum grant */
0374     u8 max_lat;     /*    Maximum Latency */
0375     __le16 sub_vendor_id;   /* 12 Subsystem Vendor Id */
0376     __le16 sub_id;      /* 13 Subsystem ID */
0377     __le16 flash_size;  /* 14 Flash size (bytes / 4K) */
0378     __le16 dram_size2pci;   /* 15 DRAM size to PCI (bytes / 64K) */
0379     __le16 rom_size2pci;    /* 16 Flash (ROM extension) size to PCI
0380                  *   (bytes / 4K)
0381                  */
0382     __le16 dev_id1;     /* 17 Device Id (function 1) */
0383     __le16 dev_id2;     /* 18 Device Id (function 2) */
0384     __le16 dev_stat_cfg;    /* 19 Device Status Config Bytes 6-7 */
0385     __le16 pme_cap;     /* 20 Power Mgment capabilities */
0386     u8 msi_cap;     /* 21 MSI capabilities */
0387     u8 clock_div;       /*    Clock divider */
0388     __le16 pci_stat_lo; /* 22 PCI Status bits 15:0 */
0389     __le16 pci_stat_hi; /* 23 PCI Status bits 31:16 */
0390     __le16 dram_cfg_lo; /* 24 DRAM Configuration bits 15:0 */
0391     __le16 dram_cfg_hi; /* 25 DRAM Configuration bits 31:16 */
0392     __le16 dram_size;   /* 26 DRAM size (bytes / 64K) */
0393     __le16 gpio_tbi_ctrl;   /* 27 GPIO/TBI controls for functions 1/0 */
0394     __le16 eeprom_size; /* 28 EEPROM Size */
0395     u8 mac[ETH_ALEN];   /* 29 MAC addresses (2 ports) */
0396     u8 mac2[ETH_ALEN];
0397     u8 fru_format;      /* 35 Alacritech FRU format type */
0398     u8 fru_assembly[6]; /* Alacritech FRU information */
0399     u8 fru_rev[2];
0400     u8 fru_serial[14];
0401     u8 fru_pad[3];
0402     u8 oem_fru[28];     /* optional OEM FRU information */
0403     u8 pad[4];      /* Pad to 128 bytes - includes 2 checksum bytes
0404                  * (if OEM FRU info exists) and two unusable
0405                  * bytes at the end
0406                  */
0407 };
0408
0409 struct slic_stats {
0410     u64 rx_packets;
0411     u64 rx_bytes;
0412     u64 rx_mcasts;
0413     u64 rx_errors;
0414     u64 tx_packets;
0415     u64 tx_bytes;
0416     /* HW STATS */
0417     u64 rx_buff_miss;
0418     u64 tx_dropped;
0419     u64 irq_errs;
0420     /* transport layer */
0421     u64 rx_tpcsum;
0422     u64 rx_tpoflow;
0423     u64 rx_tphlen;
0424     /* ip layer */
0425     u64 rx_ipcsum;
0426     u64 rx_iplen;
0427     u64 rx_iphlen;
0428     /* link layer */
0429     u64 rx_early;
0430     u64 rx_buffoflow;
0431     u64 rx_lcode;
0432     u64 rx_drbl;
0433     u64 rx_crc;
0434     u64 rx_oflow802;
0435     u64 rx_uflow802;
0436     /* oasis only */
0437     u64 tx_carrier;
0438     struct u64_stats_sync syncp;
0439 };
0440
0441 struct slic_shmem_data {
0442     __le32 isr;
0443     __le32 link;
0444 };
0445
0446 struct slic_shmem {
0447     dma_addr_t isr_paddr;
0448     dma_addr_t link_paddr;
0449     struct slic_shmem_data *shmem_data;
0450 };
0451
0452 struct slic_rx_info_oasis {
0453     __le32 frame_status;
0454     __le32 frame_status_b;
0455     __le32 time_stamp;
0456     __le32 checksum;
0457 };
0458
0459 struct slic_rx_info_mojave {
0460     __le32 frame_status;
0461     __le16 byte_cnt;
0462     __le16 tp_chksum;
0463     __le16 ctx_hash;
0464     __le16 mac_hash;
0465     __le16 buff_lnk;
0466 };
0467
0468 struct slic_stat_desc {
0469     __le32 hnd;
0470     __u8 pad[8];
0471     __le32 status;
0472     __u8 pad2[16];
0473 };
0474
0475 struct slic_stat_queue {
0476     struct slic_stat_desc *descs[SLIC_NUM_STAT_DESC_ARRAYS];
0477     dma_addr_t paddr[SLIC_NUM_STAT_DESC_ARRAYS];
0478     unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS];
0479     unsigned int active_array;
0480     unsigned int len;
0481     unsigned int done_idx;
0482     size_t mem_size;
0483 };
0484
0485 struct slic_tx_desc {
0486     __le32 hnd;
0487     __le32 rsvd;
0488     u8 cmd;
0489     u8 flags;
0490     __le16 rsvd2;
0491     __le32 totlen;
0492     __le32 paddrl;
0493     __le32 paddrh;
0494     __le32 len;
0495     __le32 type;
0496 };
0497
0498 struct slic_tx_buffer {
0499     struct sk_buff *skb;
0500     DEFINE_DMA_UNMAP_ADDR(map_addr);
0501     DEFINE_DMA_UNMAP_LEN(map_len);
0502     struct slic_tx_desc *desc;
0503     dma_addr_t desc_paddr;
0504 };
0505
0506 struct slic_tx_queue {
0507     struct dma_pool *dma_pool;
0508     struct slic_tx_buffer *txbuffs;
0509     unsigned int len;
0510     unsigned int put_idx;
0511     unsigned int done_idx;
0512 };
0513
0514 struct slic_rx_desc {
0515     u8 pad[16];
0516     __le32 buffer;
0517     __le32 length;
0518     __le32 status;
0519 };
0520
0521 struct slic_rx_buffer {
0522     struct sk_buff *skb;
0523     DEFINE_DMA_UNMAP_ADDR(map_addr);
0524     DEFINE_DMA_UNMAP_LEN(map_len);
0525     unsigned int addr_offset;
0526 };
0527
0528 struct slic_rx_queue {
0529     struct slic_rx_buffer *rxbuffs;
0530     unsigned int len;
0531     unsigned int done_idx;
0532     unsigned int put_idx;
0533 };
0534
0535 struct slic_device {
0536     struct pci_dev *pdev;
0537     struct net_device *netdev;
0538     void __iomem *regs;
0539     /* upper address setting lock */
0540     spinlock_t upper_lock;
0541     struct slic_shmem shmem;
0542     struct napi_struct napi;
0543     struct slic_rx_queue rxq;
0544     struct slic_tx_queue txq;
0545     struct slic_stat_queue stq;
0546     struct slic_stats stats;
0547     struct slic_upr_list upr_list;
0548     /* link configuration lock */
0549     spinlock_t link_lock;
0550     bool promisc;
0551     int speed;
0552     unsigned int duplex;
0553     bool is_fiber;
0554     unsigned char model;
0555 };
0556
0557 static inline u32 slic_read(struct slic_device *sdev, unsigned int reg)
0558 {
0559     return ioread32(sdev->regs + reg);
0560 }
0561
0562 static inline void slic_write(struct slic_device *sdev, unsigned int reg,
0563                   u32 val)
0564 {
0565     iowrite32(val, sdev->regs + reg);
0566 }
0567
0568 static inline void slic_flush_write(struct slic_device *sdev)
0569 {
0570     (void)ioread32(sdev->regs + SLIC_REG_HOSTID);
0571 }
0572
0573 #endif /* _SLIC_H */