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0001 /* typhoon.h:   chip info for the 3Com 3CR990 family of controllers */
0002 /*
0003     Written 2002-2003 by David Dillow <dave@thedillows.org>
0004 
0005     This software may be used and distributed according to the terms of
0006     the GNU General Public License (GPL), incorporated herein by reference.
0007     Drivers based on or derived from this code fall under the GPL and must
0008     retain the authorship, copyright and license notice.  This file is not
0009     a complete program and may only be used when the entire operating
0010     system is licensed under the GPL.
0011 
0012     This software is available on a public web site. It may enable
0013     cryptographic capabilities of the 3Com hardware, and may be
0014     exported from the United States under License Exception "TSU"
0015     pursuant to 15 C.F.R. Section 740.13(e).
0016 
0017     This work was funded by the National Library of Medicine under
0018     the Department of Energy project number 0274DD06D1 and NLM project
0019     number Y1-LM-2015-01.
0020 */
0021 
0022 /* All Typhoon ring positions are specificed in bytes, and point to the
0023  * first "clean" entry in the ring -- ie the next entry we use for whatever
0024  * purpose.
0025  */
0026 
0027 /* The Typhoon basic ring
0028  * ringBase:  where this ring lives (our virtual address)
0029  * lastWrite: the next entry we'll use
0030  */
0031 struct basic_ring {
0032     u8 *ringBase;
0033     u32 lastWrite;
0034 };
0035 
0036 /* The Typhoon transmit ring -- same as a basic ring, plus:
0037  * lastRead:      where we're at in regard to cleaning up the ring
0038  * writeRegister: register to use for writing (different for Hi & Lo rings)
0039  */
0040 struct transmit_ring {
0041     u8 *ringBase;
0042     u32 lastWrite;
0043     u32 lastRead;
0044     int writeRegister;
0045 };
0046 
0047 /* The host<->Typhoon ring index structure
0048  * This indicates the current positions in the rings
0049  *
0050  * All values must be in little endian format for the 3XP
0051  *
0052  * rxHiCleared:   entry we've cleared to in the Hi receive ring
0053  * rxLoCleared:   entry we've cleared to in the Lo receive ring
0054  * rxBuffReady:   next entry we'll put a free buffer in
0055  * respCleared:   entry we've cleared to in the response ring
0056  *
0057  * txLoCleared:   entry the NIC has cleared to in the Lo transmit ring
0058  * txHiCleared:   entry the NIC has cleared to in the Hi transmit ring
0059  * rxLoReady:     entry the NIC has filled to in the Lo receive ring
0060  * rxBuffCleared: entry the NIC has cleared in the free buffer ring
0061  * cmdCleared:    entry the NIC has cleared in the command ring
0062  * respReady:     entry the NIC has filled to in the response ring
0063  * rxHiReady:     entry the NIC has filled to in the Hi receive ring
0064  */
0065 struct typhoon_indexes {
0066     /* The first four are written by the host, and read by the NIC */
0067     volatile __le32 rxHiCleared;
0068     volatile __le32 rxLoCleared;
0069     volatile __le32 rxBuffReady;
0070     volatile __le32 respCleared;
0071 
0072     /* The remaining are written by the NIC, and read by the host */
0073     volatile __le32 txLoCleared;
0074     volatile __le32 txHiCleared;
0075     volatile __le32 rxLoReady;
0076     volatile __le32 rxBuffCleared;
0077     volatile __le32 cmdCleared;
0078     volatile __le32 respReady;
0079     volatile __le32 rxHiReady;
0080 } __packed;
0081 
0082 /* The host<->Typhoon interface
0083  * Our means of communicating where things are
0084  *
0085  * All values must be in little endian format for the 3XP
0086  *
0087  * ringIndex:   64 bit bus address of the index structure
0088  * txLoAddr:    64 bit bus address of the Lo transmit ring
0089  * txLoSize:    size (in bytes) of the Lo transmit ring
0090  * txHi*:       as above for the Hi priority transmit ring
0091  * rxLo*:       as above for the Lo priority receive ring
0092  * rxBuff*:     as above for the free buffer ring
0093  * cmd*:        as above for the command ring
0094  * resp*:       as above for the response ring
0095  * zeroAddr:    64 bit bus address of a zero word (for DMA)
0096  * rxHi*:       as above for the Hi Priority receive ring
0097  *
0098  * While there is room for 64 bit addresses, current versions of the 3XP
0099  * only do 32 bit addresses, so the *Hi for each of the above will always
0100  * be zero.
0101  */
0102 struct typhoon_interface {
0103     __le32 ringIndex;
0104     __le32 ringIndexHi;
0105     __le32 txLoAddr;
0106     __le32 txLoAddrHi;
0107     __le32 txLoSize;
0108     __le32 txHiAddr;
0109     __le32 txHiAddrHi;
0110     __le32 txHiSize;
0111     __le32 rxLoAddr;
0112     __le32 rxLoAddrHi;
0113     __le32 rxLoSize;
0114     __le32 rxBuffAddr;
0115     __le32 rxBuffAddrHi;
0116     __le32 rxBuffSize;
0117     __le32 cmdAddr;
0118     __le32 cmdAddrHi;
0119     __le32 cmdSize;
0120     __le32 respAddr;
0121     __le32 respAddrHi;
0122     __le32 respSize;
0123     __le32 zeroAddr;
0124     __le32 zeroAddrHi;
0125     __le32 rxHiAddr;
0126     __le32 rxHiAddrHi;
0127     __le32 rxHiSize;
0128 } __packed;
0129 
0130 /* The Typhoon transmit/fragment descriptor
0131  *
0132  * A packet is described by a packet descriptor, followed by option descriptors,
0133  * if any, then one or more fragment descriptors.
0134  *
0135  * Packet descriptor:
0136  * flags:   Descriptor type
0137  * len:i    zero, or length of this packet
0138  * addr*:   8 bytes of opaque data to the firmware -- for skb pointer
0139  * processFlags: Determine offload tasks to perform on this packet.
0140  *
0141  * Fragment descriptor:
0142  * flags:   Descriptor type
0143  * len:i    length of this fragment
0144  * addr:    low bytes of DMA address for this part of the packet
0145  * addrHi:  hi bytes of DMA address for this part of the packet
0146  * processFlags: must be zero
0147  *
0148  * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux
0149  * driver uses it.
0150  */
0151 struct tx_desc {
0152     u8  flags;
0153 #define TYPHOON_TYPE_MASK   0x07
0154 #define     TYPHOON_FRAG_DESC   0x00
0155 #define     TYPHOON_TX_DESC     0x01
0156 #define     TYPHOON_CMD_DESC    0x02
0157 #define     TYPHOON_OPT_DESC    0x03
0158 #define     TYPHOON_RX_DESC     0x04
0159 #define     TYPHOON_RESP_DESC   0x05
0160 #define TYPHOON_OPT_TYPE_MASK   0xf0
0161 #define     TYPHOON_OPT_IPSEC   0x00
0162 #define     TYPHOON_OPT_TCP_SEG 0x10
0163 #define TYPHOON_CMD_RESPOND 0x40
0164 #define TYPHOON_RESP_ERROR  0x40
0165 #define TYPHOON_RX_ERROR    0x40
0166 #define TYPHOON_DESC_VALID  0x80
0167     u8  numDesc;
0168     __le16 len;
0169     union {
0170         struct {
0171             __le32 addr;
0172             __le32 addrHi;
0173         } frag;
0174         u64 tx_addr;    /* opaque for hardware, for TX_DESC */
0175     };
0176     __le32 processFlags;
0177 #define TYPHOON_TX_PF_NO_CRC        cpu_to_le32(0x00000001)
0178 #define TYPHOON_TX_PF_IP_CHKSUM     cpu_to_le32(0x00000002)
0179 #define TYPHOON_TX_PF_TCP_CHKSUM    cpu_to_le32(0x00000004)
0180 #define TYPHOON_TX_PF_TCP_SEGMENT   cpu_to_le32(0x00000008)
0181 #define TYPHOON_TX_PF_INSERT_VLAN   cpu_to_le32(0x00000010)
0182 #define TYPHOON_TX_PF_IPSEC     cpu_to_le32(0x00000020)
0183 #define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040)
0184 #define TYPHOON_TX_PF_UDP_CHKSUM    cpu_to_le32(0x00000080)
0185 #define TYPHOON_TX_PF_PAD_FRAME     cpu_to_le32(0x00000100)
0186 #define TYPHOON_TX_PF_RESERVED      cpu_to_le32(0x00000e00)
0187 #define TYPHOON_TX_PF_VLAN_MASK     cpu_to_le32(0x0ffff000)
0188 #define TYPHOON_TX_PF_INTERNAL      cpu_to_le32(0xf0000000)
0189 #define TYPHOON_TX_PF_VLAN_TAG_SHIFT    12
0190 } __packed;
0191 
0192 /* The TCP Segmentation offload option descriptor
0193  *
0194  * flags:   descriptor type
0195  * numDesc: must be 1
0196  * mss_flags:   bits 0-11 (little endian) are MSS, 12 is first TSO descriptor
0197  *          13 is list TSO descriptor, set both if only one TSO
0198  * respAddrLo:  low bytes of address of the bytesTx field of this descriptor
0199  * bytesTx: total number of bytes in this TSO request
0200  * status:  0 on completion
0201  */
0202 struct tcpopt_desc {
0203     u8  flags;
0204     u8  numDesc;
0205     __le16 mss_flags;
0206 #define TYPHOON_TSO_FIRST       cpu_to_le16(0x1000)
0207 #define TYPHOON_TSO_LAST        cpu_to_le16(0x2000)
0208     __le32 respAddrLo;
0209     __le32 bytesTx;
0210     __le32 status;
0211 } __packed;
0212 
0213 /* The IPSEC Offload descriptor
0214  *
0215  * flags:   descriptor type
0216  * numDesc: must be 1
0217  * ipsecFlags:  bit 0: 0 -- generate IV, 1 -- use supplied IV
0218  * sa1, sa2:    Security Association IDs for this packet
0219  * reserved:    set to 0
0220  */
0221 struct ipsec_desc {
0222     u8  flags;
0223     u8  numDesc;
0224     __le16 ipsecFlags;
0225 #define TYPHOON_IPSEC_GEN_IV    cpu_to_le16(0x0000)
0226 #define TYPHOON_IPSEC_USE_IV    cpu_to_le16(0x0001)
0227     __le32 sa1;
0228     __le32 sa2;
0229     __le32 reserved;
0230 } __packed;
0231 
0232 /* The Typhoon receive descriptor (Updated by NIC)
0233  *
0234  * flags:         Descriptor type, error indication
0235  * numDesc:       Always zero
0236  * frameLen:      the size of the packet received
0237  * addr:          low 32 bytes of the virtual addr passed in for this buffer
0238  * addrHi:        high 32 bytes of the virtual addr passed in for this buffer
0239  * rxStatus:      Error if set in flags, otherwise result of offload processing
0240  * filterResults: results of filtering on packet, not used
0241  * ipsecResults:  Results of IPSEC processing
0242  * vlanTag:       the 801.2q TCI from the packet
0243  */
0244 struct rx_desc {
0245     u8  flags;
0246     u8  numDesc;
0247     __le16 frameLen;
0248     u32 addr;   /* opaque, comes from virtAddr */
0249     u32 addrHi; /* opaque, comes from virtAddrHi */
0250     __le32 rxStatus;
0251 #define TYPHOON_RX_ERR_INTERNAL     cpu_to_le32(0x00000000)
0252 #define TYPHOON_RX_ERR_FIFO_UNDERRUN    cpu_to_le32(0x00000001)
0253 #define TYPHOON_RX_ERR_BAD_SSD      cpu_to_le32(0x00000002)
0254 #define TYPHOON_RX_ERR_RUNT     cpu_to_le32(0x00000003)
0255 #define TYPHOON_RX_ERR_CRC      cpu_to_le32(0x00000004)
0256 #define TYPHOON_RX_ERR_OVERSIZE     cpu_to_le32(0x00000005)
0257 #define TYPHOON_RX_ERR_ALIGN        cpu_to_le32(0x00000006)
0258 #define TYPHOON_RX_ERR_DRIBBLE      cpu_to_le32(0x00000007)
0259 #define TYPHOON_RX_PROTO_MASK       cpu_to_le32(0x00000003)
0260 #define TYPHOON_RX_PROTO_UNKNOWN    cpu_to_le32(0x00000000)
0261 #define TYPHOON_RX_PROTO_IP     cpu_to_le32(0x00000001)
0262 #define TYPHOON_RX_PROTO_IPX        cpu_to_le32(0x00000002)
0263 #define TYPHOON_RX_VLAN         cpu_to_le32(0x00000004)
0264 #define TYPHOON_RX_IP_FRAG      cpu_to_le32(0x00000008)
0265 #define TYPHOON_RX_IPSEC        cpu_to_le32(0x00000010)
0266 #define TYPHOON_RX_IP_CHK_FAIL      cpu_to_le32(0x00000020)
0267 #define TYPHOON_RX_TCP_CHK_FAIL     cpu_to_le32(0x00000040)
0268 #define TYPHOON_RX_UDP_CHK_FAIL     cpu_to_le32(0x00000080)
0269 #define TYPHOON_RX_IP_CHK_GOOD      cpu_to_le32(0x00000100)
0270 #define TYPHOON_RX_TCP_CHK_GOOD     cpu_to_le32(0x00000200)
0271 #define TYPHOON_RX_UDP_CHK_GOOD     cpu_to_le32(0x00000400)
0272     __le16 filterResults;
0273 #define TYPHOON_RX_FILTER_MASK      cpu_to_le16(0x7fff)
0274 #define TYPHOON_RX_FILTERED     cpu_to_le16(0x8000)
0275     __le16 ipsecResults;
0276 #define TYPHOON_RX_OUTER_AH_GOOD    cpu_to_le16(0x0001)
0277 #define TYPHOON_RX_OUTER_ESP_GOOD   cpu_to_le16(0x0002)
0278 #define TYPHOON_RX_INNER_AH_GOOD    cpu_to_le16(0x0004)
0279 #define TYPHOON_RX_INNER_ESP_GOOD   cpu_to_le16(0x0008)
0280 #define TYPHOON_RX_OUTER_AH_FAIL    cpu_to_le16(0x0010)
0281 #define TYPHOON_RX_OUTER_ESP_FAIL   cpu_to_le16(0x0020)
0282 #define TYPHOON_RX_INNER_AH_FAIL    cpu_to_le16(0x0040)
0283 #define TYPHOON_RX_INNER_ESP_FAIL   cpu_to_le16(0x0080)
0284 #define TYPHOON_RX_UNKNOWN_SA       cpu_to_le16(0x0100)
0285 #define TYPHOON_RX_ESP_FORMAT_ERR   cpu_to_le16(0x0200)
0286     __be32 vlanTag;
0287 } __packed;
0288 
0289 /* The Typhoon free buffer descriptor, used to give a buffer to the NIC
0290  *
0291  * physAddr:    low 32 bits of the bus address of the buffer
0292  * physAddrHi:  high 32 bits of the bus address of the buffer, always zero
0293  * virtAddr:    low 32 bits of the skb address
0294  * virtAddrHi:  high 32 bits of the skb address, always zero
0295  *
0296  * the virt* address is basically two 32 bit cookies, just passed back
0297  * from the NIC
0298  */
0299 struct rx_free {
0300     __le32 physAddr;
0301     __le32 physAddrHi;
0302     u32 virtAddr;
0303     u32 virtAddrHi;
0304 } __packed;
0305 
0306 /* The Typhoon command descriptor, used for commands and responses
0307  *
0308  * flags:   descriptor type
0309  * numDesc: number of descriptors following in this command/response,
0310  *              ie, zero for a one descriptor command
0311  * cmd:     the command
0312  * seqNo:   sequence number (unused)
0313  * parm1:   use varies by command
0314  * parm2:   use varies by command
0315  * parm3:   use varies by command
0316  */
0317 struct cmd_desc {
0318     u8  flags;
0319     u8  numDesc;
0320     __le16 cmd;
0321 #define TYPHOON_CMD_TX_ENABLE       cpu_to_le16(0x0001)
0322 #define TYPHOON_CMD_TX_DISABLE      cpu_to_le16(0x0002)
0323 #define TYPHOON_CMD_RX_ENABLE       cpu_to_le16(0x0003)
0324 #define TYPHOON_CMD_RX_DISABLE      cpu_to_le16(0x0004)
0325 #define TYPHOON_CMD_SET_RX_FILTER   cpu_to_le16(0x0005)
0326 #define TYPHOON_CMD_READ_STATS      cpu_to_le16(0x0007)
0327 #define TYPHOON_CMD_XCVR_SELECT     cpu_to_le16(0x0013)
0328 #define TYPHOON_CMD_SET_MAX_PKT_SIZE    cpu_to_le16(0x001a)
0329 #define TYPHOON_CMD_READ_MEDIA_STATUS   cpu_to_le16(0x001b)
0330 #define TYPHOON_CMD_GOTO_SLEEP      cpu_to_le16(0x0023)
0331 #define TYPHOON_CMD_SET_MULTICAST_HASH  cpu_to_le16(0x0025)
0332 #define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026)
0333 #define TYPHOON_CMD_READ_MAC_ADDRESS    cpu_to_le16(0x0027)
0334 #define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b)
0335 #define TYPHOON_CMD_CREATE_SA       cpu_to_le16(0x0034)
0336 #define TYPHOON_CMD_DELETE_SA       cpu_to_le16(0x0035)
0337 #define TYPHOON_CMD_READ_VERSIONS   cpu_to_le16(0x0043)
0338 #define TYPHOON_CMD_IRQ_COALESCE_CTRL   cpu_to_le16(0x0045)
0339 #define TYPHOON_CMD_ENABLE_WAKE_EVENTS  cpu_to_le16(0x0049)
0340 #define TYPHOON_CMD_SET_OFFLOAD_TASKS   cpu_to_le16(0x004f)
0341 #define TYPHOON_CMD_HELLO_RESP      cpu_to_le16(0x0057)
0342 #define TYPHOON_CMD_HALT        cpu_to_le16(0x005d)
0343 #define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e)
0344 #define TYPHOON_CMD_GET_IPSEC_ENABLE    cpu_to_le16(0x0067)
0345 #define TYPHOON_CMD_GET_CMD_LVL     cpu_to_le16(0x0069)
0346     u16 seqNo;
0347     __le16 parm1;
0348     __le32 parm2;
0349     __le32 parm3;
0350 } __packed;
0351 
0352 /* The Typhoon response descriptor, see command descriptor for details
0353  */
0354 struct resp_desc {
0355     u8  flags;
0356     u8  numDesc;
0357     __le16 cmd;
0358     __le16 seqNo;
0359     __le16 parm1;
0360     __le32 parm2;
0361     __le32 parm3;
0362 } __packed;
0363 
0364 #define INIT_COMMAND_NO_RESPONSE(x, command)                \
0365     do { struct cmd_desc *_ptr = (x);               \
0366         memset(_ptr, 0, sizeof(struct cmd_desc));       \
0367         _ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID;    \
0368         _ptr->cmd = command;                    \
0369     } while (0)
0370 
0371 /* We set seqNo to 1 if we're expecting a response from this command */
0372 #define INIT_COMMAND_WITH_RESPONSE(x, command)              \
0373     do { struct cmd_desc *_ptr = (x);               \
0374         memset(_ptr, 0, sizeof(struct cmd_desc));       \
0375         _ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC;   \
0376         _ptr->flags |= TYPHOON_DESC_VALID;          \
0377         _ptr->cmd = command;                    \
0378         _ptr->seqNo = 1;                    \
0379     } while (0)
0380 
0381 /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1)
0382  */
0383 #define TYPHOON_RX_FILTER_DIRECTED  cpu_to_le16(0x0001)
0384 #define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002)
0385 #define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004)
0386 #define TYPHOON_RX_FILTER_PROMISCOUS    cpu_to_le16(0x0008)
0387 #define TYPHOON_RX_FILTER_MCAST_HASH    cpu_to_le16(0x0010)
0388 
0389 /* TYPHOON_CMD_READ_STATS response format
0390  */
0391 struct stats_resp {
0392     u8  flags;
0393     u8  numDesc;
0394     __le16 cmd;
0395     __le16 seqNo;
0396     __le16 unused;
0397     __le32 txPackets;
0398     __le64 txBytes;
0399     __le32 txDeferred;
0400     __le32 txLateCollisions;
0401     __le32 txCollisions;
0402     __le32 txCarrierLost;
0403     __le32 txMultipleCollisions;
0404     __le32 txExcessiveCollisions;
0405     __le32 txFifoUnderruns;
0406     __le32 txMulticastTxOverflows;
0407     __le32 txFiltered;
0408     __le32 rxPacketsGood;
0409     __le64 rxBytesGood;
0410     __le32 rxFifoOverruns;
0411     __le32 BadSSD;
0412     __le32 rxCrcErrors;
0413     __le32 rxOversized;
0414     __le32 rxBroadcast;
0415     __le32 rxMulticast;
0416     __le32 rxOverflow;
0417     __le32 rxFiltered;
0418     __le32 linkStatus;
0419 #define TYPHOON_LINK_STAT_MASK      cpu_to_le32(0x00000001)
0420 #define TYPHOON_LINK_GOOD       cpu_to_le32(0x00000001)
0421 #define TYPHOON_LINK_BAD        cpu_to_le32(0x00000000)
0422 #define TYPHOON_LINK_SPEED_MASK     cpu_to_le32(0x00000002)
0423 #define TYPHOON_LINK_100MBPS        cpu_to_le32(0x00000002)
0424 #define TYPHOON_LINK_10MBPS     cpu_to_le32(0x00000000)
0425 #define TYPHOON_LINK_DUPLEX_MASK    cpu_to_le32(0x00000004)
0426 #define TYPHOON_LINK_FULL_DUPLEX    cpu_to_le32(0x00000004)
0427 #define TYPHOON_LINK_HALF_DUPLEX    cpu_to_le32(0x00000000)
0428     __le32 unused2;
0429     __le32 unused3;
0430 } __packed;
0431 
0432 /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1)
0433  */
0434 #define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000)
0435 #define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001)
0436 #define TYPHOON_XCVR_100HALF    cpu_to_le16(0x0002)
0437 #define TYPHOON_XCVR_100FULL    cpu_to_le16(0x0003)
0438 #define TYPHOON_XCVR_AUTONEG    cpu_to_le16(0x0004)
0439 
0440 /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1)
0441  */
0442 #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE    cpu_to_le16(0x0004)
0443 #define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010)
0444 #define TYPHOON_MEDIA_STAT_CARRIER_SENSE    cpu_to_le16(0x0020)
0445 #define TYPHOON_MEDIA_STAT_POLARITY_REV     cpu_to_le16(0x0400)
0446 #define TYPHOON_MEDIA_STAT_NO_LINK      cpu_to_le16(0x0800)
0447 
0448 /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1)
0449  */
0450 #define TYPHOON_MCAST_HASH_DISABLE  cpu_to_le16(0x0000)
0451 #define TYPHOON_MCAST_HASH_ENABLE   cpu_to_le16(0x0001)
0452 #define TYPHOON_MCAST_HASH_SET      cpu_to_le16(0x0002)
0453 
0454 /* TYPHOON_CMD_CREATE_SA descriptor and settings
0455  */
0456 struct sa_descriptor {
0457     u8  flags;
0458     u8  numDesc;
0459     u16 cmd;
0460     u16 seqNo;
0461     u16 mode;
0462 #define TYPHOON_SA_MODE_NULL        cpu_to_le16(0x0000)
0463 #define TYPHOON_SA_MODE_AH      cpu_to_le16(0x0001)
0464 #define TYPHOON_SA_MODE_ESP     cpu_to_le16(0x0002)
0465     u8  hashFlags;
0466 #define TYPHOON_SA_HASH_ENABLE      0x01
0467 #define TYPHOON_SA_HASH_SHA1        0x02
0468 #define TYPHOON_SA_HASH_MD5     0x04
0469     u8  direction;
0470 #define TYPHOON_SA_DIR_RX       0x00
0471 #define TYPHOON_SA_DIR_TX       0x01
0472     u8  encryptionFlags;
0473 #define TYPHOON_SA_ENCRYPT_ENABLE   0x01
0474 #define TYPHOON_SA_ENCRYPT_DES      0x02
0475 #define TYPHOON_SA_ENCRYPT_3DES     0x00
0476 #define TYPHOON_SA_ENCRYPT_3DES_2KEY    0x00
0477 #define TYPHOON_SA_ENCRYPT_3DES_3KEY    0x04
0478 #define TYPHOON_SA_ENCRYPT_CBC      0x08
0479 #define TYPHOON_SA_ENCRYPT_ECB      0x00
0480     u8  specifyIndex;
0481 #define TYPHOON_SA_SPECIFY_INDEX    0x01
0482 #define TYPHOON_SA_GENERATE_INDEX   0x00
0483     u32 SPI;
0484     u32 destAddr;
0485     u32 destMask;
0486     u8  integKey[20];
0487     u8  confKey[24];
0488     u32 index;
0489     u32 unused;
0490     u32 unused2;
0491 } __packed;
0492 
0493 /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx))
0494  * This is all for IPv4.
0495  */
0496 #define TYPHOON_OFFLOAD_TCP_CHKSUM  cpu_to_le32(0x00000002)
0497 #define TYPHOON_OFFLOAD_UDP_CHKSUM  cpu_to_le32(0x00000004)
0498 #define TYPHOON_OFFLOAD_IP_CHKSUM   cpu_to_le32(0x00000008)
0499 #define TYPHOON_OFFLOAD_IPSEC       cpu_to_le32(0x00000010)
0500 #define TYPHOON_OFFLOAD_BCAST_THROTTLE  cpu_to_le32(0x00000020)
0501 #define TYPHOON_OFFLOAD_DHCP_PREVENT    cpu_to_le32(0x00000040)
0502 #define TYPHOON_OFFLOAD_VLAN        cpu_to_le32(0x00000080)
0503 #define TYPHOON_OFFLOAD_FILTERING   cpu_to_le32(0x00000100)
0504 #define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200)
0505 
0506 /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1)
0507  */
0508 #define TYPHOON_WAKE_MAGIC_PKT      cpu_to_le16(0x01)
0509 #define TYPHOON_WAKE_LINK_EVENT     cpu_to_le16(0x02)
0510 #define TYPHOON_WAKE_ICMP_ECHO      cpu_to_le16(0x04)
0511 #define TYPHOON_WAKE_ARP        cpu_to_le16(0x08)
0512 
0513 /* These are used to load the firmware image on the NIC
0514  */
0515 struct typhoon_file_header {
0516     u8  tag[8];
0517     __le32 version;
0518     __le32 numSections;
0519     __le32 startAddr;
0520     __le32 hmacDigest[5];
0521 } __packed;
0522 
0523 struct typhoon_section_header {
0524     __le32 len;
0525     u16 checksum;
0526     u16 reserved;
0527     __le32 startAddr;
0528 } __packed;
0529 
0530 /* The Typhoon Register offsets
0531  */
0532 #define TYPHOON_REG_SOFT_RESET          0x00
0533 #define TYPHOON_REG_INTR_STATUS         0x04
0534 #define TYPHOON_REG_INTR_ENABLE         0x08
0535 #define TYPHOON_REG_INTR_MASK           0x0c
0536 #define TYPHOON_REG_SELF_INTERRUPT      0x10
0537 #define TYPHOON_REG_HOST2ARM7           0x14
0538 #define TYPHOON_REG_HOST2ARM6           0x18
0539 #define TYPHOON_REG_HOST2ARM5           0x1c
0540 #define TYPHOON_REG_HOST2ARM4           0x20
0541 #define TYPHOON_REG_HOST2ARM3           0x24
0542 #define TYPHOON_REG_HOST2ARM2           0x28
0543 #define TYPHOON_REG_HOST2ARM1           0x2c
0544 #define TYPHOON_REG_HOST2ARM0           0x30
0545 #define TYPHOON_REG_ARM2HOST3           0x34
0546 #define TYPHOON_REG_ARM2HOST2           0x38
0547 #define TYPHOON_REG_ARM2HOST1           0x3c
0548 #define TYPHOON_REG_ARM2HOST0           0x40
0549 
0550 #define TYPHOON_REG_BOOT_DATA_LO        TYPHOON_REG_HOST2ARM5
0551 #define TYPHOON_REG_BOOT_DATA_HI        TYPHOON_REG_HOST2ARM4
0552 #define TYPHOON_REG_BOOT_DEST_ADDR      TYPHOON_REG_HOST2ARM3
0553 #define TYPHOON_REG_BOOT_CHECKSUM       TYPHOON_REG_HOST2ARM2
0554 #define TYPHOON_REG_BOOT_LENGTH         TYPHOON_REG_HOST2ARM1
0555 
0556 #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR      TYPHOON_REG_HOST2ARM1
0557 #define TYPHOON_REG_DOWNLOAD_HMAC_0     TYPHOON_REG_HOST2ARM2
0558 #define TYPHOON_REG_DOWNLOAD_HMAC_1     TYPHOON_REG_HOST2ARM3
0559 #define TYPHOON_REG_DOWNLOAD_HMAC_2     TYPHOON_REG_HOST2ARM4
0560 #define TYPHOON_REG_DOWNLOAD_HMAC_3     TYPHOON_REG_HOST2ARM5
0561 #define TYPHOON_REG_DOWNLOAD_HMAC_4     TYPHOON_REG_HOST2ARM6
0562 
0563 #define TYPHOON_REG_BOOT_RECORD_ADDR_HI     TYPHOON_REG_HOST2ARM2
0564 #define TYPHOON_REG_BOOT_RECORD_ADDR_LO     TYPHOON_REG_HOST2ARM1
0565 
0566 #define TYPHOON_REG_TX_LO_READY         TYPHOON_REG_HOST2ARM3
0567 #define TYPHOON_REG_CMD_READY           TYPHOON_REG_HOST2ARM2
0568 #define TYPHOON_REG_TX_HI_READY         TYPHOON_REG_HOST2ARM1
0569 
0570 #define TYPHOON_REG_COMMAND         TYPHOON_REG_HOST2ARM0
0571 #define TYPHOON_REG_HEARTBEAT           TYPHOON_REG_ARM2HOST3
0572 #define TYPHOON_REG_STATUS          TYPHOON_REG_ARM2HOST0
0573 
0574 /* 3XP Reset values (TYPHOON_REG_SOFT_RESET)
0575  */
0576 #define TYPHOON_RESET_ALL   0x7f
0577 #define TYPHOON_RESET_NONE  0x00
0578 
0579 /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK})
0580  *
0581  * Some of these came from OpenBSD, as the 3Com docs have it wrong
0582  * (INTR_SELF) or don't list it at all (INTR_*_ABORT)
0583  *
0584  * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq
0585  * about every 8ms, so don't do it.
0586  */
0587 #define TYPHOON_INTR_HOST_INT       0x00000001
0588 #define TYPHOON_INTR_ARM2HOST0      0x00000002
0589 #define TYPHOON_INTR_ARM2HOST1      0x00000004
0590 #define TYPHOON_INTR_ARM2HOST2      0x00000008
0591 #define TYPHOON_INTR_ARM2HOST3      0x00000010
0592 #define TYPHOON_INTR_DMA0       0x00000020
0593 #define TYPHOON_INTR_DMA1       0x00000040
0594 #define TYPHOON_INTR_DMA2       0x00000080
0595 #define TYPHOON_INTR_DMA3       0x00000100
0596 #define TYPHOON_INTR_MASTER_ABORT   0x00000200
0597 #define TYPHOON_INTR_TARGET_ABORT   0x00000400
0598 #define TYPHOON_INTR_SELF       0x00000800
0599 #define TYPHOON_INTR_RESERVED       0xfffff000
0600 
0601 #define TYPHOON_INTR_BOOTCMD        TYPHOON_INTR_ARM2HOST0
0602 
0603 #define TYPHOON_INTR_ENABLE_ALL     0xffffffef
0604 #define TYPHOON_INTR_ALL        0xffffffff
0605 #define TYPHOON_INTR_NONE       0x00000000
0606 
0607 /* The commands for the 3XP chip (TYPHOON_REG_COMMAND)
0608  */
0609 #define TYPHOON_BOOTCMD_BOOT            0x00
0610 #define TYPHOON_BOOTCMD_WAKEUP          0xfa
0611 #define TYPHOON_BOOTCMD_DNLD_COMPLETE       0xfb
0612 #define TYPHOON_BOOTCMD_SEG_AVAILABLE       0xfc
0613 #define TYPHOON_BOOTCMD_RUNTIME_IMAGE       0xfd
0614 #define TYPHOON_BOOTCMD_REG_BOOT_RECORD     0xff
0615 
0616 /* 3XP Status values (TYPHOON_REG_STATUS)
0617  */
0618 #define TYPHOON_STATUS_WAITING_FOR_BOOT     0x07
0619 #define TYPHOON_STATUS_SECOND_INIT      0x08
0620 #define TYPHOON_STATUS_RUNNING          0x09
0621 #define TYPHOON_STATUS_WAITING_FOR_HOST     0x0d
0622 #define TYPHOON_STATUS_WAITING_FOR_SEGMENT  0x10
0623 #define TYPHOON_STATUS_SLEEPING         0x11
0624 #define TYPHOON_STATUS_HALTED           0x14
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