dsa/xrs700x/xrs700x_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 /* Register Base Addresses */
0004 #define XRS_DEVICE_ID_BASE      0x0
0005 #define XRS_GPIO_BASE           0x10000
0006 #define XRS_PORT_OFFSET         0x10000
0007 #define XRS_PORT_BASE(x)        (0x200000 + XRS_PORT_OFFSET * (x))
0008 #define XRS_RTC_BASE            0x280000
0009 #define XRS_TS_OFFSET           0x8000
0010 #define XRS_TS_BASE(x)          (0x290000 + XRS_TS_OFFSET * (x))
0011 #define XRS_SWITCH_CONF_BASE        0x300000
0012
0013 /* Device Identification Registers */
0014 #define XRS_DEV_ID0         (XRS_DEVICE_ID_BASE + 0)
0015 #define XRS_DEV_ID1         (XRS_DEVICE_ID_BASE + 2)
0016 #define XRS_INT_ID0         (XRS_DEVICE_ID_BASE + 4)
0017 #define XRS_INT_ID1         (XRS_DEVICE_ID_BASE + 6)
0018 #define XRS_REV_ID          (XRS_DEVICE_ID_BASE + 8)
0019
0020 /* GPIO Registers */
0021 #define XRS_CONFIG0         (XRS_GPIO_BASE + 0x1000)
0022 #define XRS_INPUT_STATUS0       (XRS_GPIO_BASE + 0x1002)
0023 #define XRS_CONFIG1         (XRS_GPIO_BASE + 0x1004)
0024 #define XRS_INPUT_STATUS1       (XRS_GPIO_BASE + 0x1006)
0025 #define XRS_CONFIG2         (XRS_GPIO_BASE + 0x1008)
0026 #define XRS_INPUT_STATUS2       (XRS_GPIO_BASE + 0x100a)
0027
0028 /* Port Configuration Registers */
0029 #define XRS_PORT_GEN_BASE(x)        (XRS_PORT_BASE(x) + 0x0)
0030 #define XRS_PORT_HSR_BASE(x)        (XRS_PORT_BASE(x) + 0x2000)
0031 #define XRS_PORT_PTP_BASE(x)        (XRS_PORT_BASE(x) + 0x4000)
0032 #define XRS_PORT_CNT_BASE(x)        (XRS_PORT_BASE(x) + 0x6000)
0033 #define XRS_PORT_IPO_BASE(x)        (XRS_PORT_BASE(x) + 0x8000)
0034
0035 /* Port Configuration Registers - General and State */
0036 #define XRS_PORT_STATE(x)       (XRS_PORT_GEN_BASE(x) + 0x0)
0037 #define XRS_PORT_FORWARDING     0
0038 #define XRS_PORT_LEARNING       1
0039 #define XRS_PORT_DISABLED       2
0040 #define XRS_PORT_MODE_NORMAL        0
0041 #define XRS_PORT_MODE_MANAGEMENT    1
0042 #define XRS_PORT_SPEED_1000     0x12
0043 #define XRS_PORT_SPEED_100      0x20
0044 #define XRS_PORT_SPEED_10       0x30
0045 #define XRS_PORT_VLAN(x)        (XRS_PORT_GEN_BASE(x) + 0x10)
0046 #define XRS_PORT_VLAN0_MAPPING(x)   (XRS_PORT_GEN_BASE(x) + 0x12)
0047 #define XRS_PORT_FWD_MASK(x)        (XRS_PORT_GEN_BASE(x) + 0x14)
0048 #define XRS_PORT_VLAN_PRIO(x)       (XRS_PORT_GEN_BASE(x) + 0x16)
0049
0050 /* Port Configuration Registers - HSR/PRP */
0051 #define XRS_HSR_CFG(x)          (XRS_PORT_HSR_BASE(x) + 0x0)
0052 #define XRS_HSR_CFG_HSR_PRP     BIT(0)
0053 #define XRS_HSR_CFG_HSR         0
0054 #define XRS_HSR_CFG_PRP         BIT(8)
0055 #define XRS_HSR_CFG_LANID_A     0
0056 #define XRS_HSR_CFG_LANID_B     BIT(10)
0057
0058 /* Port Configuration Registers - PTP */
0059 #define XRS_PTP_RX_SYNC_DELAY_NS_LO(x)  (XRS_PORT_PTP_BASE(x) + 0x2)
0060 #define XRS_PTP_RX_SYNC_DELAY_NS_HI(x)  (XRS_PORT_PTP_BASE(x) + 0x4)
0061 #define XRS_PTP_RX_EVENT_DELAY_NS(x)    (XRS_PORT_PTP_BASE(x) + 0xa)
0062 #define XRS_PTP_TX_EVENT_DELAY_NS(x)    (XRS_PORT_PTP_BASE(x) + 0x12)
0063
0064 /* Port Configuration Registers - Counter */
0065 #define XRS_CNT_CTRL(x)         (XRS_PORT_CNT_BASE(x) + 0x0)
0066 #define XRS_RX_GOOD_OCTETS_L        (XRS_PORT_CNT_BASE(0) + 0x200)
0067 #define XRS_RX_GOOD_OCTETS_H        (XRS_PORT_CNT_BASE(0) + 0x202)
0068 #define XRS_RX_BAD_OCTETS_L     (XRS_PORT_CNT_BASE(0) + 0x204)
0069 #define XRS_RX_BAD_OCTETS_H     (XRS_PORT_CNT_BASE(0) + 0x206)
0070 #define XRS_RX_UNICAST_L        (XRS_PORT_CNT_BASE(0) + 0x208)
0071 #define XRS_RX_UNICAST_H        (XRS_PORT_CNT_BASE(0) + 0x20a)
0072 #define XRS_RX_BROADCAST_L      (XRS_PORT_CNT_BASE(0) + 0x20c)
0073 #define XRS_RX_BROADCAST_H      (XRS_PORT_CNT_BASE(0) + 0x20e)
0074 #define XRS_RX_MULTICAST_L      (XRS_PORT_CNT_BASE(0) + 0x210)
0075 #define XRS_RX_MULTICAST_H      (XRS_PORT_CNT_BASE(0) + 0x212)
0076 #define XRS_RX_UNDERSIZE_L      (XRS_PORT_CNT_BASE(0) + 0x214)
0077 #define XRS_RX_UNDERSIZE_H      (XRS_PORT_CNT_BASE(0) + 0x216)
0078 #define XRS_RX_FRAGMENTS_L      (XRS_PORT_CNT_BASE(0) + 0x218)
0079 #define XRS_RX_FRAGMENTS_H      (XRS_PORT_CNT_BASE(0) + 0x21a)
0080 #define XRS_RX_OVERSIZE_L       (XRS_PORT_CNT_BASE(0) + 0x21c)
0081 #define XRS_RX_OVERSIZE_H       (XRS_PORT_CNT_BASE(0) + 0x21e)
0082 #define XRS_RX_JABBER_L         (XRS_PORT_CNT_BASE(0) + 0x220)
0083 #define XRS_RX_JABBER_H         (XRS_PORT_CNT_BASE(0) + 0x222)
0084 #define XRS_RX_ERR_L            (XRS_PORT_CNT_BASE(0) + 0x224)
0085 #define XRS_RX_ERR_H            (XRS_PORT_CNT_BASE(0) + 0x226)
0086 #define XRS_RX_CRC_L            (XRS_PORT_CNT_BASE(0) + 0x228)
0087 #define XRS_RX_CRC_H            (XRS_PORT_CNT_BASE(0) + 0x22a)
0088 #define XRS_RX_64_L         (XRS_PORT_CNT_BASE(0) + 0x22c)
0089 #define XRS_RX_64_H         (XRS_PORT_CNT_BASE(0) + 0x22e)
0090 #define XRS_RX_65_127_L         (XRS_PORT_CNT_BASE(0) + 0x230)
0091 #define XRS_RX_65_127_H         (XRS_PORT_CNT_BASE(0) + 0x232)
0092 #define XRS_RX_128_255_L        (XRS_PORT_CNT_BASE(0) + 0x234)
0093 #define XRS_RX_128_255_H        (XRS_PORT_CNT_BASE(0) + 0x236)
0094 #define XRS_RX_256_511_L        (XRS_PORT_CNT_BASE(0) + 0x238)
0095 #define XRS_RX_256_511_H        (XRS_PORT_CNT_BASE(0) + 0x23a)
0096 #define XRS_RX_512_1023_L       (XRS_PORT_CNT_BASE(0) + 0x23c)
0097 #define XRS_RX_512_1023_H       (XRS_PORT_CNT_BASE(0) + 0x23e)
0098 #define XRS_RX_1024_1536_L      (XRS_PORT_CNT_BASE(0) + 0x240)
0099 #define XRS_RX_1024_1536_H      (XRS_PORT_CNT_BASE(0) + 0x242)
0100 #define XRS_RX_HSR_PRP_L        (XRS_PORT_CNT_BASE(0) + 0x244)
0101 #define XRS_RX_HSR_PRP_H        (XRS_PORT_CNT_BASE(0) + 0x246)
0102 #define XRS_RX_WRONGLAN_L       (XRS_PORT_CNT_BASE(0) + 0x248)
0103 #define XRS_RX_WRONGLAN_H       (XRS_PORT_CNT_BASE(0) + 0x24a)
0104 #define XRS_RX_DUPLICATE_L      (XRS_PORT_CNT_BASE(0) + 0x24c)
0105 #define XRS_RX_DUPLICATE_H      (XRS_PORT_CNT_BASE(0) + 0x24e)
0106 #define XRS_TX_OCTETS_L         (XRS_PORT_CNT_BASE(0) + 0x280)
0107 #define XRS_TX_OCTETS_H         (XRS_PORT_CNT_BASE(0) + 0x282)
0108 #define XRS_TX_UNICAST_L        (XRS_PORT_CNT_BASE(0) + 0x284)
0109 #define XRS_TX_UNICAST_H        (XRS_PORT_CNT_BASE(0) + 0x286)
0110 #define XRS_TX_BROADCAST_L      (XRS_PORT_CNT_BASE(0) + 0x288)
0111 #define XRS_TX_BROADCAST_H      (XRS_PORT_CNT_BASE(0) + 0x28a)
0112 #define XRS_TX_MULTICAST_L      (XRS_PORT_CNT_BASE(0) + 0x28c)
0113 #define XRS_TX_MULTICAST_H      (XRS_PORT_CNT_BASE(0) + 0x28e)
0114 #define XRS_TX_HSR_PRP_L        (XRS_PORT_CNT_BASE(0) + 0x290)
0115 #define XRS_TX_HSR_PRP_H        (XRS_PORT_CNT_BASE(0) + 0x292)
0116 #define XRS_PRIQ_DROP_L         (XRS_PORT_CNT_BASE(0) + 0x2c0)
0117 #define XRS_PRIQ_DROP_H         (XRS_PORT_CNT_BASE(0) + 0x2c2)
0118 #define XRS_EARLY_DROP_L        (XRS_PORT_CNT_BASE(0) + 0x2c4)
0119 #define XRS_EARLY_DROP_H        (XRS_PORT_CNT_BASE(0) + 0x2c6)
0120
0121 /* Port Configuration Registers - Inbound Policy 0 - 15 */
0122 #define XRS_ETH_ADDR_CFG(x, p)      (XRS_PORT_IPO_BASE(x) + \
0123                      (p) * 0x20 + 0x0)
0124 #define XRS_ETH_ADDR_FWD_ALLOW(x, p)    (XRS_PORT_IPO_BASE(x) + \
0125                      (p) * 0x20 + 0x2)
0126 #define XRS_ETH_ADDR_FWD_MIRROR(x, p)   (XRS_PORT_IPO_BASE(x) + \
0127                      (p) * 0x20 + 0x4)
0128 #define XRS_ETH_ADDR_0(x, p)        (XRS_PORT_IPO_BASE(x) + \
0129                      (p) * 0x20 + 0x8)
0130 #define XRS_ETH_ADDR_1(x, p)        (XRS_PORT_IPO_BASE(x) + \
0131                      (p) * 0x20 + 0xa)
0132 #define XRS_ETH_ADDR_2(x, p)        (XRS_PORT_IPO_BASE(x) + \
0133                      (p) * 0x20 + 0xc)
0134
0135 /* RTC Registers */
0136 #define XRS_CUR_NSEC0           (XRS_RTC_BASE + 0x1004)
0137 #define XRS_CUR_NSEC1           (XRS_RTC_BASE + 0x1006)
0138 #define XRS_CUR_SEC0            (XRS_RTC_BASE + 0x1008)
0139 #define XRS_CUR_SEC1            (XRS_RTC_BASE + 0x100a)
0140 #define XRS_CUR_SEC2            (XRS_RTC_BASE + 0x100c)
0141 #define XRS_TIME_CC0            (XRS_RTC_BASE + 0x1010)
0142 #define XRS_TIME_CC1            (XRS_RTC_BASE + 0x1012)
0143 #define XRS_TIME_CC2            (XRS_RTC_BASE + 0x1014)
0144 #define XRS_STEP_SIZE0          (XRS_RTC_BASE + 0x1020)
0145 #define XRS_STEP_SIZE1          (XRS_RTC_BASE + 0x1022)
0146 #define XRS_STEP_SIZE2          (XRS_RTC_BASE + 0x1024)
0147 #define XRS_ADJUST_NSEC0        (XRS_RTC_BASE + 0x1034)
0148 #define XRS_ADJUST_NSEC1        (XRS_RTC_BASE + 0x1036)
0149 #define XRS_ADJUST_SEC0         (XRS_RTC_BASE + 0x1038)
0150 #define XRS_ADJUST_SEC1         (XRS_RTC_BASE + 0x103a)
0151 #define XRS_ADJUST_SEC2         (XRS_RTC_BASE + 0x103c)
0152 #define XRS_TIME_CMD            (XRS_RTC_BASE + 0x1040)
0153
0154 /* Time Stamper Registers */
0155 #define XRS_TS_CTRL(x)          (XRS_TS_BASE(x) + 0x1000)
0156 #define XRS_TS_INT_MASK(x)      (XRS_TS_BASE(x) + 0x1008)
0157 #define XRS_TS_INT_STATUS(x)        (XRS_TS_BASE(x) + 0x1010)
0158 #define XRS_TS_NSEC0(x)         (XRS_TS_BASE(x) + 0x1104)
0159 #define XRS_TS_NSEC1(x)         (XRS_TS_BASE(x) + 0x1106)
0160 #define XRS_TS_SEC0(x)          (XRS_TS_BASE(x) + 0x1108)
0161 #define XRS_TS_SEC1(x)          (XRS_TS_BASE(x) + 0x110a)
0162 #define XRS_TS_SEC2(x)          (XRS_TS_BASE(x) + 0x110c)
0163 #define XRS_PNCT0(x)            (XRS_TS_BASE(x) + 0x1110)
0164 #define XRS_PNCT1(x)            (XRS_TS_BASE(x) + 0x1112)
0165
0166 /* Switch Configuration Registers */
0167 #define XRS_SWITCH_GEN_BASE     (XRS_SWITCH_CONF_BASE + 0x0)
0168 #define XRS_SWITCH_TS_BASE      (XRS_SWITCH_CONF_BASE + 0x2000)
0169 #define XRS_SWITCH_VLAN_BASE        (XRS_SWITCH_CONF_BASE + 0x4000)
0170
0171 /* Switch Configuration Registers - General */
0172 #define XRS_GENERAL         (XRS_SWITCH_GEN_BASE + 0x10)
0173 #define XRS_GENERAL_TIME_TRAILER    BIT(9)
0174 #define XRS_GENERAL_MOD_SYNC        BIT(10)
0175 #define XRS_GENERAL_CUT_THRU        BIT(13)
0176 #define XRS_GENERAL_CLR_MAC_TBL     BIT(14)
0177 #define XRS_GENERAL_RESET       BIT(15)
0178 #define XRS_MT_CLEAR_MASK       (XRS_SWITCH_GEN_BASE + 0x12)
0179 #define XRS_ADDRESS_AGING       (XRS_SWITCH_GEN_BASE + 0x20)
0180 #define XRS_TS_CTRL_TX          (XRS_SWITCH_GEN_BASE + 0x28)
0181 #define XRS_TS_CTRL_RX          (XRS_SWITCH_GEN_BASE + 0x2a)
0182 #define XRS_INT_MASK            (XRS_SWITCH_GEN_BASE + 0x2c)
0183 #define XRS_INT_STATUS          (XRS_SWITCH_GEN_BASE + 0x2e)
0184 #define XRS_MAC_TABLE0          (XRS_SWITCH_GEN_BASE + 0x200)
0185 #define XRS_MAC_TABLE1          (XRS_SWITCH_GEN_BASE + 0x202)
0186 #define XRS_MAC_TABLE2          (XRS_SWITCH_GEN_BASE + 0x204)
0187 #define XRS_MAC_TABLE3          (XRS_SWITCH_GEN_BASE + 0x206)
0188
0189 /* Switch Configuration Registers - Frame Timestamp */
0190 #define XRS_TX_TS_NS_LO(t)      (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0)
0191 #define XRS_TX_TS_NS_HI(t)      (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2)
0192 #define XRS_TX_TS_S_LO(t)       (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4)
0193 #define XRS_TX_TS_S_HI(t)       (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6)
0194 #define XRS_TX_TS_HDR(t, h)     (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0195                      0x2 * (h) + 0xe)
0196 #define XRS_RX_TS_NS_LO(t)      (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0197                      0x200)
0198 #define XRS_RX_TS_NS_HI(t)      (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0199                      0x202)
0200 #define XRS_RX_TS_S_LO(t)       (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0201                      0x204)
0202 #define XRS_RX_TS_S_HI(t)       (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0203                      0x206)
0204 #define XRS_RX_TS_HDR(t, h)     (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0205                      0x2 * (h) + 0xe)
0206
0207 /* Switch Configuration Registers - VLAN */
0208 #define XRS_VLAN(v)         (XRS_SWITCH_VLAN_BASE + 0x2 * (v))