dsa/sja1105/sja1105.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
0003  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
0004  */
0005 #ifndef _SJA1105_H
0006 #define _SJA1105_H
0007
0008 #include <linux/ptp_clock_kernel.h>
0009 #include <linux/timecounter.h>
0010 #include <linux/dsa/sja1105.h>
0011 #include <linux/dsa/8021q.h>
0012 #include <net/dsa.h>
0013 #include <linux/mutex.h>
0014 #include "sja1105_static_config.h"
0015
0016 #define SJA1105ET_FDB_BIN_SIZE      4
0017 /* The hardware value is in multiples of 10 ms.
0018  * The passed parameter is in multiples of 1 ms.
0019  */
0020 #define SJA1105_AGEING_TIME_MS(ms)  ((ms) / 10)
0021 #define SJA1105_NUM_L2_POLICERS     SJA1110_MAX_L2_POLICING_COUNT
0022
0023 /* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period)
0024  * To avoid floating point operations, we'll multiply the degrees by 10
0025  * to get a "phase" and get 1 decimal point precision.
0026  */
0027 #define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \
0028     (((ps) * 360) / 800)
0029 #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
0030     ((800 * (phase)) / 360)
0031 #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
0032     (((phase) - 738) / 9)
0033 #define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \
0034     SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps))
0035
0036 /* Valid range in degrees is a value between 73.8 and 101.7
0037  * in 0.9 degree increments
0038  */
0039 #define SJA1105_RGMII_DELAY_MIN_PS \
0040     SJA1105_RGMII_DELAY_PHASE_TO_PS(738)
0041 #define SJA1105_RGMII_DELAY_MAX_PS \
0042     SJA1105_RGMII_DELAY_PHASE_TO_PS(1017)
0043
0044 typedef enum {
0045     SPI_READ = 0,
0046     SPI_WRITE = 1,
0047 } sja1105_spi_rw_mode_t;
0048
0049 #include "sja1105_tas.h"
0050 #include "sja1105_ptp.h"
0051
0052 enum sja1105_stats_area {
0053     MAC,
0054     HL1,
0055     HL2,
0056     ETHER,
0057     __MAX_SJA1105_STATS_AREA,
0058 };
0059
0060 /* Keeps the different addresses between E/T and P/Q/R/S */
0061 struct sja1105_regs {
0062     u64 device_id;
0063     u64 prod_id;
0064     u64 status;
0065     u64 port_control;
0066     u64 rgu;
0067     u64 vl_status;
0068     u64 config;
0069     u64 rmii_pll1;
0070     u64 ptppinst;
0071     u64 ptppindur;
0072     u64 ptp_control;
0073     u64 ptpclkval;
0074     u64 ptpclkrate;
0075     u64 ptpclkcorp;
0076     u64 ptpsyncts;
0077     u64 ptpschtm;
0078     u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
0079     u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
0080     u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
0081     u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
0082     u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
0083     u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
0084     u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
0085     u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
0086     u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
0087     u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
0088     u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
0089     u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
0090     u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
0091     u64 mdio_100base_tx;
0092     u64 mdio_100base_t1;
0093     u64 pcs_base[SJA1105_MAX_NUM_PORTS];
0094 };
0095
0096 struct sja1105_mdio_private {
0097     struct sja1105_private *priv;
0098 };
0099
0100 enum {
0101     SJA1105_SPEED_AUTO,
0102     SJA1105_SPEED_10MBPS,
0103     SJA1105_SPEED_100MBPS,
0104     SJA1105_SPEED_1000MBPS,
0105     SJA1105_SPEED_2500MBPS,
0106     SJA1105_SPEED_MAX,
0107 };
0108
0109 enum sja1105_internal_phy_t {
0110     SJA1105_NO_PHY      = 0,
0111     SJA1105_PHY_BASE_TX,
0112     SJA1105_PHY_BASE_T1,
0113 };
0114
0115 struct sja1105_info {
0116     u64 device_id;
0117     /* Needed for distinction between P and R, and between Q and S
0118      * (since the parts with/without SGMII share the same
0119      * switch core and device_id)
0120      */
0121     u64 part_no;
0122     /* E/T and P/Q/R/S have partial timestamps of different sizes.
0123      * They must be reconstructed on both families anyway to get the full
0124      * 64-bit values back.
0125      */
0126     int ptp_ts_bits;
0127     /* Also SPI commands are of different sizes to retrieve
0128      * the egress timestamps.
0129      */
0130     int ptpegr_ts_bytes;
0131     int num_cbs_shapers;
0132     int max_frame_mem;
0133     int num_ports;
0134     bool multiple_cascade_ports;
0135     enum dsa_tag_protocol tag_proto;
0136     const struct sja1105_dynamic_table_ops *dyn_ops;
0137     const struct sja1105_table_ops *static_ops;
0138     const struct sja1105_regs *regs;
0139     bool can_limit_mcast_flood;
0140     int (*reset_cmd)(struct dsa_switch *ds);
0141     int (*setup_rgmii_delay)(const void *ctx, int port);
0142     /* Prototypes from include/net/dsa.h */
0143     int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
0144                const unsigned char *addr, u16 vid);
0145     int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
0146                const unsigned char *addr, u16 vid);
0147     void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
0148                 enum packing_op op);
0149     bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
0150     void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
0151     int (*clocking_setup)(struct sja1105_private *priv);
0152     int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);
0153     int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);
0154     int (*disable_microcontroller)(struct sja1105_private *priv);
0155     const char *name;
0156     bool supports_mii[SJA1105_MAX_NUM_PORTS];
0157     bool supports_rmii[SJA1105_MAX_NUM_PORTS];
0158     bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
0159     bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
0160     bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
0161     enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
0162     const u64 port_speed[SJA1105_SPEED_MAX];
0163 };
0164
0165 enum sja1105_key_type {
0166     SJA1105_KEY_BCAST,
0167     SJA1105_KEY_TC,
0168     SJA1105_KEY_VLAN_UNAWARE_VL,
0169     SJA1105_KEY_VLAN_AWARE_VL,
0170 };
0171
0172 struct sja1105_key {
0173     enum sja1105_key_type type;
0174
0175     union {
0176         /* SJA1105_KEY_TC */
0177         struct {
0178             int pcp;
0179         } tc;
0180
0181         /* SJA1105_KEY_VLAN_UNAWARE_VL */
0182         /* SJA1105_KEY_VLAN_AWARE_VL */
0183         struct {
0184             u64 dmac;
0185             u16 vid;
0186             u16 pcp;
0187         } vl;
0188     };
0189 };
0190
0191 enum sja1105_rule_type {
0192     SJA1105_RULE_BCAST_POLICER,
0193     SJA1105_RULE_TC_POLICER,
0194     SJA1105_RULE_VL,
0195 };
0196
0197 enum sja1105_vl_type {
0198     SJA1105_VL_NONCRITICAL,
0199     SJA1105_VL_RATE_CONSTRAINED,
0200     SJA1105_VL_TIME_TRIGGERED,
0201 };
0202
0203 struct sja1105_rule {
0204     struct list_head list;
0205     unsigned long cookie;
0206     unsigned long port_mask;
0207     struct sja1105_key key;
0208     enum sja1105_rule_type type;
0209
0210     /* Action */
0211     union {
0212         /* SJA1105_RULE_BCAST_POLICER */
0213         struct {
0214             int sharindx;
0215         } bcast_pol;
0216
0217         /* SJA1105_RULE_TC_POLICER */
0218         struct {
0219             int sharindx;
0220         } tc_pol;
0221
0222         /* SJA1105_RULE_VL */
0223         struct {
0224             enum sja1105_vl_type type;
0225             unsigned long destports;
0226             int sharindx;
0227             int maxlen;
0228             int ipv;
0229             u64 base_time;
0230             u64 cycle_time;
0231             int num_entries;
0232             struct action_gate_entry *entries;
0233             struct flow_stats stats;
0234         } vl;
0235     };
0236 };
0237
0238 struct sja1105_flow_block {
0239     struct list_head rules;
0240     bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
0241     int num_virtual_links;
0242 };
0243
0244 struct sja1105_private {
0245     struct sja1105_static_config static_config;
0246     int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
0247     int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
0248     phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
0249     bool fixed_link[SJA1105_MAX_NUM_PORTS];
0250     unsigned long ucast_egress_floods;
0251     unsigned long bcast_egress_floods;
0252     unsigned long hwts_tx_en;
0253     const struct sja1105_info *info;
0254     size_t max_xfer_len;
0255     struct spi_device *spidev;
0256     struct dsa_switch *ds;
0257     u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
0258     u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
0259     struct sja1105_flow_block flow_block;
0260     /* Serializes transmission of management frames so that
0261      * the switch doesn't confuse them with one another.
0262      */
0263     struct mutex mgmt_lock;
0264     /* PTP two-step TX timestamp ID, and its serialization lock */
0265     spinlock_t ts_id_lock;
0266     u8 ts_id;
0267     /* Serializes access to the dynamic config interface */
0268     struct mutex dynamic_config_lock;
0269     struct devlink_region **regions;
0270     struct sja1105_cbs_entry *cbs;
0271     struct mii_bus *mdio_base_t1;
0272     struct mii_bus *mdio_base_tx;
0273     struct mii_bus *mdio_pcs;
0274     struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
0275     struct sja1105_ptp_data ptp_data;
0276     struct sja1105_tas_data tas_data;
0277 };
0278
0279 #include "sja1105_dynamic_config.h"
0280
0281 struct sja1105_spi_message {
0282     u64 access;
0283     u64 read_count;
0284     u64 address;
0285 };
0286
0287 /* From sja1105_main.c */
0288 enum sja1105_reset_reason {
0289     SJA1105_VLAN_FILTERING = 0,
0290     SJA1105_RX_HWTSTAMPING,
0291     SJA1105_AGEING_TIME,
0292     SJA1105_SCHEDULING,
0293     SJA1105_BEST_EFFORT_POLICING,
0294     SJA1105_VIRTUAL_LINKS,
0295 };
0296
0297 int sja1105_static_config_reload(struct sja1105_private *priv,
0298                  enum sja1105_reset_reason reason);
0299 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
0300                struct netlink_ext_ack *extack);
0301 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
0302
0303 /* From sja1105_mdio.c */
0304 int sja1105_mdiobus_register(struct dsa_switch *ds);
0305 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
0306 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
0307 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
0308 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
0309 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
0310
0311 /* From sja1105_devlink.c */
0312 int sja1105_devlink_setup(struct dsa_switch *ds);
0313 void sja1105_devlink_teardown(struct dsa_switch *ds);
0314 int sja1105_devlink_info_get(struct dsa_switch *ds,
0315                  struct devlink_info_req *req,
0316                  struct netlink_ext_ack *extack);
0317
0318 /* From sja1105_spi.c */
0319 int sja1105_xfer_buf(const struct sja1105_private *priv,
0320              sja1105_spi_rw_mode_t rw, u64 reg_addr,
0321              u8 *buf, size_t len);
0322 int sja1105_xfer_u32(const struct sja1105_private *priv,
0323              sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
0324              struct ptp_system_timestamp *ptp_sts);
0325 int sja1105_xfer_u64(const struct sja1105_private *priv,
0326              sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
0327              struct ptp_system_timestamp *ptp_sts);
0328 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
0329                      void *config_buf, int buf_len);
0330 int sja1105_static_config_upload(struct sja1105_private *priv);
0331 int sja1105_inhibit_tx(const struct sja1105_private *priv,
0332                unsigned long port_bitmap, bool tx_inhibited);
0333
0334 extern const struct sja1105_info sja1105e_info;
0335 extern const struct sja1105_info sja1105t_info;
0336 extern const struct sja1105_info sja1105p_info;
0337 extern const struct sja1105_info sja1105q_info;
0338 extern const struct sja1105_info sja1105r_info;
0339 extern const struct sja1105_info sja1105s_info;
0340 extern const struct sja1105_info sja1110a_info;
0341 extern const struct sja1105_info sja1110b_info;
0342 extern const struct sja1105_info sja1110c_info;
0343 extern const struct sja1105_info sja1110d_info;
0344
0345 /* From sja1105_clocking.c */
0346
0347 typedef enum {
0348     XMII_MAC = 0,
0349     XMII_PHY = 1,
0350 } sja1105_mii_role_t;
0351
0352 typedef enum {
0353     XMII_MODE_MII       = 0,
0354     XMII_MODE_RMII      = 1,
0355     XMII_MODE_RGMII     = 2,
0356     XMII_MODE_SGMII     = 3,
0357 } sja1105_phy_interface_t;
0358
0359 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
0360 int sja1110_setup_rgmii_delay(const void *ctx, int port);
0361 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
0362 int sja1105_clocking_setup(struct sja1105_private *priv);
0363 int sja1110_disable_microcontroller(struct sja1105_private *priv);
0364
0365 /* From sja1105_ethtool.c */
0366 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
0367 void sja1105_get_strings(struct dsa_switch *ds, int port,
0368              u32 stringset, u8 *data);
0369 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
0370
0371 /* From sja1105_dynamic_config.c */
0372 int sja1105_dynamic_config_read(struct sja1105_private *priv,
0373                 enum sja1105_blk_idx blk_idx,
0374                 int index, void *entry);
0375 int sja1105_dynamic_config_write(struct sja1105_private *priv,
0376                  enum sja1105_blk_idx blk_idx,
0377                  int index, void *entry, bool keep);
0378
0379 enum sja1105_iotag {
0380     SJA1105_C_TAG = 0, /* Inner VLAN header */
0381     SJA1105_S_TAG = 1, /* Outer VLAN header */
0382 };
0383
0384 enum sja1110_vlan_type {
0385     SJA1110_VLAN_INVALID = 0,
0386     SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
0387     SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
0388     SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
0389 };
0390
0391 enum sja1110_shaper_type {
0392     SJA1110_LEAKY_BUCKET_SHAPER = 0,
0393     SJA1110_CBS_SHAPER = 1,
0394 };
0395
0396 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
0397 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
0398               const unsigned char *addr, u16 vid);
0399 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
0400               const unsigned char *addr, u16 vid);
0401 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
0402             const unsigned char *addr, u16 vid);
0403 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
0404             const unsigned char *addr, u16 vid);
0405
0406 /* From sja1105_flower.c */
0407 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
0408                struct flow_cls_offload *cls, bool ingress);
0409 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
0410                struct flow_cls_offload *cls, bool ingress);
0411 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
0412                  struct flow_cls_offload *cls, bool ingress);
0413 void sja1105_flower_setup(struct dsa_switch *ds);
0414 void sja1105_flower_teardown(struct dsa_switch *ds);
0415 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
0416                        unsigned long cookie);
0417
0418 #endif