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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Realtek Simple Management Interface (SMI) driver
0003  * It can be discussed how "simple" this interface is.
0004  *
0005  * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
0006  * but the protocol is not MDIO at all. Instead it is a Realtek
0007  * pecularity that need to bit-bang the lines in a special way to
0008  * communicate with the switch.
0009  *
0010  * ASICs we intend to support with this driver:
0011  *
0012  * RTL8366   - The original version, apparently
0013  * RTL8369   - Similar enough to have the same datsheet as RTL8366
0014  * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
0015  *             different register layout from the other two
0016  * RTL8366S  - Is this "RTL8366 super"?
0017  * RTL8367   - Has an OpenWRT driver as well
0018  * RTL8368S  - Seems to be an alternative name for RTL8366RB
0019  * RTL8370   - Also uses SMI
0020  *
0021  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0022  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
0023  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
0024  * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
0025  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
0026  */
0027 
0028 #include <linux/kernel.h>
0029 #include <linux/module.h>
0030 #include <linux/device.h>
0031 #include <linux/spinlock.h>
0032 #include <linux/skbuff.h>
0033 #include <linux/of.h>
0034 #include <linux/of_device.h>
0035 #include <linux/of_mdio.h>
0036 #include <linux/delay.h>
0037 #include <linux/gpio/consumer.h>
0038 #include <linux/platform_device.h>
0039 #include <linux/regmap.h>
0040 #include <linux/bitops.h>
0041 #include <linux/if_bridge.h>
0042 
0043 #include "realtek.h"
0044 
0045 #define REALTEK_SMI_ACK_RETRY_COUNT     5
0046 
0047 static inline void realtek_smi_clk_delay(struct realtek_priv *priv)
0048 {
0049     ndelay(priv->clk_delay);
0050 }
0051 
0052 static void realtek_smi_start(struct realtek_priv *priv)
0053 {
0054     /* Set GPIO pins to output mode, with initial state:
0055      * SCK = 0, SDA = 1
0056      */
0057     gpiod_direction_output(priv->mdc, 0);
0058     gpiod_direction_output(priv->mdio, 1);
0059     realtek_smi_clk_delay(priv);
0060 
0061     /* CLK 1: 0 -> 1, 1 -> 0 */
0062     gpiod_set_value(priv->mdc, 1);
0063     realtek_smi_clk_delay(priv);
0064     gpiod_set_value(priv->mdc, 0);
0065     realtek_smi_clk_delay(priv);
0066 
0067     /* CLK 2: */
0068     gpiod_set_value(priv->mdc, 1);
0069     realtek_smi_clk_delay(priv);
0070     gpiod_set_value(priv->mdio, 0);
0071     realtek_smi_clk_delay(priv);
0072     gpiod_set_value(priv->mdc, 0);
0073     realtek_smi_clk_delay(priv);
0074     gpiod_set_value(priv->mdio, 1);
0075 }
0076 
0077 static void realtek_smi_stop(struct realtek_priv *priv)
0078 {
0079     realtek_smi_clk_delay(priv);
0080     gpiod_set_value(priv->mdio, 0);
0081     gpiod_set_value(priv->mdc, 1);
0082     realtek_smi_clk_delay(priv);
0083     gpiod_set_value(priv->mdio, 1);
0084     realtek_smi_clk_delay(priv);
0085     gpiod_set_value(priv->mdc, 1);
0086     realtek_smi_clk_delay(priv);
0087     gpiod_set_value(priv->mdc, 0);
0088     realtek_smi_clk_delay(priv);
0089     gpiod_set_value(priv->mdc, 1);
0090 
0091     /* Add a click */
0092     realtek_smi_clk_delay(priv);
0093     gpiod_set_value(priv->mdc, 0);
0094     realtek_smi_clk_delay(priv);
0095     gpiod_set_value(priv->mdc, 1);
0096 
0097     /* Set GPIO pins to input mode */
0098     gpiod_direction_input(priv->mdio);
0099     gpiod_direction_input(priv->mdc);
0100 }
0101 
0102 static void realtek_smi_write_bits(struct realtek_priv *priv, u32 data, u32 len)
0103 {
0104     for (; len > 0; len--) {
0105         realtek_smi_clk_delay(priv);
0106 
0107         /* Prepare data */
0108         gpiod_set_value(priv->mdio, !!(data & (1 << (len - 1))));
0109         realtek_smi_clk_delay(priv);
0110 
0111         /* Clocking */
0112         gpiod_set_value(priv->mdc, 1);
0113         realtek_smi_clk_delay(priv);
0114         gpiod_set_value(priv->mdc, 0);
0115     }
0116 }
0117 
0118 static void realtek_smi_read_bits(struct realtek_priv *priv, u32 len, u32 *data)
0119 {
0120     gpiod_direction_input(priv->mdio);
0121 
0122     for (*data = 0; len > 0; len--) {
0123         u32 u;
0124 
0125         realtek_smi_clk_delay(priv);
0126 
0127         /* Clocking */
0128         gpiod_set_value(priv->mdc, 1);
0129         realtek_smi_clk_delay(priv);
0130         u = !!gpiod_get_value(priv->mdio);
0131         gpiod_set_value(priv->mdc, 0);
0132 
0133         *data |= (u << (len - 1));
0134     }
0135 
0136     gpiod_direction_output(priv->mdio, 0);
0137 }
0138 
0139 static int realtek_smi_wait_for_ack(struct realtek_priv *priv)
0140 {
0141     int retry_cnt;
0142 
0143     retry_cnt = 0;
0144     do {
0145         u32 ack;
0146 
0147         realtek_smi_read_bits(priv, 1, &ack);
0148         if (ack == 0)
0149             break;
0150 
0151         if (++retry_cnt > REALTEK_SMI_ACK_RETRY_COUNT) {
0152             dev_err(priv->dev, "ACK timeout\n");
0153             return -ETIMEDOUT;
0154         }
0155     } while (1);
0156 
0157     return 0;
0158 }
0159 
0160 static int realtek_smi_write_byte(struct realtek_priv *priv, u8 data)
0161 {
0162     realtek_smi_write_bits(priv, data, 8);
0163     return realtek_smi_wait_for_ack(priv);
0164 }
0165 
0166 static int realtek_smi_write_byte_noack(struct realtek_priv *priv, u8 data)
0167 {
0168     realtek_smi_write_bits(priv, data, 8);
0169     return 0;
0170 }
0171 
0172 static int realtek_smi_read_byte0(struct realtek_priv *priv, u8 *data)
0173 {
0174     u32 t;
0175 
0176     /* Read data */
0177     realtek_smi_read_bits(priv, 8, &t);
0178     *data = (t & 0xff);
0179 
0180     /* Send an ACK */
0181     realtek_smi_write_bits(priv, 0x00, 1);
0182 
0183     return 0;
0184 }
0185 
0186 static int realtek_smi_read_byte1(struct realtek_priv *priv, u8 *data)
0187 {
0188     u32 t;
0189 
0190     /* Read data */
0191     realtek_smi_read_bits(priv, 8, &t);
0192     *data = (t & 0xff);
0193 
0194     /* Send an ACK */
0195     realtek_smi_write_bits(priv, 0x01, 1);
0196 
0197     return 0;
0198 }
0199 
0200 static int realtek_smi_read_reg(struct realtek_priv *priv, u32 addr, u32 *data)
0201 {
0202     unsigned long flags;
0203     u8 lo = 0;
0204     u8 hi = 0;
0205     int ret;
0206 
0207     spin_lock_irqsave(&priv->lock, flags);
0208 
0209     realtek_smi_start(priv);
0210 
0211     /* Send READ command */
0212     ret = realtek_smi_write_byte(priv, priv->cmd_read);
0213     if (ret)
0214         goto out;
0215 
0216     /* Set ADDR[7:0] */
0217     ret = realtek_smi_write_byte(priv, addr & 0xff);
0218     if (ret)
0219         goto out;
0220 
0221     /* Set ADDR[15:8] */
0222     ret = realtek_smi_write_byte(priv, addr >> 8);
0223     if (ret)
0224         goto out;
0225 
0226     /* Read DATA[7:0] */
0227     realtek_smi_read_byte0(priv, &lo);
0228     /* Read DATA[15:8] */
0229     realtek_smi_read_byte1(priv, &hi);
0230 
0231     *data = ((u32)lo) | (((u32)hi) << 8);
0232 
0233     ret = 0;
0234 
0235  out:
0236     realtek_smi_stop(priv);
0237     spin_unlock_irqrestore(&priv->lock, flags);
0238 
0239     return ret;
0240 }
0241 
0242 static int realtek_smi_write_reg(struct realtek_priv *priv,
0243                  u32 addr, u32 data, bool ack)
0244 {
0245     unsigned long flags;
0246     int ret;
0247 
0248     spin_lock_irqsave(&priv->lock, flags);
0249 
0250     realtek_smi_start(priv);
0251 
0252     /* Send WRITE command */
0253     ret = realtek_smi_write_byte(priv, priv->cmd_write);
0254     if (ret)
0255         goto out;
0256 
0257     /* Set ADDR[7:0] */
0258     ret = realtek_smi_write_byte(priv, addr & 0xff);
0259     if (ret)
0260         goto out;
0261 
0262     /* Set ADDR[15:8] */
0263     ret = realtek_smi_write_byte(priv, addr >> 8);
0264     if (ret)
0265         goto out;
0266 
0267     /* Write DATA[7:0] */
0268     ret = realtek_smi_write_byte(priv, data & 0xff);
0269     if (ret)
0270         goto out;
0271 
0272     /* Write DATA[15:8] */
0273     if (ack)
0274         ret = realtek_smi_write_byte(priv, data >> 8);
0275     else
0276         ret = realtek_smi_write_byte_noack(priv, data >> 8);
0277     if (ret)
0278         goto out;
0279 
0280     ret = 0;
0281 
0282  out:
0283     realtek_smi_stop(priv);
0284     spin_unlock_irqrestore(&priv->lock, flags);
0285 
0286     return ret;
0287 }
0288 
0289 /* There is one single case when we need to use this accessor and that
0290  * is when issueing soft reset. Since the device reset as soon as we write
0291  * that bit, no ACK will come back for natural reasons.
0292  */
0293 static int realtek_smi_write_reg_noack(void *ctx, u32 reg, u32 val)
0294 {
0295     return realtek_smi_write_reg(ctx, reg, val, false);
0296 }
0297 
0298 /* Regmap accessors */
0299 
0300 static int realtek_smi_write(void *ctx, u32 reg, u32 val)
0301 {
0302     struct realtek_priv *priv = ctx;
0303 
0304     return realtek_smi_write_reg(priv, reg, val, true);
0305 }
0306 
0307 static int realtek_smi_read(void *ctx, u32 reg, u32 *val)
0308 {
0309     struct realtek_priv *priv = ctx;
0310 
0311     return realtek_smi_read_reg(priv, reg, val);
0312 }
0313 
0314 static void realtek_smi_lock(void *ctx)
0315 {
0316     struct realtek_priv *priv = ctx;
0317 
0318     mutex_lock(&priv->map_lock);
0319 }
0320 
0321 static void realtek_smi_unlock(void *ctx)
0322 {
0323     struct realtek_priv *priv = ctx;
0324 
0325     mutex_unlock(&priv->map_lock);
0326 }
0327 
0328 static const struct regmap_config realtek_smi_regmap_config = {
0329     .reg_bits = 10, /* A4..A0 R4..R0 */
0330     .val_bits = 16,
0331     .reg_stride = 1,
0332     /* PHY regs are at 0x8000 */
0333     .max_register = 0xffff,
0334     .reg_format_endian = REGMAP_ENDIAN_BIG,
0335     .reg_read = realtek_smi_read,
0336     .reg_write = realtek_smi_write,
0337     .cache_type = REGCACHE_NONE,
0338     .lock = realtek_smi_lock,
0339     .unlock = realtek_smi_unlock,
0340 };
0341 
0342 static const struct regmap_config realtek_smi_nolock_regmap_config = {
0343     .reg_bits = 10, /* A4..A0 R4..R0 */
0344     .val_bits = 16,
0345     .reg_stride = 1,
0346     /* PHY regs are at 0x8000 */
0347     .max_register = 0xffff,
0348     .reg_format_endian = REGMAP_ENDIAN_BIG,
0349     .reg_read = realtek_smi_read,
0350     .reg_write = realtek_smi_write,
0351     .cache_type = REGCACHE_NONE,
0352     .disable_locking = true,
0353 };
0354 
0355 static int realtek_smi_mdio_read(struct mii_bus *bus, int addr, int regnum)
0356 {
0357     struct realtek_priv *priv = bus->priv;
0358 
0359     return priv->ops->phy_read(priv, addr, regnum);
0360 }
0361 
0362 static int realtek_smi_mdio_write(struct mii_bus *bus, int addr, int regnum,
0363                   u16 val)
0364 {
0365     struct realtek_priv *priv = bus->priv;
0366 
0367     return priv->ops->phy_write(priv, addr, regnum, val);
0368 }
0369 
0370 static int realtek_smi_setup_mdio(struct dsa_switch *ds)
0371 {
0372     struct realtek_priv *priv =  ds->priv;
0373     struct device_node *mdio_np;
0374     int ret;
0375 
0376     mdio_np = of_get_compatible_child(priv->dev->of_node, "realtek,smi-mdio");
0377     if (!mdio_np) {
0378         dev_err(priv->dev, "no MDIO bus node\n");
0379         return -ENODEV;
0380     }
0381 
0382     priv->slave_mii_bus = devm_mdiobus_alloc(priv->dev);
0383     if (!priv->slave_mii_bus) {
0384         ret = -ENOMEM;
0385         goto err_put_node;
0386     }
0387     priv->slave_mii_bus->priv = priv;
0388     priv->slave_mii_bus->name = "SMI slave MII";
0389     priv->slave_mii_bus->read = realtek_smi_mdio_read;
0390     priv->slave_mii_bus->write = realtek_smi_mdio_write;
0391     snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "SMI-%d",
0392          ds->index);
0393     priv->slave_mii_bus->dev.of_node = mdio_np;
0394     priv->slave_mii_bus->parent = priv->dev;
0395     ds->slave_mii_bus = priv->slave_mii_bus;
0396 
0397     ret = devm_of_mdiobus_register(priv->dev, priv->slave_mii_bus, mdio_np);
0398     if (ret) {
0399         dev_err(priv->dev, "unable to register MDIO bus %s\n",
0400             priv->slave_mii_bus->id);
0401         goto err_put_node;
0402     }
0403 
0404     return 0;
0405 
0406 err_put_node:
0407     of_node_put(mdio_np);
0408 
0409     return ret;
0410 }
0411 
0412 static int realtek_smi_probe(struct platform_device *pdev)
0413 {
0414     const struct realtek_variant *var;
0415     struct device *dev = &pdev->dev;
0416     struct realtek_priv *priv;
0417     struct regmap_config rc;
0418     struct device_node *np;
0419     int ret;
0420 
0421     var = of_device_get_match_data(dev);
0422     np = dev->of_node;
0423 
0424     priv = devm_kzalloc(dev, sizeof(*priv) + var->chip_data_sz, GFP_KERNEL);
0425     if (!priv)
0426         return -ENOMEM;
0427     priv->chip_data = (void *)priv + sizeof(*priv);
0428 
0429     mutex_init(&priv->map_lock);
0430 
0431     rc = realtek_smi_regmap_config;
0432     rc.lock_arg = priv;
0433     priv->map = devm_regmap_init(dev, NULL, priv, &rc);
0434     if (IS_ERR(priv->map)) {
0435         ret = PTR_ERR(priv->map);
0436         dev_err(dev, "regmap init failed: %d\n", ret);
0437         return ret;
0438     }
0439 
0440     rc = realtek_smi_nolock_regmap_config;
0441     priv->map_nolock = devm_regmap_init(dev, NULL, priv, &rc);
0442     if (IS_ERR(priv->map_nolock)) {
0443         ret = PTR_ERR(priv->map_nolock);
0444         dev_err(dev, "regmap init failed: %d\n", ret);
0445         return ret;
0446     }
0447 
0448     /* Link forward and backward */
0449     priv->dev = dev;
0450     priv->clk_delay = var->clk_delay;
0451     priv->cmd_read = var->cmd_read;
0452     priv->cmd_write = var->cmd_write;
0453     priv->ops = var->ops;
0454 
0455     priv->setup_interface = realtek_smi_setup_mdio;
0456     priv->write_reg_noack = realtek_smi_write_reg_noack;
0457 
0458     dev_set_drvdata(dev, priv);
0459     spin_lock_init(&priv->lock);
0460 
0461     /* TODO: if power is software controlled, set up any regulators here */
0462 
0463     priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
0464     if (IS_ERR(priv->reset)) {
0465         dev_err(dev, "failed to get RESET GPIO\n");
0466         return PTR_ERR(priv->reset);
0467     }
0468     if (priv->reset) {
0469         gpiod_set_value(priv->reset, 1);
0470         dev_dbg(dev, "asserted RESET\n");
0471         msleep(REALTEK_HW_STOP_DELAY);
0472         gpiod_set_value(priv->reset, 0);
0473         msleep(REALTEK_HW_START_DELAY);
0474         dev_dbg(dev, "deasserted RESET\n");
0475     }
0476 
0477     /* Fetch MDIO pins */
0478     priv->mdc = devm_gpiod_get_optional(dev, "mdc", GPIOD_OUT_LOW);
0479     if (IS_ERR(priv->mdc))
0480         return PTR_ERR(priv->mdc);
0481     priv->mdio = devm_gpiod_get_optional(dev, "mdio", GPIOD_OUT_LOW);
0482     if (IS_ERR(priv->mdio))
0483         return PTR_ERR(priv->mdio);
0484 
0485     priv->leds_disabled = of_property_read_bool(np, "realtek,disable-leds");
0486 
0487     ret = priv->ops->detect(priv);
0488     if (ret) {
0489         dev_err(dev, "unable to detect switch\n");
0490         return ret;
0491     }
0492 
0493     priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
0494     if (!priv->ds)
0495         return -ENOMEM;
0496 
0497     priv->ds->dev = dev;
0498     priv->ds->num_ports = priv->num_ports;
0499     priv->ds->priv = priv;
0500 
0501     priv->ds->ops = var->ds_ops_smi;
0502     ret = dsa_register_switch(priv->ds);
0503     if (ret) {
0504         dev_err_probe(dev, ret, "unable to register switch\n");
0505         return ret;
0506     }
0507     return 0;
0508 }
0509 
0510 static int realtek_smi_remove(struct platform_device *pdev)
0511 {
0512     struct realtek_priv *priv = platform_get_drvdata(pdev);
0513 
0514     if (!priv)
0515         return 0;
0516 
0517     dsa_unregister_switch(priv->ds);
0518     if (priv->slave_mii_bus)
0519         of_node_put(priv->slave_mii_bus->dev.of_node);
0520 
0521     /* leave the device reset asserted */
0522     if (priv->reset)
0523         gpiod_set_value(priv->reset, 1);
0524 
0525     platform_set_drvdata(pdev, NULL);
0526 
0527     return 0;
0528 }
0529 
0530 static void realtek_smi_shutdown(struct platform_device *pdev)
0531 {
0532     struct realtek_priv *priv = platform_get_drvdata(pdev);
0533 
0534     if (!priv)
0535         return;
0536 
0537     dsa_switch_shutdown(priv->ds);
0538 
0539     platform_set_drvdata(pdev, NULL);
0540 }
0541 
0542 static const struct of_device_id realtek_smi_of_match[] = {
0543 #if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8366RB)
0544     {
0545         .compatible = "realtek,rtl8366rb",
0546         .data = &rtl8366rb_variant,
0547     },
0548 #endif
0549 #if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB)
0550     {
0551         .compatible = "realtek,rtl8365mb",
0552         .data = &rtl8365mb_variant,
0553     },
0554 #endif
0555     { /* sentinel */ },
0556 };
0557 MODULE_DEVICE_TABLE(of, realtek_smi_of_match);
0558 
0559 static struct platform_driver realtek_smi_driver = {
0560     .driver = {
0561         .name = "realtek-smi",
0562         .of_match_table = of_match_ptr(realtek_smi_of_match),
0563     },
0564     .probe  = realtek_smi_probe,
0565     .remove = realtek_smi_remove,
0566     .shutdown = realtek_smi_shutdown,
0567 };
0568 module_platform_driver(realtek_smi_driver);
0569 
0570 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
0571 MODULE_DESCRIPTION("Driver for Realtek ethernet switch connected via SMI interface");
0572 MODULE_LICENSE("GPL");
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