dsa/qca/qca8k.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
0005  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0006  */
0007
0008 #ifndef __QCA8K_H
0009 #define __QCA8K_H
0010
0011 #include <linux/delay.h>
0012 #include <linux/regmap.h>
0013 #include <linux/gpio.h>
0014 #include <linux/dsa/tag_qca.h>
0015
0016 #define QCA8K_ETHERNET_MDIO_PRIORITY            7
0017 #define QCA8K_ETHERNET_PHY_PRIORITY         6
0018 #define QCA8K_ETHERNET_TIMEOUT              5
0019
0020 #define QCA8K_NUM_PORTS                 7
0021 #define QCA8K_NUM_CPU_PORTS             2
0022 #define QCA8K_MAX_MTU                   9000
0023 #define QCA8K_NUM_LAGS                  4
0024 #define QCA8K_NUM_PORTS_FOR_LAG             4
0025
0026 #define PHY_ID_QCA8327                  0x004dd034
0027 #define QCA8K_ID_QCA8327                0x12
0028 #define PHY_ID_QCA8337                  0x004dd036
0029 #define QCA8K_ID_QCA8337                0x13
0030
0031 #define QCA8K_QCA832X_MIB_COUNT             39
0032 #define QCA8K_QCA833X_MIB_COUNT             41
0033
0034 #define QCA8K_BUSY_WAIT_TIMEOUT             2000
0035
0036 #define QCA8K_NUM_FDB_RECORDS               2048
0037
0038 #define QCA8K_PORT_VID_DEF              1
0039
0040 /* Global control registers */
0041 #define QCA8K_REG_MASK_CTRL             0x000
0042 #define   QCA8K_MASK_CTRL_REV_ID_MASK           GENMASK(7, 0)
0043 #define   QCA8K_MASK_CTRL_REV_ID(x)         FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
0044 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK        GENMASK(15, 8)
0045 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)          FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
0046 #define QCA8K_REG_PORT0_PAD_CTRL            0x004
0047 #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN     BIT(31)
0048 #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE  BIT(19)
0049 #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE  BIT(18)
0050 #define QCA8K_REG_PORT5_PAD_CTRL            0x008
0051 #define QCA8K_REG_PORT6_PAD_CTRL            0x00c
0052 #define   QCA8K_PORT_PAD_RGMII_EN           BIT(26)
0053 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK        GENMASK(23, 22)
0054 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)      FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
0055 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK        GENMASK(21, 20)
0056 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)      FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
0057 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_EN      BIT(25)
0058 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN      BIT(24)
0059 #define   QCA8K_PORT_PAD_SGMII_EN           BIT(7)
0060 #define QCA8K_REG_PWS                   0x010
0061 #define   QCA8K_PWS_POWER_ON_SEL            BIT(31)
0062 /* This reg is only valid for QCA832x and toggle the package
0063  * type from 176 pin (by default) to 148 pin used on QCA8327
0064  */
0065 #define   QCA8327_PWS_PACKAGE148_EN         BIT(30)
0066 #define   QCA8K_PWS_LED_OPEN_EN_CSR         BIT(24)
0067 #define   QCA8K_PWS_SERDES_AEN_DIS          BIT(7)
0068 #define QCA8K_REG_MODULE_EN             0x030
0069 #define   QCA8K_MODULE_EN_MIB               BIT(0)
0070 #define QCA8K_REG_MIB                   0x034
0071 #define   QCA8K_MIB_FUNC                GENMASK(26, 24)
0072 #define   QCA8K_MIB_CPU_KEEP                BIT(20)
0073 #define   QCA8K_MIB_BUSY                BIT(17)
0074 #define QCA8K_MDIO_MASTER_CTRL              0x3c
0075 #define   QCA8K_MDIO_MASTER_BUSY            BIT(31)
0076 #define   QCA8K_MDIO_MASTER_EN              BIT(30)
0077 #define   QCA8K_MDIO_MASTER_READ            BIT(27)
0078 #define   QCA8K_MDIO_MASTER_WRITE           0
0079 #define   QCA8K_MDIO_MASTER_SUP_PRE         BIT(26)
0080 #define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK       GENMASK(25, 21)
0081 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)         FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
0082 #define   QCA8K_MDIO_MASTER_REG_ADDR_MASK       GENMASK(20, 16)
0083 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)         FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
0084 #define   QCA8K_MDIO_MASTER_DATA_MASK           GENMASK(15, 0)
0085 #define   QCA8K_MDIO_MASTER_DATA(x)         FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
0086 #define   QCA8K_MDIO_MASTER_MAX_PORTS           5
0087 #define   QCA8K_MDIO_MASTER_MAX_REG         32
0088 #define QCA8K_GOL_MAC_ADDR0             0x60
0089 #define QCA8K_GOL_MAC_ADDR1             0x64
0090 #define QCA8K_MAX_FRAME_SIZE                0x78
0091 #define QCA8K_REG_PORT_STATUS(_i)           (0x07c + (_i) * 4)
0092 #define   QCA8K_PORT_STATUS_SPEED           GENMASK(1, 0)
0093 #define   QCA8K_PORT_STATUS_SPEED_10            0
0094 #define   QCA8K_PORT_STATUS_SPEED_100           0x1
0095 #define   QCA8K_PORT_STATUS_SPEED_1000          0x2
0096 #define   QCA8K_PORT_STATUS_TXMAC           BIT(2)
0097 #define   QCA8K_PORT_STATUS_RXMAC           BIT(3)
0098 #define   QCA8K_PORT_STATUS_TXFLOW          BIT(4)
0099 #define   QCA8K_PORT_STATUS_RXFLOW          BIT(5)
0100 #define   QCA8K_PORT_STATUS_DUPLEX          BIT(6)
0101 #define   QCA8K_PORT_STATUS_LINK_UP         BIT(8)
0102 #define   QCA8K_PORT_STATUS_LINK_AUTO           BIT(9)
0103 #define   QCA8K_PORT_STATUS_LINK_PAUSE          BIT(10)
0104 #define   QCA8K_PORT_STATUS_FLOW_AUTO           BIT(12)
0105 #define QCA8K_REG_PORT_HDR_CTRL(_i)         (0x9c + (_i * 4))
0106 #define   QCA8K_PORT_HDR_CTRL_RX_MASK           GENMASK(3, 2)
0107 #define   QCA8K_PORT_HDR_CTRL_TX_MASK           GENMASK(1, 0)
0108 #define   QCA8K_PORT_HDR_CTRL_ALL           2
0109 #define   QCA8K_PORT_HDR_CTRL_MGMT          1
0110 #define   QCA8K_PORT_HDR_CTRL_NONE          0
0111 #define QCA8K_REG_SGMII_CTRL                0x0e0
0112 #define   QCA8K_SGMII_EN_PLL                BIT(1)
0113 #define   QCA8K_SGMII_EN_RX             BIT(2)
0114 #define   QCA8K_SGMII_EN_TX             BIT(3)
0115 #define   QCA8K_SGMII_EN_SD             BIT(4)
0116 #define   QCA8K_SGMII_CLK125M_DELAY         BIT(7)
0117 #define   QCA8K_SGMII_MODE_CTRL_MASK            GENMASK(23, 22)
0118 #define   QCA8K_SGMII_MODE_CTRL(x)          FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
0119 #define   QCA8K_SGMII_MODE_CTRL_BASEX           QCA8K_SGMII_MODE_CTRL(0x0)
0120 #define   QCA8K_SGMII_MODE_CTRL_PHY         QCA8K_SGMII_MODE_CTRL(0x1)
0121 #define   QCA8K_SGMII_MODE_CTRL_MAC         QCA8K_SGMII_MODE_CTRL(0x2)
0122
0123 /* MAC_PWR_SEL registers */
0124 #define QCA8K_REG_MAC_PWR_SEL               0x0e4
0125 #define   QCA8K_MAC_PWR_RGMII1_1_8V         BIT(18)
0126 #define   QCA8K_MAC_PWR_RGMII0_1_8V         BIT(19)
0127
0128 /* EEE control registers */
0129 #define QCA8K_REG_EEE_CTRL              0x100
0130 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)          ((_i + 1) * 2)
0131
0132 /* TRUNK_HASH_EN registers */
0133 #define QCA8K_TRUNK_HASH_EN_CTRL            0x270
0134 #define   QCA8K_TRUNK_HASH_SIP_EN           BIT(3)
0135 #define   QCA8K_TRUNK_HASH_DIP_EN           BIT(2)
0136 #define   QCA8K_TRUNK_HASH_SA_EN            BIT(1)
0137 #define   QCA8K_TRUNK_HASH_DA_EN            BIT(0)
0138 #define   QCA8K_TRUNK_HASH_MASK             GENMASK(3, 0)
0139
0140 /* ACL registers */
0141 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)           (0x420 + (_i * 8))
0142 #define   QCA8K_PORT_VLAN_CVID_MASK         GENMASK(27, 16)
0143 #define   QCA8K_PORT_VLAN_CVID(x)           FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
0144 #define   QCA8K_PORT_VLAN_SVID_MASK         GENMASK(11, 0)
0145 #define   QCA8K_PORT_VLAN_SVID(x)           FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
0146 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)           (0x424 + (_i * 8))
0147 #define QCA8K_REG_IPV4_PRI_BASE_ADDR            0x470
0148 #define QCA8K_REG_IPV4_PRI_ADDR_MASK            0x474
0149
0150 /* Lookup registers */
0151 #define QCA8K_REG_ATU_DATA0             0x600
0152 #define   QCA8K_ATU_ADDR2_MASK              GENMASK(31, 24)
0153 #define   QCA8K_ATU_ADDR3_MASK              GENMASK(23, 16)
0154 #define   QCA8K_ATU_ADDR4_MASK              GENMASK(15, 8)
0155 #define   QCA8K_ATU_ADDR5_MASK              GENMASK(7, 0)
0156 #define QCA8K_REG_ATU_DATA1             0x604
0157 #define   QCA8K_ATU_PORT_MASK               GENMASK(22, 16)
0158 #define   QCA8K_ATU_ADDR0_MASK              GENMASK(15, 8)
0159 #define   QCA8K_ATU_ADDR1_MASK              GENMASK(7, 0)
0160 #define QCA8K_REG_ATU_DATA2             0x608
0161 #define   QCA8K_ATU_VID_MASK                GENMASK(19, 8)
0162 #define   QCA8K_ATU_STATUS_MASK             GENMASK(3, 0)
0163 #define   QCA8K_ATU_STATUS_STATIC           0xf
0164 #define QCA8K_REG_ATU_FUNC              0x60c
0165 #define   QCA8K_ATU_FUNC_BUSY               BIT(31)
0166 #define   QCA8K_ATU_FUNC_PORT_EN            BIT(14)
0167 #define   QCA8K_ATU_FUNC_MULTI_EN           BIT(13)
0168 #define   QCA8K_ATU_FUNC_FULL               BIT(12)
0169 #define   QCA8K_ATU_FUNC_PORT_MASK          GENMASK(11, 8)
0170 #define QCA8K_REG_VTU_FUNC0             0x610
0171 #define   QCA8K_VTU_FUNC0_VALID             BIT(20)
0172 #define   QCA8K_VTU_FUNC0_IVL_EN            BIT(19)
0173 /*        QCA8K_VTU_FUNC0_EG_MODE_MASK          GENMASK(17, 4)
0174  *          It does contain VLAN_MODE for each port [5:4] for port0,
0175  *          [7:6] for port1 ... [17:16] for port6. Use virtual port
0176  *          define to handle this.
0177  */
0178 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)    (4 + (_i) * 2)
0179 #define   QCA8K_VTU_FUNC0_EG_MODE_MASK          GENMASK(1, 0)
0180 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)     (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
0181 #define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD         FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
0182 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)    (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
0183 #define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG         FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
0184 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)    (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
0185 #define   QCA8K_VTU_FUNC0_EG_MODE_TAG           FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
0186 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)      (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
0187 #define   QCA8K_VTU_FUNC0_EG_MODE_NOT           FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
0188 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)      (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
0189 #define QCA8K_REG_VTU_FUNC1             0x614
0190 #define   QCA8K_VTU_FUNC1_BUSY              BIT(31)
0191 #define   QCA8K_VTU_FUNC1_VID_MASK          GENMASK(27, 16)
0192 #define   QCA8K_VTU_FUNC1_FULL              BIT(4)
0193 #define QCA8K_REG_ATU_CTRL              0x618
0194 #define   QCA8K_ATU_AGE_TIME_MASK           GENMASK(15, 0)
0195 #define   QCA8K_ATU_AGE_TIME(x)             FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
0196 #define QCA8K_REG_GLOBAL_FW_CTRL0           0x620
0197 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN     BIT(10)
0198 #define   QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM     GENMASK(7, 4)
0199 #define QCA8K_REG_GLOBAL_FW_CTRL1           0x624
0200 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK        GENMASK(30, 24)
0201 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK      GENMASK(22, 16)
0202 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK      GENMASK(14, 8)
0203 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK      GENMASK(6, 0)
0204 #define QCA8K_PORT_LOOKUP_CTRL(_i)          (0x660 + (_i) * 0xc)
0205 #define   QCA8K_PORT_LOOKUP_MEMBER          GENMASK(6, 0)
0206 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK      GENMASK(9, 8)
0207 #define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)        FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
0208 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE      QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
0209 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK      QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
0210 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK     QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
0211 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE        QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
0212 #define   QCA8K_PORT_LOOKUP_STATE_MASK          GENMASK(18, 16)
0213 #define   QCA8K_PORT_LOOKUP_STATE(x)            FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
0214 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED      QCA8K_PORT_LOOKUP_STATE(0x0)
0215 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING      QCA8K_PORT_LOOKUP_STATE(0x1)
0216 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING     QCA8K_PORT_LOOKUP_STATE(0x2)
0217 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING      QCA8K_PORT_LOOKUP_STATE(0x3)
0218 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD       QCA8K_PORT_LOOKUP_STATE(0x4)
0219 #define   QCA8K_PORT_LOOKUP_LEARN           BIT(20)
0220 #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN       BIT(25)
0221
0222 #define QCA8K_REG_GOL_TRUNK_CTRL0           0x700
0223 /* 4 max trunk first
0224  * first 6 bit for member bitmap
0225  * 7th bit is to enable trunk port
0226  */
0227 #define QCA8K_REG_GOL_TRUNK_SHIFT(_i)           ((_i) * 8)
0228 #define QCA8K_REG_GOL_TRUNK_EN_MASK         BIT(7)
0229 #define QCA8K_REG_GOL_TRUNK_EN(_i)          (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
0230 #define QCA8K_REG_GOL_TRUNK_MEMBER_MASK         GENMASK(6, 0)
0231 #define QCA8K_REG_GOL_TRUNK_MEMBER(_i)          (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
0232 /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
0233 #define QCA8K_REG_GOL_TRUNK_CTRL(_i)            (0x704 + (((_i) / 2) * 4))
0234 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK      GENMASK(3, 0)
0235 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK       BIT(3)
0236 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK     GENMASK(2, 0)
0237 #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i)        (((_i) / 2) * 16)
0238 #define QCA8K_REG_GOL_MEM_ID_SHIFT(_i)          ((_i) * 4)
0239 /* Complex shift: FIRST shift for port THEN shift for trunk */
0240 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
0241 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j)    (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
0242 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j)  (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
0243
0244 #define QCA8K_REG_GLOBAL_FC_THRESH          0x800
0245 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK        GENMASK(24, 16)
0246 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)      FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
0247 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK       GENMASK(8, 0)
0248 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)     FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
0249
0250 #define QCA8K_REG_PORT_HOL_CTRL0(_i)            (0x970 + (_i) * 0x8)
0251 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK     GENMASK(3, 0)
0252 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
0253 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK     GENMASK(7, 4)
0254 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
0255 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK     GENMASK(11, 8)
0256 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
0257 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK     GENMASK(15, 12)
0258 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
0259 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK     GENMASK(19, 16)
0260 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
0261 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK     GENMASK(23, 20)
0262 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
0263 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK     GENMASK(29, 24)
0264 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)       FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
0265
0266 #define QCA8K_REG_PORT_HOL_CTRL1(_i)            (0x974 + (_i) * 0x8)
0267 #define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK     GENMASK(3, 0)
0268 #define   QCA8K_PORT_HOL_CTRL1_ING(x)           FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
0269 #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN        BIT(6)
0270 #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN       BIT(7)
0271 #define   QCA8K_PORT_HOL_CTRL1_WRED_EN          BIT(8)
0272 #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN     BIT(16)
0273
0274 /* Pkt edit registers */
0275 #define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)        (16 * ((_i) % 2))
0276 #define QCA8K_EGREES_VLAN_PORT_MASK(_i)         (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
0277 #define QCA8K_EGREES_VLAN_PORT(_i, x)           ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
0278 #define QCA8K_EGRESS_VLAN(x)                (0x0c70 + (4 * (x / 2)))
0279
0280 /* L3 registers */
0281 #define QCA8K_HROUTER_CONTROL               0xe00
0282 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M      GENMASK(17, 16)
0283 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S      16
0284 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE        1
0285 #define QCA8K_HROUTER_PBASED_CONTROL1           0xe08
0286 #define QCA8K_HROUTER_PBASED_CONTROL2           0xe0c
0287 #define QCA8K_HNAT_CONTROL              0xe38
0288
0289 /* MIB registers */
0290 #define QCA8K_PORT_MIB_COUNTER(_i)          (0x1000 + (_i) * 0x100)
0291
0292 /* QCA specific MII registers */
0293 #define MII_ATH_MMD_ADDR                0x0d
0294 #define MII_ATH_MMD_DATA                0x0e
0295
0296 enum {
0297     QCA8K_PORT_SPEED_10M = 0,
0298     QCA8K_PORT_SPEED_100M = 1,
0299     QCA8K_PORT_SPEED_1000M = 2,
0300     QCA8K_PORT_SPEED_ERR = 3,
0301 };
0302
0303 enum qca8k_fdb_cmd {
0304     QCA8K_FDB_FLUSH = 1,
0305     QCA8K_FDB_LOAD = 2,
0306     QCA8K_FDB_PURGE = 3,
0307     QCA8K_FDB_FLUSH_PORT = 5,
0308     QCA8K_FDB_NEXT = 6,
0309     QCA8K_FDB_SEARCH = 7,
0310 };
0311
0312 enum qca8k_vlan_cmd {
0313     QCA8K_VLAN_FLUSH = 1,
0314     QCA8K_VLAN_LOAD = 2,
0315     QCA8K_VLAN_PURGE = 3,
0316     QCA8K_VLAN_REMOVE_PORT = 4,
0317     QCA8K_VLAN_NEXT = 5,
0318     QCA8K_VLAN_READ = 6,
0319 };
0320
0321 enum qca8k_mid_cmd {
0322     QCA8K_MIB_FLUSH = 1,
0323     QCA8K_MIB_FLUSH_PORT = 2,
0324     QCA8K_MIB_CAST = 3,
0325 };
0326
0327 struct qca8k_priv;
0328
0329 struct qca8k_info_ops {
0330     int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data);
0331     /* TODO: remove these extra ops when we can support regmap bulk read/write */
0332     int (*read_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len);
0333     int (*write_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len);
0334 };
0335
0336 struct qca8k_match_data {
0337     u8 id;
0338     bool reduced_package;
0339     u8 mib_count;
0340     const struct qca8k_info_ops *ops;
0341 };
0342
0343 enum {
0344     QCA8K_CPU_PORT0,
0345     QCA8K_CPU_PORT6,
0346 };
0347
0348 struct qca8k_mgmt_eth_data {
0349     struct completion rw_done;
0350     struct mutex mutex; /* Enforce one mdio read/write at time */
0351     bool ack;
0352     u32 seq;
0353     u32 data[4];
0354 };
0355
0356 struct qca8k_mib_eth_data {
0357     struct completion rw_done;
0358     struct mutex mutex; /* Process one command at time */
0359     refcount_t port_parsed; /* Counter to track parsed port */
0360     u8 req_port;
0361     u64 *data; /* pointer to ethtool data */
0362 };
0363
0364 struct qca8k_ports_config {
0365     bool sgmii_rx_clk_falling_edge;
0366     bool sgmii_tx_clk_falling_edge;
0367     bool sgmii_enable_pll;
0368     u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
0369     u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
0370 };
0371
0372 struct qca8k_mdio_cache {
0373 /* The 32bit switch registers are accessed indirectly. To achieve this we need
0374  * to set the page of the register. Track the last page that was set to reduce
0375  * mdio writes
0376  */
0377     u16 page;
0378 /* lo and hi can also be cached and from Documentation we can skip one
0379  * extra mdio write if lo or hi is didn't change.
0380  */
0381     u16 lo;
0382     u16 hi;
0383 };
0384
0385 struct qca8k_pcs {
0386     struct phylink_pcs pcs;
0387     struct qca8k_priv *priv;
0388     int port;
0389 };
0390
0391 struct qca8k_priv {
0392     u8 switch_id;
0393     u8 switch_revision;
0394     u8 mirror_rx;
0395     u8 mirror_tx;
0396     u8 lag_hash_mode;
0397     /* Each bit correspond to a port. This switch can support a max of 7 port.
0398      * Bit 1: port enabled. Bit 0: port disabled.
0399      */
0400     u8 port_enabled_map;
0401     struct qca8k_ports_config ports_config;
0402     struct regmap *regmap;
0403     struct mii_bus *bus;
0404     struct dsa_switch *ds;
0405     struct mutex reg_mutex;
0406     struct device *dev;
0407     struct gpio_desc *reset_gpio;
0408     struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */
0409     struct qca8k_mgmt_eth_data mgmt_eth_data;
0410     struct qca8k_mib_eth_data mib_eth_data;
0411     struct qca8k_mdio_cache mdio_cache;
0412     struct qca8k_pcs pcs_port_0;
0413     struct qca8k_pcs pcs_port_6;
0414     const struct qca8k_match_data *info;
0415 };
0416
0417 struct qca8k_mib_desc {
0418     unsigned int size;
0419     unsigned int offset;
0420     const char *name;
0421 };
0422
0423 struct qca8k_fdb {
0424     u16 vid;
0425     u8 port_mask;
0426     u8 aging;
0427     u8 mac[6];
0428 };
0429
0430 /* Common setup function */
0431 extern const struct qca8k_mib_desc ar8327_mib[];
0432 extern const struct regmap_access_table qca8k_readable_table;
0433 int qca8k_mib_init(struct qca8k_priv *priv);
0434 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable);
0435 int qca8k_read_switch_id(struct qca8k_priv *priv);
0436
0437 /* Common read/write/rmw function */
0438 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
0439 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
0440 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
0441
0442 /* Common ops function */
0443 void qca8k_fdb_flush(struct qca8k_priv *priv);
0444
0445 /* Common ethtool stats function */
0446 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data);
0447 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
0448                  uint64_t *data);
0449 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset);
0450
0451 /* Common eee function */
0452 int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee);
0453 int qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
0454
0455 /* Common bridge function */
0456 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
0457 int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
0458                struct dsa_bridge bridge,
0459                bool *tx_fwd_offload,
0460                struct netlink_ext_ack *extack);
0461 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
0462                  struct dsa_bridge bridge);
0463
0464 /* Common port enable/disable function */
0465 int qca8k_port_enable(struct dsa_switch *ds, int port,
0466               struct phy_device *phy);
0467 void qca8k_port_disable(struct dsa_switch *ds, int port);
0468
0469 /* Common MTU function */
0470 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu);
0471 int qca8k_port_max_mtu(struct dsa_switch *ds, int port);
0472
0473 /* Common fast age function */
0474 void qca8k_port_fast_age(struct dsa_switch *ds, int port);
0475 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs);
0476
0477 /* Common FDB function */
0478 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
0479               u16 port_mask, u16 vid);
0480 int qca8k_port_fdb_add(struct dsa_switch *ds, int port,
0481                const unsigned char *addr, u16 vid,
0482                struct dsa_db db);
0483 int qca8k_port_fdb_del(struct dsa_switch *ds, int port,
0484                const unsigned char *addr, u16 vid,
0485                struct dsa_db db);
0486 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
0487             dsa_fdb_dump_cb_t *cb, void *data);
0488
0489 /* Common MDB function */
0490 int qca8k_port_mdb_add(struct dsa_switch *ds, int port,
0491                const struct switchdev_obj_port_mdb *mdb,
0492                struct dsa_db db);
0493 int qca8k_port_mdb_del(struct dsa_switch *ds, int port,
0494                const struct switchdev_obj_port_mdb *mdb,
0495                struct dsa_db db);
0496
0497 /* Common port mirror function */
0498 int qca8k_port_mirror_add(struct dsa_switch *ds, int port,
0499               struct dsa_mall_mirror_tc_entry *mirror,
0500               bool ingress, struct netlink_ext_ack *extack);
0501 void qca8k_port_mirror_del(struct dsa_switch *ds, int port,
0502                struct dsa_mall_mirror_tc_entry *mirror);
0503
0504 /* Common port VLAN function */
0505 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
0506                   struct netlink_ext_ack *extack);
0507 int qca8k_port_vlan_add(struct dsa_switch *ds, int port,
0508             const struct switchdev_obj_port_vlan *vlan,
0509             struct netlink_ext_ack *extack);
0510 int qca8k_port_vlan_del(struct dsa_switch *ds, int port,
0511             const struct switchdev_obj_port_vlan *vlan);
0512
0513 /* Common port LAG function */
0514 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag,
0515             struct netdev_lag_upper_info *info);
0516 int qca8k_port_lag_leave(struct dsa_switch *ds, int port,
0517              struct dsa_lag lag);
0518
0519 #endif /* __QCA8K_H */