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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
0003 /*
0004  *                   +----------------------+
0005  * GMAC1----RGMII----|--MAC0                |
0006  *      \---MDIO1----|--REGs                |----MDIO3----\
0007  *                   |                      |             |  +------+
0008  *                   |                      |             +--|      |
0009  *                   |                 MAC1-|----RMII--M-----| PHY0 |-o P0
0010  *                   |                      |          |  |  +------+
0011  *                   |                      |          |  +--|      |
0012  *                   |                 MAC2-|----RMII--------| PHY1 |-o P1
0013  *                   |                      |          |  |  +------+
0014  *                   |                      |          |  +--|      |
0015  *                   |                 MAC3-|----RMII--------| PHY2 |-o P2
0016  *                   |                      |          |  |  +------+
0017  *                   |                      |          |  +--|      |
0018  *                   |                 MAC4-|----RMII--------| PHY3 |-o P3
0019  *                   |                      |          |  |  +------+
0020  *                   |                      |          |  +--|      |
0021  *                   |                 MAC5-|--+-RMII--M-----|-PHY4-|-o P4
0022  *                   |                      |  |       |     +------+
0023  *                   +----------------------+  |       \--CFG_SW_PHY_SWAP
0024  * GMAC0---------------RMII--------------------/        \-CFG_SW_PHY_ADDR_SWAP
0025  *      \---MDIO0--NC
0026  *
0027  * GMAC0 and MAC5 are connected together and use same PHY. Depending on
0028  * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be
0029  * used at same time. If GMAC0 is used (default) then MAC5 should be disabled.
0030  *
0031  * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
0032  * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this
0033  * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5
0034  * bundle.
0035  *
0036  * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
0037  *
0038  * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register
0039  * set and not related to switch internal registers.
0040  */
0041 
0042 #include <linux/bitfield.h>
0043 #include <linux/module.h>
0044 #include <linux/of_irq.h>
0045 #include <linux/of_mdio.h>
0046 #include <linux/regmap.h>
0047 #include <linux/reset.h>
0048 #include <net/dsa.h>
0049 
0050 #define AR9331_SW_NAME              "ar9331_switch"
0051 #define AR9331_SW_PORTS             6
0052 
0053 /* dummy reg to change page */
0054 #define AR9331_SW_REG_PAGE          0x40000
0055 
0056 /* Global Interrupt */
0057 #define AR9331_SW_REG_GINT          0x10
0058 #define AR9331_SW_REG_GINT_MASK         0x14
0059 #define AR9331_SW_GINT_PHY_INT          BIT(2)
0060 
0061 #define AR9331_SW_REG_FLOOD_MASK        0x2c
0062 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU   BIT(26)
0063 
0064 #define AR9331_SW_REG_GLOBAL_CTRL       0x30
0065 #define AR9331_SW_GLOBAL_CTRL_MFS_M     GENMASK(13, 0)
0066 
0067 #define AR9331_SW_REG_MDIO_CTRL         0x98
0068 #define AR9331_SW_MDIO_CTRL_BUSY        BIT(31)
0069 #define AR9331_SW_MDIO_CTRL_MASTER_EN       BIT(30)
0070 #define AR9331_SW_MDIO_CTRL_CMD_READ        BIT(27)
0071 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M      GENMASK(25, 21)
0072 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M      GENMASK(20, 16)
0073 #define AR9331_SW_MDIO_CTRL_DATA_M      GENMASK(16, 0)
0074 
0075 #define AR9331_SW_REG_PORT_STATUS(_port)    (0x100 + (_port) * 0x100)
0076 
0077 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
0078  * If not set, mac can be config by software.
0079  */
0080 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN  BIT(12)
0081 
0082 /* LINK_EN - If set, MAC is configured from PHY link status.
0083  * If not set, MAC should be configured by software.
0084  */
0085 #define AR9331_SW_PORT_STATUS_LINK_EN       BIT(9)
0086 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE   BIT(6)
0087 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN    BIT(5)
0088 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN    BIT(4)
0089 #define AR9331_SW_PORT_STATUS_RXMAC     BIT(3)
0090 #define AR9331_SW_PORT_STATUS_TXMAC     BIT(2)
0091 #define AR9331_SW_PORT_STATUS_SPEED_M       GENMASK(1, 0)
0092 #define AR9331_SW_PORT_STATUS_SPEED_1000    2
0093 #define AR9331_SW_PORT_STATUS_SPEED_100     1
0094 #define AR9331_SW_PORT_STATUS_SPEED_10      0
0095 
0096 #define AR9331_SW_PORT_STATUS_MAC_MASK \
0097     (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
0098 
0099 #define AR9331_SW_PORT_STATUS_LINK_MASK \
0100     (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
0101      AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
0102      AR9331_SW_PORT_STATUS_SPEED_M)
0103 
0104 #define AR9331_SW_REG_PORT_CTRL(_port)          (0x104 + (_port) * 0x100)
0105 #define AR9331_SW_PORT_CTRL_HEAD_EN         BIT(11)
0106 #define AR9331_SW_PORT_CTRL_PORT_STATE          GENMASK(2, 0)
0107 #define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED     0
0108 #define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING     1
0109 #define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING    2
0110 #define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING     3
0111 #define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD      4
0112 
0113 #define AR9331_SW_REG_PORT_VLAN(_port)          (0x108 + (_port) * 0x100)
0114 #define AR9331_SW_PORT_VLAN_8021Q_MODE          GENMASK(31, 30)
0115 #define AR9331_SW_8021Q_MODE_SECURE         3
0116 #define AR9331_SW_8021Q_MODE_CHECK          2
0117 #define AR9331_SW_8021Q_MODE_FALLBACK           1
0118 #define AR9331_SW_8021Q_MODE_NONE           0
0119 #define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER     GENMASK(25, 16)
0120 
0121 /* MIB registers */
0122 #define AR9331_MIB_COUNTER(x)           (0x20000 + ((x) * 0x100))
0123 
0124 /* Phy bypass mode
0125  * ------------------------------------------------------------------------
0126  * Bit:   | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
0127  *
0128  * real   | start |   OP  | PhyAddr           |  Reg Addr         |  TA   |
0129  * atheros| start |   OP  | 2'b00 |PhyAdd[2:0]|  Reg Addr[4:0]    |  TA   |
0130  *
0131  *
0132  * Bit:   |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
0133  * real   |  Data                                                         |
0134  * atheros|  Data                                                         |
0135  *
0136  * ------------------------------------------------------------------------
0137  * Page address mode
0138  * ------------------------------------------------------------------------
0139  * Bit:   | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
0140  * real   | start |   OP  | PhyAddr           |  Reg Addr         |  TA   |
0141  * atheros| start |   OP  | 2'b11 |                          8'b0 |  TA   |
0142  *
0143  * Bit:   |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
0144  * real   |  Data                                                         |
0145  * atheros|                       | Page [9:0]                            |
0146  */
0147 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be
0148  * written to bits[9:0] of mdio data register.
0149  */
0150 #define AR9331_SW_ADDR_PAGE         GENMASK(18, 9)
0151 
0152 /* ------------------------------------------------------------------------
0153  * Normal register access mode
0154  * ------------------------------------------------------------------------
0155  * Bit:   | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
0156  * real   | start |   OP  | PhyAddr           |  Reg Addr         |  TA   |
0157  * atheros| start |   OP  | 2'b10 |  low_addr[7:0]                |  TA   |
0158  *
0159  * Bit:   |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
0160  * real   |  Data                                                         |
0161  * atheros|  Data                                                         |
0162  * ------------------------------------------------------------------------
0163  */
0164 #define AR9331_SW_LOW_ADDR_PHY          GENMASK(8, 6)
0165 #define AR9331_SW_LOW_ADDR_REG          GENMASK(5, 1)
0166 
0167 #define AR9331_SW_MDIO_PHY_MODE_M       GENMASK(4, 3)
0168 #define AR9331_SW_MDIO_PHY_MODE_PAGE        3
0169 #define AR9331_SW_MDIO_PHY_MODE_REG     2
0170 #define AR9331_SW_MDIO_PHY_MODE_BYPASS      0
0171 #define AR9331_SW_MDIO_PHY_ADDR_M       GENMASK(2, 0)
0172 
0173 /* Empirical determined values */
0174 #define AR9331_SW_MDIO_POLL_SLEEP_US        1
0175 #define AR9331_SW_MDIO_POLL_TIMEOUT_US      20
0176 
0177 /* The interval should be small enough to avoid overflow of 32bit MIBs */
0178 /*
0179  * FIXME: until we can read MIBs from stats64 call directly (i.e. sleep
0180  * there), we have to poll stats more frequently then it is actually needed.
0181  * For overflow protection, normally, 100 sec interval should have been OK.
0182  */
0183 #define STATS_INTERVAL_JIFFIES          (3 * HZ)
0184 
0185 struct ar9331_sw_stats_raw {
0186     u32 rxbroad;            /* 0x00 */
0187     u32 rxpause;            /* 0x04 */
0188     u32 rxmulti;            /* 0x08 */
0189     u32 rxfcserr;           /* 0x0c */
0190     u32 rxalignerr;         /* 0x10 */
0191     u32 rxrunt;         /* 0x14 */
0192     u32 rxfragment;         /* 0x18 */
0193     u32 rx64byte;           /* 0x1c */
0194     u32 rx128byte;          /* 0x20 */
0195     u32 rx256byte;          /* 0x24 */
0196     u32 rx512byte;          /* 0x28 */
0197     u32 rx1024byte;         /* 0x2c */
0198     u32 rx1518byte;         /* 0x30 */
0199     u32 rxmaxbyte;          /* 0x34 */
0200     u32 rxtoolong;          /* 0x38 */
0201     u32 rxgoodbyte;         /* 0x3c */
0202     u32 rxgoodbyte_hi;
0203     u32 rxbadbyte;          /* 0x44 */
0204     u32 rxbadbyte_hi;
0205     u32 rxoverflow;         /* 0x4c */
0206     u32 filtered;           /* 0x50 */
0207     u32 txbroad;            /* 0x54 */
0208     u32 txpause;            /* 0x58 */
0209     u32 txmulti;            /* 0x5c */
0210     u32 txunderrun;         /* 0x60 */
0211     u32 tx64byte;           /* 0x64 */
0212     u32 tx128byte;          /* 0x68 */
0213     u32 tx256byte;          /* 0x6c */
0214     u32 tx512byte;          /* 0x70 */
0215     u32 tx1024byte;         /* 0x74 */
0216     u32 tx1518byte;         /* 0x78 */
0217     u32 txmaxbyte;          /* 0x7c */
0218     u32 txoversize;         /* 0x80 */
0219     u32 txbyte;         /* 0x84 */
0220     u32 txbyte_hi;
0221     u32 txcollision;        /* 0x8c */
0222     u32 txabortcol;         /* 0x90 */
0223     u32 txmulticol;         /* 0x94 */
0224     u32 txsinglecol;        /* 0x98 */
0225     u32 txexcdefer;         /* 0x9c */
0226     u32 txdefer;            /* 0xa0 */
0227     u32 txlatecol;          /* 0xa4 */
0228 };
0229 
0230 struct ar9331_sw_port {
0231     int idx;
0232     struct delayed_work mib_read;
0233     struct rtnl_link_stats64 stats;
0234     struct ethtool_pause_stats pause_stats;
0235     struct spinlock stats_lock;
0236 };
0237 
0238 struct ar9331_sw_priv {
0239     struct device *dev;
0240     struct dsa_switch ds;
0241     struct dsa_switch_ops ops;
0242     struct irq_domain *irqdomain;
0243     u32 irq_mask;
0244     struct mutex lock_irq;
0245     struct mii_bus *mbus; /* mdio master */
0246     struct mii_bus *sbus; /* mdio slave */
0247     struct regmap *regmap;
0248     struct reset_control *sw_reset;
0249     struct ar9331_sw_port port[AR9331_SW_PORTS];
0250 };
0251 
0252 static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
0253 {
0254     struct ar9331_sw_port *p = port - port->idx;
0255 
0256     return (struct ar9331_sw_priv *)((void *)p -
0257                      offsetof(struct ar9331_sw_priv, port));
0258 }
0259 
0260 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
0261  * If some kind of optimization is used, the request should be repeated.
0262  */
0263 static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
0264 {
0265     int ret;
0266 
0267     ret = reset_control_assert(priv->sw_reset);
0268     if (ret)
0269         goto error;
0270 
0271     /* AR9331 doc do not provide any information about proper reset
0272      * sequence. The AR8136 (the closes switch to the AR9331) doc says:
0273      * reset duration should be greater than 10ms. So, let's use this value
0274      * for now.
0275      */
0276     usleep_range(10000, 15000);
0277     ret = reset_control_deassert(priv->sw_reset);
0278     if (ret)
0279         goto error;
0280     /* There is no information on how long should we wait after reset.
0281      * AR8136 has an EEPROM and there is an Interrupt for EEPROM load
0282      * status. AR9331 has no EEPROM support.
0283      * For now, do not wait. In case AR8136 will be needed, the after
0284      * reset delay can be added as well.
0285      */
0286 
0287     return 0;
0288 error:
0289     dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0290     return ret;
0291 }
0292 
0293 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
0294                 u16 data)
0295 {
0296     struct ar9331_sw_priv *priv = mbus->priv;
0297     struct regmap *regmap = priv->regmap;
0298     u32 val;
0299     int ret;
0300 
0301     ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
0302                AR9331_SW_MDIO_CTRL_BUSY |
0303                AR9331_SW_MDIO_CTRL_MASTER_EN |
0304                FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
0305                FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
0306                FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
0307     if (ret)
0308         goto error;
0309 
0310     ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
0311                        !(val & AR9331_SW_MDIO_CTRL_BUSY),
0312                        AR9331_SW_MDIO_POLL_SLEEP_US,
0313                        AR9331_SW_MDIO_POLL_TIMEOUT_US);
0314     if (ret)
0315         goto error;
0316 
0317     return 0;
0318 error:
0319     dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
0320     return ret;
0321 }
0322 
0323 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
0324 {
0325     struct ar9331_sw_priv *priv = mbus->priv;
0326     struct regmap *regmap = priv->regmap;
0327     u32 val;
0328     int ret;
0329 
0330     ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
0331                AR9331_SW_MDIO_CTRL_BUSY |
0332                AR9331_SW_MDIO_CTRL_MASTER_EN |
0333                AR9331_SW_MDIO_CTRL_CMD_READ |
0334                FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
0335                FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
0336     if (ret)
0337         goto error;
0338 
0339     ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
0340                        !(val & AR9331_SW_MDIO_CTRL_BUSY),
0341                        AR9331_SW_MDIO_POLL_SLEEP_US,
0342                        AR9331_SW_MDIO_POLL_TIMEOUT_US);
0343     if (ret)
0344         goto error;
0345 
0346     ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
0347     if (ret)
0348         goto error;
0349 
0350     return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
0351 
0352 error:
0353     dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
0354     return ret;
0355 }
0356 
0357 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
0358 {
0359     struct device *dev = priv->dev;
0360     struct mii_bus *mbus;
0361     struct device_node *np, *mnp;
0362     int ret;
0363 
0364     np = dev->of_node;
0365 
0366     mbus = devm_mdiobus_alloc(dev);
0367     if (!mbus)
0368         return -ENOMEM;
0369 
0370     mbus->name = np->full_name;
0371     snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
0372 
0373     mbus->read = ar9331_sw_mbus_read;
0374     mbus->write = ar9331_sw_mbus_write;
0375     mbus->priv = priv;
0376     mbus->parent = dev;
0377 
0378     mnp = of_get_child_by_name(np, "mdio");
0379     if (!mnp)
0380         return -ENODEV;
0381 
0382     ret = devm_of_mdiobus_register(dev, mbus, mnp);
0383     of_node_put(mnp);
0384     if (ret)
0385         return ret;
0386 
0387     priv->mbus = mbus;
0388 
0389     return 0;
0390 }
0391 
0392 static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
0393 {
0394     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0395     struct regmap *regmap = priv->regmap;
0396     u32 port_mask, port_ctrl, val;
0397     int ret;
0398 
0399     /* Generate default port settings */
0400     port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE,
0401                    AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD);
0402 
0403     if (dsa_is_cpu_port(ds, port)) {
0404         /* CPU port should be allowed to communicate with all user
0405          * ports.
0406          */
0407         port_mask = dsa_user_ports(ds);
0408         /* Enable Atheros header on CPU port. This will allow us
0409          * communicate with each port separately
0410          */
0411         port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN;
0412     } else if (dsa_is_user_port(ds, port)) {
0413         /* User ports should communicate only with the CPU port.
0414          */
0415         port_mask = BIT(dsa_upstream_port(ds, port));
0416     } else {
0417         /* Other ports do not need to communicate at all */
0418         port_mask = 0;
0419     }
0420 
0421     val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE,
0422              AR9331_SW_8021Q_MODE_NONE) |
0423         FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask);
0424 
0425     ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
0426     if (ret)
0427         goto error;
0428 
0429     ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
0430     if (ret)
0431         goto error;
0432 
0433     return 0;
0434 error:
0435     dev_err(priv->dev, "%s: error: %i\n", __func__, ret);
0436 
0437     return ret;
0438 }
0439 
0440 static int ar9331_sw_setup(struct dsa_switch *ds)
0441 {
0442     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0443     struct regmap *regmap = priv->regmap;
0444     int ret, i;
0445 
0446     ret = ar9331_sw_reset(priv);
0447     if (ret)
0448         return ret;
0449 
0450     /* Reset will set proper defaults. CPU - Port0 will be enabled and
0451      * configured. All other ports (ports 1 - 5) are disabled
0452      */
0453     ret = ar9331_sw_mbus_init(priv);
0454     if (ret)
0455         return ret;
0456 
0457     /* Do not drop broadcast frames */
0458     ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
0459                 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
0460                 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
0461     if (ret)
0462         goto error;
0463 
0464     /* Set max frame size to the maximum supported value */
0465     ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
0466                 AR9331_SW_GLOBAL_CTRL_MFS_M,
0467                 AR9331_SW_GLOBAL_CTRL_MFS_M);
0468     if (ret)
0469         goto error;
0470 
0471     for (i = 0; i < ds->num_ports; i++) {
0472         ret = ar9331_sw_setup_port(ds, i);
0473         if (ret)
0474             goto error;
0475     }
0476 
0477     ds->configure_vlan_while_not_filtering = false;
0478 
0479     return 0;
0480 error:
0481     dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0482     return ret;
0483 }
0484 
0485 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
0486 {
0487     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0488     struct regmap *regmap = priv->regmap;
0489     int ret;
0490 
0491     ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
0492     if (ret)
0493         dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0494 }
0495 
0496 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
0497                             int port,
0498                             enum dsa_tag_protocol m)
0499 {
0500     return DSA_TAG_PROTO_AR9331;
0501 }
0502 
0503 static void ar9331_sw_phylink_get_caps(struct dsa_switch *ds, int port,
0504                        struct phylink_config *config)
0505 {
0506     config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
0507         MAC_10 | MAC_100;
0508 
0509     switch (port) {
0510     case 0:
0511         __set_bit(PHY_INTERFACE_MODE_GMII,
0512               config->supported_interfaces);
0513         config->mac_capabilities |= MAC_1000;
0514         break;
0515     case 1:
0516     case 2:
0517     case 3:
0518     case 4:
0519     case 5:
0520         __set_bit(PHY_INTERFACE_MODE_INTERNAL,
0521               config->supported_interfaces);
0522         break;
0523     }
0524 }
0525 
0526 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
0527                      unsigned int mode,
0528                      const struct phylink_link_state *state)
0529 {
0530     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0531     struct regmap *regmap = priv->regmap;
0532     int ret;
0533 
0534     ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
0535                  AR9331_SW_PORT_STATUS_LINK_EN |
0536                  AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
0537     if (ret)
0538         dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0539 }
0540 
0541 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
0542                         unsigned int mode,
0543                         phy_interface_t interface)
0544 {
0545     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0546     struct ar9331_sw_port *p = &priv->port[port];
0547     struct regmap *regmap = priv->regmap;
0548     int ret;
0549 
0550     ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
0551                  AR9331_SW_PORT_STATUS_MAC_MASK, 0);
0552     if (ret)
0553         dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0554 
0555     cancel_delayed_work_sync(&p->mib_read);
0556 }
0557 
0558 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
0559                       unsigned int mode,
0560                       phy_interface_t interface,
0561                       struct phy_device *phydev,
0562                       int speed, int duplex,
0563                       bool tx_pause, bool rx_pause)
0564 {
0565     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0566     struct ar9331_sw_port *p = &priv->port[port];
0567     struct regmap *regmap = priv->regmap;
0568     u32 val;
0569     int ret;
0570 
0571     schedule_delayed_work(&p->mib_read, 0);
0572 
0573     val = AR9331_SW_PORT_STATUS_MAC_MASK;
0574     switch (speed) {
0575     case SPEED_1000:
0576         val |= AR9331_SW_PORT_STATUS_SPEED_1000;
0577         break;
0578     case SPEED_100:
0579         val |= AR9331_SW_PORT_STATUS_SPEED_100;
0580         break;
0581     case SPEED_10:
0582         val |= AR9331_SW_PORT_STATUS_SPEED_10;
0583         break;
0584     default:
0585         return;
0586     }
0587 
0588     if (duplex)
0589         val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
0590 
0591     if (tx_pause)
0592         val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
0593 
0594     if (rx_pause)
0595         val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
0596 
0597     ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
0598                  AR9331_SW_PORT_STATUS_MAC_MASK |
0599                  AR9331_SW_PORT_STATUS_LINK_MASK,
0600                  val);
0601     if (ret)
0602         dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0603 }
0604 
0605 static void ar9331_read_stats(struct ar9331_sw_port *port)
0606 {
0607     struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
0608     struct ethtool_pause_stats *pstats = &port->pause_stats;
0609     struct rtnl_link_stats64 *stats = &port->stats;
0610     struct ar9331_sw_stats_raw raw;
0611     int ret;
0612 
0613     /* Do the slowest part first, to avoid needless locking for long time */
0614     ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
0615                    &raw, sizeof(raw) / sizeof(u32));
0616     if (ret) {
0617         dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
0618         return;
0619     }
0620     /* All MIB counters are cleared automatically on read */
0621 
0622     spin_lock(&port->stats_lock);
0623 
0624     stats->rx_bytes += raw.rxgoodbyte;
0625     stats->tx_bytes += raw.txbyte;
0626 
0627     stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
0628         raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
0629     stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
0630         raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
0631 
0632     stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
0633     stats->rx_crc_errors += raw.rxfcserr;
0634     stats->rx_frame_errors += raw.rxalignerr;
0635     stats->rx_missed_errors += raw.rxoverflow;
0636     stats->rx_dropped += raw.filtered;
0637     stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
0638         raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
0639 
0640     stats->tx_window_errors += raw.txlatecol;
0641     stats->tx_fifo_errors += raw.txunderrun;
0642     stats->tx_aborted_errors += raw.txabortcol;
0643     stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
0644         raw.txlatecol;
0645 
0646     stats->multicast += raw.rxmulti;
0647     stats->collisions += raw.txcollision;
0648 
0649     pstats->tx_pause_frames += raw.txpause;
0650     pstats->rx_pause_frames += raw.rxpause;
0651 
0652     spin_unlock(&port->stats_lock);
0653 }
0654 
0655 static void ar9331_do_stats_poll(struct work_struct *work)
0656 {
0657     struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
0658                            mib_read.work);
0659 
0660     ar9331_read_stats(port);
0661 
0662     schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
0663 }
0664 
0665 static void ar9331_get_stats64(struct dsa_switch *ds, int port,
0666                    struct rtnl_link_stats64 *s)
0667 {
0668     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0669     struct ar9331_sw_port *p = &priv->port[port];
0670 
0671     spin_lock(&p->stats_lock);
0672     memcpy(s, &p->stats, sizeof(*s));
0673     spin_unlock(&p->stats_lock);
0674 }
0675 
0676 static void ar9331_get_pause_stats(struct dsa_switch *ds, int port,
0677                    struct ethtool_pause_stats *pause_stats)
0678 {
0679     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
0680     struct ar9331_sw_port *p = &priv->port[port];
0681 
0682     spin_lock(&p->stats_lock);
0683     memcpy(pause_stats, &p->pause_stats, sizeof(*pause_stats));
0684     spin_unlock(&p->stats_lock);
0685 }
0686 
0687 static const struct dsa_switch_ops ar9331_sw_ops = {
0688     .get_tag_protocol   = ar9331_sw_get_tag_protocol,
0689     .setup          = ar9331_sw_setup,
0690     .port_disable       = ar9331_sw_port_disable,
0691     .phylink_get_caps   = ar9331_sw_phylink_get_caps,
0692     .phylink_mac_config = ar9331_sw_phylink_mac_config,
0693     .phylink_mac_link_down  = ar9331_sw_phylink_mac_link_down,
0694     .phylink_mac_link_up    = ar9331_sw_phylink_mac_link_up,
0695     .get_stats64        = ar9331_get_stats64,
0696     .get_pause_stats    = ar9331_get_pause_stats,
0697 };
0698 
0699 static irqreturn_t ar9331_sw_irq(int irq, void *data)
0700 {
0701     struct ar9331_sw_priv *priv = data;
0702     struct regmap *regmap = priv->regmap;
0703     u32 stat;
0704     int ret;
0705 
0706     ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
0707     if (ret) {
0708         dev_err(priv->dev, "can't read interrupt status\n");
0709         return IRQ_NONE;
0710     }
0711 
0712     if (!stat)
0713         return IRQ_NONE;
0714 
0715     if (stat & AR9331_SW_GINT_PHY_INT) {
0716         int child_irq;
0717 
0718         child_irq = irq_find_mapping(priv->irqdomain, 0);
0719         handle_nested_irq(child_irq);
0720     }
0721 
0722     ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
0723     if (ret) {
0724         dev_err(priv->dev, "can't write interrupt status\n");
0725         return IRQ_NONE;
0726     }
0727 
0728     return IRQ_HANDLED;
0729 }
0730 
0731 static void ar9331_sw_mask_irq(struct irq_data *d)
0732 {
0733     struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
0734 
0735     priv->irq_mask = 0;
0736 }
0737 
0738 static void ar9331_sw_unmask_irq(struct irq_data *d)
0739 {
0740     struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
0741 
0742     priv->irq_mask = AR9331_SW_GINT_PHY_INT;
0743 }
0744 
0745 static void ar9331_sw_irq_bus_lock(struct irq_data *d)
0746 {
0747     struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
0748 
0749     mutex_lock(&priv->lock_irq);
0750 }
0751 
0752 static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
0753 {
0754     struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
0755     struct regmap *regmap = priv->regmap;
0756     int ret;
0757 
0758     ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
0759                  AR9331_SW_GINT_PHY_INT, priv->irq_mask);
0760     if (ret)
0761         dev_err(priv->dev, "failed to change IRQ mask\n");
0762 
0763     mutex_unlock(&priv->lock_irq);
0764 }
0765 
0766 static struct irq_chip ar9331_sw_irq_chip = {
0767     .name = AR9331_SW_NAME,
0768     .irq_mask = ar9331_sw_mask_irq,
0769     .irq_unmask = ar9331_sw_unmask_irq,
0770     .irq_bus_lock = ar9331_sw_irq_bus_lock,
0771     .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
0772 };
0773 
0774 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
0775                  irq_hw_number_t hwirq)
0776 {
0777     irq_set_chip_data(irq, domain->host_data);
0778     irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
0779     irq_set_nested_thread(irq, 1);
0780     irq_set_noprobe(irq);
0781 
0782     return 0;
0783 }
0784 
0785 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
0786 {
0787     irq_set_nested_thread(irq, 0);
0788     irq_set_chip_and_handler(irq, NULL, NULL);
0789     irq_set_chip_data(irq, NULL);
0790 }
0791 
0792 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
0793     .map = ar9331_sw_irq_map,
0794     .unmap = ar9331_sw_irq_unmap,
0795     .xlate = irq_domain_xlate_onecell,
0796 };
0797 
0798 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
0799 {
0800     struct device_node *np = priv->dev->of_node;
0801     struct device *dev = priv->dev;
0802     int ret, irq;
0803 
0804     irq = of_irq_get(np, 0);
0805     if (irq <= 0) {
0806         dev_err(dev, "failed to get parent IRQ\n");
0807         return irq ? irq : -EINVAL;
0808     }
0809 
0810     mutex_init(&priv->lock_irq);
0811     ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
0812                     IRQF_ONESHOT, AR9331_SW_NAME, priv);
0813     if (ret) {
0814         dev_err(dev, "unable to request irq: %d\n", ret);
0815         return ret;
0816     }
0817 
0818     priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
0819                         priv);
0820     if (!priv->irqdomain) {
0821         dev_err(dev, "failed to create IRQ domain\n");
0822         return -EINVAL;
0823     }
0824 
0825     irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
0826 
0827     return 0;
0828 }
0829 
0830 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
0831 {
0832     u8 r, p;
0833 
0834     p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
0835         FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
0836     r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
0837 
0838     return __mdiobus_write(sbus, p, r, val);
0839 }
0840 
0841 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
0842 {
0843     u8 r, p;
0844 
0845     p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
0846         FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
0847     r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
0848 
0849     return __mdiobus_read(sbus, p, r);
0850 }
0851 
0852 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
0853                 void *val_buf, size_t val_len)
0854 {
0855     struct ar9331_sw_priv *priv = ctx;
0856     struct mii_bus *sbus = priv->sbus;
0857     u32 reg = *(u32 *)reg_buf;
0858     int ret;
0859 
0860     if (reg == AR9331_SW_REG_PAGE) {
0861         /* We cannot read the page selector register from hardware and
0862          * we cache its value in regmap. Return all bits set here,
0863          * that regmap will always write the page on first use.
0864          */
0865         *(u32 *)val_buf = GENMASK(9, 0);
0866         return 0;
0867     }
0868 
0869     mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED);
0870 
0871     ret = __ar9331_mdio_read(sbus, reg);
0872     if (ret < 0)
0873         goto error;
0874 
0875     *(u32 *)val_buf = ret;
0876     ret = __ar9331_mdio_read(sbus, reg + 2);
0877     if (ret < 0)
0878         goto error;
0879 
0880     *(u32 *)val_buf |= ret << 16;
0881 
0882     mutex_unlock(&sbus->mdio_lock);
0883 
0884     return 0;
0885 error:
0886     mutex_unlock(&sbus->mdio_lock);
0887     dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
0888 
0889     return ret;
0890 }
0891 
0892 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
0893 {
0894     struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
0895     struct mii_bus *sbus = priv->sbus;
0896     int ret;
0897 
0898     mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED);
0899     if (reg == AR9331_SW_REG_PAGE) {
0900         ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
0901                       0, val);
0902         if (ret < 0)
0903             goto error;
0904 
0905         mutex_unlock(&sbus->mdio_lock);
0906 
0907         return 0;
0908     }
0909 
0910     /* In case of this switch we work with 32bit registers on top of 16bit
0911      * bus. Some registers (for example access to forwarding database) have
0912      * trigger bit on the first 16bit half of request, the result and
0913      * configuration of request in the second half.
0914      * To make it work properly, we should do the second part of transfer
0915      * before the first one is done.
0916      */
0917     ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
0918                   val >> 16);
0919     if (ret < 0)
0920         goto error;
0921 
0922     ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
0923     if (ret < 0)
0924         goto error;
0925 
0926     mutex_unlock(&sbus->mdio_lock);
0927 
0928     return 0;
0929 
0930 error:
0931     mutex_unlock(&sbus->mdio_lock);
0932     dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
0933 
0934     return ret;
0935 }
0936 
0937 static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
0938 {
0939     u32 reg = *(u32 *)data;
0940     u32 val = *((u32 *)data + 1);
0941 
0942     return ar9331_mdio_write(context, reg, val);
0943 }
0944 
0945 static const struct regmap_range ar9331_valid_regs[] = {
0946     regmap_reg_range(0x0, 0x0),
0947     regmap_reg_range(0x10, 0x14),
0948     regmap_reg_range(0x20, 0x24),
0949     regmap_reg_range(0x2c, 0x30),
0950     regmap_reg_range(0x40, 0x44),
0951     regmap_reg_range(0x50, 0x78),
0952     regmap_reg_range(0x80, 0x98),
0953 
0954     regmap_reg_range(0x100, 0x120),
0955     regmap_reg_range(0x200, 0x220),
0956     regmap_reg_range(0x300, 0x320),
0957     regmap_reg_range(0x400, 0x420),
0958     regmap_reg_range(0x500, 0x520),
0959     regmap_reg_range(0x600, 0x620),
0960 
0961     regmap_reg_range(0x20000, 0x200a4),
0962     regmap_reg_range(0x20100, 0x201a4),
0963     regmap_reg_range(0x20200, 0x202a4),
0964     regmap_reg_range(0x20300, 0x203a4),
0965     regmap_reg_range(0x20400, 0x204a4),
0966     regmap_reg_range(0x20500, 0x205a4),
0967 
0968     /* dummy page selector reg */
0969     regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
0970 };
0971 
0972 static const struct regmap_range ar9331_nonvolatile_regs[] = {
0973     regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
0974 };
0975 
0976 static const struct regmap_range_cfg ar9331_regmap_range[] = {
0977     {
0978         .selector_reg = AR9331_SW_REG_PAGE,
0979         .selector_mask = GENMASK(9, 0),
0980         .selector_shift = 0,
0981 
0982         .window_start = 0,
0983         .window_len = 512,
0984 
0985         .range_min = 0,
0986         .range_max = AR9331_SW_REG_PAGE - 4,
0987     },
0988 };
0989 
0990 static const struct regmap_access_table ar9331_register_set = {
0991     .yes_ranges = ar9331_valid_regs,
0992     .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
0993 };
0994 
0995 static const struct regmap_access_table ar9331_volatile_set = {
0996     .no_ranges = ar9331_nonvolatile_regs,
0997     .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
0998 };
0999 
1000 static const struct regmap_config ar9331_mdio_regmap_config = {
1001     .reg_bits = 32,
1002     .val_bits = 32,
1003     .reg_stride = 4,
1004     .max_register = AR9331_SW_REG_PAGE,
1005 
1006     .ranges = ar9331_regmap_range,
1007     .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
1008 
1009     .volatile_table = &ar9331_volatile_set,
1010     .wr_table = &ar9331_register_set,
1011     .rd_table = &ar9331_register_set,
1012 
1013     .cache_type = REGCACHE_RBTREE,
1014 };
1015 
1016 static struct regmap_bus ar9331_sw_bus = {
1017     .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
1018     .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1019     .read = ar9331_mdio_read,
1020     .write = ar9331_sw_bus_write,
1021     .max_raw_read = 4,
1022     .max_raw_write = 4,
1023 };
1024 
1025 static int ar9331_sw_probe(struct mdio_device *mdiodev)
1026 {
1027     struct ar9331_sw_priv *priv;
1028     struct dsa_switch *ds;
1029     int ret, i;
1030 
1031     priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1032     if (!priv)
1033         return -ENOMEM;
1034 
1035     priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
1036                     &ar9331_mdio_regmap_config);
1037     if (IS_ERR(priv->regmap)) {
1038         ret = PTR_ERR(priv->regmap);
1039         dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
1040         return ret;
1041     }
1042 
1043     priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
1044     if (IS_ERR(priv->sw_reset)) {
1045         dev_err(&mdiodev->dev, "missing switch reset\n");
1046         return PTR_ERR(priv->sw_reset);
1047     }
1048 
1049     priv->sbus = mdiodev->bus;
1050     priv->dev = &mdiodev->dev;
1051 
1052     ret = ar9331_sw_irq_init(priv);
1053     if (ret)
1054         return ret;
1055 
1056     ds = &priv->ds;
1057     ds->dev = &mdiodev->dev;
1058     ds->num_ports = AR9331_SW_PORTS;
1059     ds->priv = priv;
1060     priv->ops = ar9331_sw_ops;
1061     ds->ops = &priv->ops;
1062     dev_set_drvdata(&mdiodev->dev, priv);
1063 
1064     for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1065         struct ar9331_sw_port *port = &priv->port[i];
1066 
1067         port->idx = i;
1068         spin_lock_init(&port->stats_lock);
1069         INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1070     }
1071 
1072     ret = dsa_register_switch(ds);
1073     if (ret)
1074         goto err_remove_irq;
1075 
1076     return 0;
1077 
1078 err_remove_irq:
1079     irq_domain_remove(priv->irqdomain);
1080 
1081     return ret;
1082 }
1083 
1084 static void ar9331_sw_remove(struct mdio_device *mdiodev)
1085 {
1086     struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1087     unsigned int i;
1088 
1089     if (!priv)
1090         return;
1091 
1092     for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1093         struct ar9331_sw_port *port = &priv->port[i];
1094 
1095         cancel_delayed_work_sync(&port->mib_read);
1096     }
1097 
1098     irq_domain_remove(priv->irqdomain);
1099     dsa_unregister_switch(&priv->ds);
1100 
1101     reset_control_assert(priv->sw_reset);
1102 
1103     dev_set_drvdata(&mdiodev->dev, NULL);
1104 }
1105 
1106 static void ar9331_sw_shutdown(struct mdio_device *mdiodev)
1107 {
1108     struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1109 
1110     if (!priv)
1111         return;
1112 
1113     dsa_switch_shutdown(&priv->ds);
1114 
1115     dev_set_drvdata(&mdiodev->dev, NULL);
1116 }
1117 
1118 static const struct of_device_id ar9331_sw_of_match[] = {
1119     { .compatible = "qca,ar9331-switch" },
1120     { },
1121 };
1122 
1123 static struct mdio_driver ar9331_sw_mdio_driver = {
1124     .probe = ar9331_sw_probe,
1125     .remove = ar9331_sw_remove,
1126     .shutdown = ar9331_sw_shutdown,
1127     .mdiodrv.driver = {
1128         .name = AR9331_SW_NAME,
1129         .of_match_table = ar9331_sw_of_match,
1130     },
1131 };
1132 
1133 mdio_module_driver(ar9331_sw_mdio_driver);
1134 
1135 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1136 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1137 MODULE_LICENSE("GPL v2");
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