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0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /* Distributed Switch Architecture VSC9953 driver
0003  * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru>
0004  */
0005 #include <linux/types.h>
0006 #include <soc/mscc/ocelot_vcap.h>
0007 #include <soc/mscc/ocelot_sys.h>
0008 #include <soc/mscc/ocelot.h>
0009 #include <linux/mdio/mdio-mscc-miim.h>
0010 #include <linux/of_mdio.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/pcs-lynx.h>
0013 #include <linux/dsa/ocelot.h>
0014 #include <linux/iopoll.h>
0015 #include "felix.h"
0016 
0017 #define VSC9953_NUM_PORTS           10
0018 
0019 #define VSC9953_VCAP_POLICER_BASE       11
0020 #define VSC9953_VCAP_POLICER_MAX        31
0021 #define VSC9953_VCAP_POLICER_BASE2      120
0022 #define VSC9953_VCAP_POLICER_MAX2       161
0023 
0024 #define VSC9953_PORT_MODE_SERDES        (OCELOT_PORT_MODE_1000BASEX | \
0025                          OCELOT_PORT_MODE_SGMII | \
0026                          OCELOT_PORT_MODE_QSGMII)
0027 
0028 static const u32 vsc9953_port_modes[VSC9953_NUM_PORTS] = {
0029     VSC9953_PORT_MODE_SERDES,
0030     VSC9953_PORT_MODE_SERDES,
0031     VSC9953_PORT_MODE_SERDES,
0032     VSC9953_PORT_MODE_SERDES,
0033     VSC9953_PORT_MODE_SERDES,
0034     VSC9953_PORT_MODE_SERDES,
0035     VSC9953_PORT_MODE_SERDES,
0036     VSC9953_PORT_MODE_SERDES,
0037     OCELOT_PORT_MODE_INTERNAL,
0038     OCELOT_PORT_MODE_INTERNAL,
0039 };
0040 
0041 static const u32 vsc9953_ana_regmap[] = {
0042     REG(ANA_ADVLEARN,           0x00b500),
0043     REG(ANA_VLANMASK,           0x00b504),
0044     REG_RESERVED(ANA_PORT_B_DOMAIN),
0045     REG(ANA_ANAGEFIL,           0x00b50c),
0046     REG(ANA_ANEVENTS,           0x00b510),
0047     REG(ANA_STORMLIMIT_BURST,       0x00b514),
0048     REG(ANA_STORMLIMIT_CFG,         0x00b518),
0049     REG(ANA_ISOLATED_PORTS,         0x00b528),
0050     REG(ANA_COMMUNITY_PORTS,        0x00b52c),
0051     REG(ANA_AUTOAGE,            0x00b530),
0052     REG(ANA_MACTOPTIONS,            0x00b534),
0053     REG(ANA_LEARNDISC,          0x00b538),
0054     REG(ANA_AGENCTRL,           0x00b53c),
0055     REG(ANA_MIRRORPORTS,            0x00b540),
0056     REG(ANA_EMIRRORPORTS,           0x00b544),
0057     REG(ANA_FLOODING,           0x00b548),
0058     REG(ANA_FLOODING_IPMC,          0x00b54c),
0059     REG(ANA_SFLOW_CFG,          0x00b550),
0060     REG(ANA_PORT_MODE,          0x00b57c),
0061     REG_RESERVED(ANA_CUT_THRU_CFG),
0062     REG(ANA_PGID_PGID,          0x00b600),
0063     REG(ANA_TABLES_ANMOVED,         0x00b4ac),
0064     REG(ANA_TABLES_MACHDATA,        0x00b4b0),
0065     REG(ANA_TABLES_MACLDATA,        0x00b4b4),
0066     REG_RESERVED(ANA_TABLES_STREAMDATA),
0067     REG(ANA_TABLES_MACACCESS,       0x00b4b8),
0068     REG(ANA_TABLES_MACTINDX,        0x00b4bc),
0069     REG(ANA_TABLES_VLANACCESS,      0x00b4c0),
0070     REG(ANA_TABLES_VLANTIDX,        0x00b4c4),
0071     REG_RESERVED(ANA_TABLES_ISDXACCESS),
0072     REG_RESERVED(ANA_TABLES_ISDXTIDX),
0073     REG(ANA_TABLES_ENTRYLIM,        0x00b480),
0074     REG_RESERVED(ANA_TABLES_PTP_ID_HIGH),
0075     REG_RESERVED(ANA_TABLES_PTP_ID_LOW),
0076     REG_RESERVED(ANA_TABLES_STREAMACCESS),
0077     REG_RESERVED(ANA_TABLES_STREAMTIDX),
0078     REG_RESERVED(ANA_TABLES_SEQ_HISTORY),
0079     REG_RESERVED(ANA_TABLES_SEQ_MASK),
0080     REG_RESERVED(ANA_TABLES_SFID_MASK),
0081     REG_RESERVED(ANA_TABLES_SFIDACCESS),
0082     REG_RESERVED(ANA_TABLES_SFIDTIDX),
0083     REG_RESERVED(ANA_MSTI_STATE),
0084     REG_RESERVED(ANA_OAM_UPM_LM_CNT),
0085     REG_RESERVED(ANA_SG_ACCESS_CTRL),
0086     REG_RESERVED(ANA_SG_CONFIG_REG_1),
0087     REG_RESERVED(ANA_SG_CONFIG_REG_2),
0088     REG_RESERVED(ANA_SG_CONFIG_REG_3),
0089     REG_RESERVED(ANA_SG_CONFIG_REG_4),
0090     REG_RESERVED(ANA_SG_CONFIG_REG_5),
0091     REG_RESERVED(ANA_SG_GCL_GS_CONFIG),
0092     REG_RESERVED(ANA_SG_GCL_TI_CONFIG),
0093     REG_RESERVED(ANA_SG_STATUS_REG_1),
0094     REG_RESERVED(ANA_SG_STATUS_REG_2),
0095     REG_RESERVED(ANA_SG_STATUS_REG_3),
0096     REG(ANA_PORT_VLAN_CFG,          0x000000),
0097     REG(ANA_PORT_DROP_CFG,          0x000004),
0098     REG(ANA_PORT_QOS_CFG,           0x000008),
0099     REG(ANA_PORT_VCAP_CFG,          0x00000c),
0100     REG(ANA_PORT_VCAP_S1_KEY_CFG,       0x000010),
0101     REG(ANA_PORT_VCAP_S2_CFG,       0x00001c),
0102     REG(ANA_PORT_PCP_DEI_MAP,       0x000020),
0103     REG(ANA_PORT_CPU_FWD_CFG,       0x000060),
0104     REG(ANA_PORT_CPU_FWD_BPDU_CFG,      0x000064),
0105     REG(ANA_PORT_CPU_FWD_GARP_CFG,      0x000068),
0106     REG(ANA_PORT_CPU_FWD_CCM_CFG,       0x00006c),
0107     REG(ANA_PORT_PORT_CFG,          0x000070),
0108     REG(ANA_PORT_POL_CFG,           0x000074),
0109     REG_RESERVED(ANA_PORT_PTP_CFG),
0110     REG_RESERVED(ANA_PORT_PTP_DLY1_CFG),
0111     REG_RESERVED(ANA_PORT_PTP_DLY2_CFG),
0112     REG_RESERVED(ANA_PORT_SFID_CFG),
0113     REG(ANA_PFC_PFC_CFG,            0x00c000),
0114     REG_RESERVED(ANA_PFC_PFC_TIMER),
0115     REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
0116     REG_RESERVED(ANA_IPT_IPT),
0117     REG_RESERVED(ANA_PPT_PPT),
0118     REG_RESERVED(ANA_FID_MAP_FID_MAP),
0119     REG(ANA_AGGR_CFG,           0x00c600),
0120     REG(ANA_CPUQ_CFG,           0x00c604),
0121     REG_RESERVED(ANA_CPUQ_CFG2),
0122     REG(ANA_CPUQ_8021_CFG,          0x00c60c),
0123     REG(ANA_DSCP_CFG,           0x00c64c),
0124     REG(ANA_DSCP_REWR_CFG,          0x00c74c),
0125     REG(ANA_VCAP_RNG_TYPE_CFG,      0x00c78c),
0126     REG(ANA_VCAP_RNG_VAL_CFG,       0x00c7ac),
0127     REG_RESERVED(ANA_VRAP_CFG),
0128     REG_RESERVED(ANA_VRAP_HDR_DATA),
0129     REG_RESERVED(ANA_VRAP_HDR_MASK),
0130     REG(ANA_DISCARD_CFG,            0x00c7d8),
0131     REG(ANA_FID_CFG,            0x00c7dc),
0132     REG(ANA_POL_PIR_CFG,            0x00a000),
0133     REG(ANA_POL_CIR_CFG,            0x00a004),
0134     REG(ANA_POL_MODE_CFG,           0x00a008),
0135     REG(ANA_POL_PIR_STATE,          0x00a00c),
0136     REG(ANA_POL_CIR_STATE,          0x00a010),
0137     REG_RESERVED(ANA_POL_STATE),
0138     REG(ANA_POL_FLOWC,          0x00c280),
0139     REG(ANA_POL_HYST,           0x00c2ec),
0140     REG_RESERVED(ANA_POL_MISC_CFG),
0141 };
0142 
0143 static const u32 vsc9953_qs_regmap[] = {
0144     REG(QS_XTR_GRP_CFG,         0x000000),
0145     REG(QS_XTR_RD,              0x000008),
0146     REG(QS_XTR_FRM_PRUNING,         0x000010),
0147     REG(QS_XTR_FLUSH,           0x000018),
0148     REG(QS_XTR_DATA_PRESENT,        0x00001c),
0149     REG(QS_XTR_CFG,             0x000020),
0150     REG(QS_INJ_GRP_CFG,         0x000024),
0151     REG(QS_INJ_WR,              0x00002c),
0152     REG(QS_INJ_CTRL,            0x000034),
0153     REG(QS_INJ_STATUS,          0x00003c),
0154     REG(QS_INJ_ERR,             0x000040),
0155     REG_RESERVED(QS_INH_DBG),
0156 };
0157 
0158 static const u32 vsc9953_vcap_regmap[] = {
0159     /* VCAP_CORE_CFG */
0160     REG(VCAP_CORE_UPDATE_CTRL,      0x000000),
0161     REG(VCAP_CORE_MV_CFG,           0x000004),
0162     /* VCAP_CORE_CACHE */
0163     REG(VCAP_CACHE_ENTRY_DAT,       0x000008),
0164     REG(VCAP_CACHE_MASK_DAT,        0x000108),
0165     REG(VCAP_CACHE_ACTION_DAT,      0x000208),
0166     REG(VCAP_CACHE_CNT_DAT,         0x000308),
0167     REG(VCAP_CACHE_TG_DAT,          0x000388),
0168     /* VCAP_CONST */
0169     REG(VCAP_CONST_VCAP_VER,        0x000398),
0170     REG(VCAP_CONST_ENTRY_WIDTH,     0x00039c),
0171     REG(VCAP_CONST_ENTRY_CNT,       0x0003a0),
0172     REG(VCAP_CONST_ENTRY_SWCNT,     0x0003a4),
0173     REG(VCAP_CONST_ENTRY_TG_WIDTH,      0x0003a8),
0174     REG(VCAP_CONST_ACTION_DEF_CNT,      0x0003ac),
0175     REG(VCAP_CONST_ACTION_WIDTH,        0x0003b0),
0176     REG(VCAP_CONST_CNT_WIDTH,       0x0003b4),
0177     REG_RESERVED(VCAP_CONST_CORE_CNT),
0178     REG_RESERVED(VCAP_CONST_IF_CNT),
0179 };
0180 
0181 static const u32 vsc9953_qsys_regmap[] = {
0182     REG(QSYS_PORT_MODE,         0x003600),
0183     REG(QSYS_SWITCH_PORT_MODE,      0x003630),
0184     REG(QSYS_STAT_CNT_CFG,          0x00365c),
0185     REG(QSYS_EEE_CFG,           0x003660),
0186     REG(QSYS_EEE_THRES,         0x003688),
0187     REG(QSYS_IGR_NO_SHARING,        0x00368c),
0188     REG(QSYS_EGR_NO_SHARING,        0x003690),
0189     REG(QSYS_SW_STATUS,         0x003694),
0190     REG(QSYS_EXT_CPU_CFG,           0x0036c0),
0191     REG_RESERVED(QSYS_PAD_CFG),
0192     REG(QSYS_CPU_GROUP_MAP,         0x0036c8),
0193     REG_RESERVED(QSYS_QMAP),
0194     REG_RESERVED(QSYS_ISDX_SGRP),
0195     REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
0196     REG_RESERVED(QSYS_TFRM_MISC),
0197     REG_RESERVED(QSYS_TFRM_PORT_DLY),
0198     REG_RESERVED(QSYS_TFRM_TIMER_CFG_1),
0199     REG_RESERVED(QSYS_TFRM_TIMER_CFG_2),
0200     REG_RESERVED(QSYS_TFRM_TIMER_CFG_3),
0201     REG_RESERVED(QSYS_TFRM_TIMER_CFG_4),
0202     REG_RESERVED(QSYS_TFRM_TIMER_CFG_5),
0203     REG_RESERVED(QSYS_TFRM_TIMER_CFG_6),
0204     REG_RESERVED(QSYS_TFRM_TIMER_CFG_7),
0205     REG_RESERVED(QSYS_TFRM_TIMER_CFG_8),
0206     REG(QSYS_RED_PROFILE,           0x003724),
0207     REG(QSYS_RES_QOS_MODE,          0x003764),
0208     REG(QSYS_RES_CFG,           0x004000),
0209     REG(QSYS_RES_STAT,          0x004004),
0210     REG(QSYS_EGR_DROP_MODE,         0x003768),
0211     REG(QSYS_EQ_CTRL,           0x00376c),
0212     REG_RESERVED(QSYS_EVENTS_CORE),
0213     REG_RESERVED(QSYS_QMAXSDU_CFG_0),
0214     REG_RESERVED(QSYS_QMAXSDU_CFG_1),
0215     REG_RESERVED(QSYS_QMAXSDU_CFG_2),
0216     REG_RESERVED(QSYS_QMAXSDU_CFG_3),
0217     REG_RESERVED(QSYS_QMAXSDU_CFG_4),
0218     REG_RESERVED(QSYS_QMAXSDU_CFG_5),
0219     REG_RESERVED(QSYS_QMAXSDU_CFG_6),
0220     REG_RESERVED(QSYS_QMAXSDU_CFG_7),
0221     REG_RESERVED(QSYS_PREEMPTION_CFG),
0222     REG(QSYS_CIR_CFG,           0x000000),
0223     REG_RESERVED(QSYS_EIR_CFG),
0224     REG(QSYS_SE_CFG,            0x000008),
0225     REG(QSYS_SE_DWRR_CFG,           0x00000c),
0226     REG_RESERVED(QSYS_SE_CONNECT),
0227     REG_RESERVED(QSYS_SE_DLB_SENSE),
0228     REG(QSYS_CIR_STATE,         0x000044),
0229     REG_RESERVED(QSYS_EIR_STATE),
0230     REG_RESERVED(QSYS_SE_STATE),
0231     REG(QSYS_HSCH_MISC_CFG,         0x003774),
0232     REG_RESERVED(QSYS_TAG_CONFIG),
0233     REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL),
0234     REG_RESERVED(QSYS_PORT_MAX_SDU),
0235     REG_RESERVED(QSYS_PARAM_CFG_REG_1),
0236     REG_RESERVED(QSYS_PARAM_CFG_REG_2),
0237     REG_RESERVED(QSYS_PARAM_CFG_REG_3),
0238     REG_RESERVED(QSYS_PARAM_CFG_REG_4),
0239     REG_RESERVED(QSYS_PARAM_CFG_REG_5),
0240     REG_RESERVED(QSYS_GCL_CFG_REG_1),
0241     REG_RESERVED(QSYS_GCL_CFG_REG_2),
0242     REG_RESERVED(QSYS_PARAM_STATUS_REG_1),
0243     REG_RESERVED(QSYS_PARAM_STATUS_REG_2),
0244     REG_RESERVED(QSYS_PARAM_STATUS_REG_3),
0245     REG_RESERVED(QSYS_PARAM_STATUS_REG_4),
0246     REG_RESERVED(QSYS_PARAM_STATUS_REG_5),
0247     REG_RESERVED(QSYS_PARAM_STATUS_REG_6),
0248     REG_RESERVED(QSYS_PARAM_STATUS_REG_7),
0249     REG_RESERVED(QSYS_PARAM_STATUS_REG_8),
0250     REG_RESERVED(QSYS_PARAM_STATUS_REG_9),
0251     REG_RESERVED(QSYS_GCL_STATUS_REG_1),
0252     REG_RESERVED(QSYS_GCL_STATUS_REG_2),
0253 };
0254 
0255 static const u32 vsc9953_rew_regmap[] = {
0256     REG(REW_PORT_VLAN_CFG,          0x000000),
0257     REG(REW_TAG_CFG,            0x000004),
0258     REG(REW_PORT_CFG,           0x000008),
0259     REG(REW_DSCP_CFG,           0x00000c),
0260     REG(REW_PCP_DEI_QOS_MAP_CFG,        0x000010),
0261     REG_RESERVED(REW_PTP_CFG),
0262     REG_RESERVED(REW_PTP_DLY1_CFG),
0263     REG_RESERVED(REW_RED_TAG_CFG),
0264     REG(REW_DSCP_REMAP_DP1_CFG,     0x000610),
0265     REG(REW_DSCP_REMAP_CFG,         0x000710),
0266     REG_RESERVED(REW_STAT_CFG),
0267     REG_RESERVED(REW_REW_STICKY),
0268     REG_RESERVED(REW_PPT),
0269 };
0270 
0271 static const u32 vsc9953_sys_regmap[] = {
0272     REG(SYS_COUNT_RX_OCTETS,        0x000000),
0273     REG(SYS_COUNT_RX_UNICAST,       0x000004),
0274     REG(SYS_COUNT_RX_MULTICAST,     0x000008),
0275     REG(SYS_COUNT_RX_BROADCAST,     0x00000c),
0276     REG(SYS_COUNT_RX_SHORTS,        0x000010),
0277     REG(SYS_COUNT_RX_FRAGMENTS,     0x000014),
0278     REG(SYS_COUNT_RX_JABBERS,       0x000018),
0279     REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,    0x00001c),
0280     REG(SYS_COUNT_RX_SYM_ERRS,      0x000020),
0281     REG(SYS_COUNT_RX_64,            0x000024),
0282     REG(SYS_COUNT_RX_65_127,        0x000028),
0283     REG(SYS_COUNT_RX_128_255,       0x00002c),
0284     REG(SYS_COUNT_RX_256_511,       0x000030),
0285     REG(SYS_COUNT_RX_512_1023,      0x000034),
0286     REG(SYS_COUNT_RX_1024_1526,     0x000038),
0287     REG(SYS_COUNT_RX_1527_MAX,      0x00003c),
0288     REG(SYS_COUNT_RX_PAUSE,         0x000040),
0289     REG(SYS_COUNT_RX_CONTROL,       0x000044),
0290     REG(SYS_COUNT_RX_LONGS,         0x000048),
0291     REG(SYS_COUNT_RX_CLASSIFIED_DROPS,  0x00004c),
0292     REG(SYS_COUNT_RX_RED_PRIO_0,        0x000050),
0293     REG(SYS_COUNT_RX_RED_PRIO_1,        0x000054),
0294     REG(SYS_COUNT_RX_RED_PRIO_2,        0x000058),
0295     REG(SYS_COUNT_RX_RED_PRIO_3,        0x00005c),
0296     REG(SYS_COUNT_RX_RED_PRIO_4,        0x000060),
0297     REG(SYS_COUNT_RX_RED_PRIO_5,        0x000064),
0298     REG(SYS_COUNT_RX_RED_PRIO_6,        0x000068),
0299     REG(SYS_COUNT_RX_RED_PRIO_7,        0x00006c),
0300     REG(SYS_COUNT_RX_YELLOW_PRIO_0,     0x000070),
0301     REG(SYS_COUNT_RX_YELLOW_PRIO_1,     0x000074),
0302     REG(SYS_COUNT_RX_YELLOW_PRIO_2,     0x000078),
0303     REG(SYS_COUNT_RX_YELLOW_PRIO_3,     0x00007c),
0304     REG(SYS_COUNT_RX_YELLOW_PRIO_4,     0x000080),
0305     REG(SYS_COUNT_RX_YELLOW_PRIO_5,     0x000084),
0306     REG(SYS_COUNT_RX_YELLOW_PRIO_6,     0x000088),
0307     REG(SYS_COUNT_RX_YELLOW_PRIO_7,     0x00008c),
0308     REG(SYS_COUNT_RX_GREEN_PRIO_0,      0x000090),
0309     REG(SYS_COUNT_RX_GREEN_PRIO_1,      0x000094),
0310     REG(SYS_COUNT_RX_GREEN_PRIO_2,      0x000098),
0311     REG(SYS_COUNT_RX_GREEN_PRIO_3,      0x00009c),
0312     REG(SYS_COUNT_RX_GREEN_PRIO_4,      0x0000a0),
0313     REG(SYS_COUNT_RX_GREEN_PRIO_5,      0x0000a4),
0314     REG(SYS_COUNT_RX_GREEN_PRIO_6,      0x0000a8),
0315     REG(SYS_COUNT_RX_GREEN_PRIO_7,      0x0000ac),
0316     REG(SYS_COUNT_TX_OCTETS,        0x000100),
0317     REG(SYS_COUNT_TX_UNICAST,       0x000104),
0318     REG(SYS_COUNT_TX_MULTICAST,     0x000108),
0319     REG(SYS_COUNT_TX_BROADCAST,     0x00010c),
0320     REG(SYS_COUNT_TX_COLLISION,     0x000110),
0321     REG(SYS_COUNT_TX_DROPS,         0x000114),
0322     REG(SYS_COUNT_TX_PAUSE,         0x000118),
0323     REG(SYS_COUNT_TX_64,            0x00011c),
0324     REG(SYS_COUNT_TX_65_127,        0x000120),
0325     REG(SYS_COUNT_TX_128_255,       0x000124),
0326     REG(SYS_COUNT_TX_256_511,       0x000128),
0327     REG(SYS_COUNT_TX_512_1023,      0x00012c),
0328     REG(SYS_COUNT_TX_1024_1526,     0x000130),
0329     REG(SYS_COUNT_TX_1527_MAX,      0x000134),
0330     REG(SYS_COUNT_TX_YELLOW_PRIO_0,     0x000138),
0331     REG(SYS_COUNT_TX_YELLOW_PRIO_1,     0x00013c),
0332     REG(SYS_COUNT_TX_YELLOW_PRIO_2,     0x000140),
0333     REG(SYS_COUNT_TX_YELLOW_PRIO_3,     0x000144),
0334     REG(SYS_COUNT_TX_YELLOW_PRIO_4,     0x000148),
0335     REG(SYS_COUNT_TX_YELLOW_PRIO_5,     0x00014c),
0336     REG(SYS_COUNT_TX_YELLOW_PRIO_6,     0x000150),
0337     REG(SYS_COUNT_TX_YELLOW_PRIO_7,     0x000154),
0338     REG(SYS_COUNT_TX_GREEN_PRIO_0,      0x000158),
0339     REG(SYS_COUNT_TX_GREEN_PRIO_1,      0x00015c),
0340     REG(SYS_COUNT_TX_GREEN_PRIO_2,      0x000160),
0341     REG(SYS_COUNT_TX_GREEN_PRIO_3,      0x000164),
0342     REG(SYS_COUNT_TX_GREEN_PRIO_4,      0x000168),
0343     REG(SYS_COUNT_TX_GREEN_PRIO_5,      0x00016c),
0344     REG(SYS_COUNT_TX_GREEN_PRIO_6,      0x000170),
0345     REG(SYS_COUNT_TX_GREEN_PRIO_7,      0x000174),
0346     REG(SYS_COUNT_TX_AGING,         0x000178),
0347     REG(SYS_COUNT_DROP_LOCAL,       0x000200),
0348     REG(SYS_COUNT_DROP_TAIL,        0x000204),
0349     REG(SYS_COUNT_DROP_YELLOW_PRIO_0,   0x000208),
0350     REG(SYS_COUNT_DROP_YELLOW_PRIO_1,   0x00020c),
0351     REG(SYS_COUNT_DROP_YELLOW_PRIO_2,   0x000210),
0352     REG(SYS_COUNT_DROP_YELLOW_PRIO_3,   0x000214),
0353     REG(SYS_COUNT_DROP_YELLOW_PRIO_4,   0x000218),
0354     REG(SYS_COUNT_DROP_YELLOW_PRIO_5,   0x00021c),
0355     REG(SYS_COUNT_DROP_YELLOW_PRIO_6,   0x000220),
0356     REG(SYS_COUNT_DROP_YELLOW_PRIO_7,   0x000224),
0357     REG(SYS_COUNT_DROP_GREEN_PRIO_0,    0x000228),
0358     REG(SYS_COUNT_DROP_GREEN_PRIO_1,    0x00022c),
0359     REG(SYS_COUNT_DROP_GREEN_PRIO_2,    0x000230),
0360     REG(SYS_COUNT_DROP_GREEN_PRIO_3,    0x000234),
0361     REG(SYS_COUNT_DROP_GREEN_PRIO_4,    0x000238),
0362     REG(SYS_COUNT_DROP_GREEN_PRIO_5,    0x00023c),
0363     REG(SYS_COUNT_DROP_GREEN_PRIO_6,    0x000240),
0364     REG(SYS_COUNT_DROP_GREEN_PRIO_7,    0x000244),
0365     REG(SYS_RESET_CFG,          0x000318),
0366     REG_RESERVED(SYS_SR_ETYPE_CFG),
0367     REG(SYS_VLAN_ETYPE_CFG,         0x000320),
0368     REG(SYS_PORT_MODE,          0x000324),
0369     REG(SYS_FRONT_PORT_MODE,        0x000354),
0370     REG(SYS_FRM_AGING,          0x00037c),
0371     REG(SYS_STAT_CFG,           0x000380),
0372     REG_RESERVED(SYS_SW_STATUS),
0373     REG_RESERVED(SYS_MISC_CFG),
0374     REG_RESERVED(SYS_REW_MAC_HIGH_CFG),
0375     REG_RESERVED(SYS_REW_MAC_LOW_CFG),
0376     REG_RESERVED(SYS_TIMESTAMP_OFFSET),
0377     REG(SYS_PAUSE_CFG,          0x00044c),
0378     REG(SYS_PAUSE_TOT_CFG,          0x000478),
0379     REG(SYS_ATOP,               0x00047c),
0380     REG(SYS_ATOP_TOT_CFG,           0x0004a8),
0381     REG(SYS_MAC_FC_CFG,         0x0004ac),
0382     REG(SYS_MMGT,               0x0004d4),
0383     REG_RESERVED(SYS_MMGT_FAST),
0384     REG_RESERVED(SYS_EVENTS_DIF),
0385     REG_RESERVED(SYS_EVENTS_CORE),
0386     REG_RESERVED(SYS_CNT),
0387     REG_RESERVED(SYS_PTP_STATUS),
0388     REG_RESERVED(SYS_PTP_TXSTAMP),
0389     REG_RESERVED(SYS_PTP_NXT),
0390     REG_RESERVED(SYS_PTP_CFG),
0391     REG_RESERVED(SYS_RAM_INIT),
0392     REG_RESERVED(SYS_CM_ADDR),
0393     REG_RESERVED(SYS_CM_DATA_WR),
0394     REG_RESERVED(SYS_CM_DATA_RD),
0395     REG_RESERVED(SYS_CM_OP),
0396     REG_RESERVED(SYS_CM_DATA),
0397 };
0398 
0399 static const u32 vsc9953_gcb_regmap[] = {
0400     REG(GCB_SOFT_RST,           0x000008),
0401     REG(GCB_MIIM_MII_STATUS,        0x0000ac),
0402     REG(GCB_MIIM_MII_CMD,           0x0000b4),
0403     REG(GCB_MIIM_MII_DATA,          0x0000b8),
0404 };
0405 
0406 static const u32 vsc9953_dev_gmii_regmap[] = {
0407     REG(DEV_CLOCK_CFG,          0x0),
0408     REG(DEV_PORT_MISC,          0x4),
0409     REG_RESERVED(DEV_EVENTS),
0410     REG(DEV_EEE_CFG,            0xc),
0411     REG_RESERVED(DEV_RX_PATH_DELAY),
0412     REG_RESERVED(DEV_TX_PATH_DELAY),
0413     REG_RESERVED(DEV_PTP_PREDICT_CFG),
0414     REG(DEV_MAC_ENA_CFG,            0x10),
0415     REG(DEV_MAC_MODE_CFG,           0x14),
0416     REG(DEV_MAC_MAXLEN_CFG,         0x18),
0417     REG(DEV_MAC_TAGS_CFG,           0x1c),
0418     REG(DEV_MAC_ADV_CHK_CFG,        0x20),
0419     REG(DEV_MAC_IFG_CFG,            0x24),
0420     REG(DEV_MAC_HDX_CFG,            0x28),
0421     REG_RESERVED(DEV_MAC_DBG_CFG),
0422     REG(DEV_MAC_FC_MAC_LOW_CFG,     0x30),
0423     REG(DEV_MAC_FC_MAC_HIGH_CFG,        0x34),
0424     REG(DEV_MAC_STICKY,         0x38),
0425     REG_RESERVED(PCS1G_CFG),
0426     REG_RESERVED(PCS1G_MODE_CFG),
0427     REG_RESERVED(PCS1G_SD_CFG),
0428     REG_RESERVED(PCS1G_ANEG_CFG),
0429     REG_RESERVED(PCS1G_ANEG_NP_CFG),
0430     REG_RESERVED(PCS1G_LB_CFG),
0431     REG_RESERVED(PCS1G_DBG_CFG),
0432     REG_RESERVED(PCS1G_CDET_CFG),
0433     REG_RESERVED(PCS1G_ANEG_STATUS),
0434     REG_RESERVED(PCS1G_ANEG_NP_STATUS),
0435     REG_RESERVED(PCS1G_LINK_STATUS),
0436     REG_RESERVED(PCS1G_LINK_DOWN_CNT),
0437     REG_RESERVED(PCS1G_STICKY),
0438     REG_RESERVED(PCS1G_DEBUG_STATUS),
0439     REG_RESERVED(PCS1G_LPI_CFG),
0440     REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
0441     REG_RESERVED(PCS1G_LPI_STATUS),
0442     REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
0443     REG_RESERVED(PCS1G_TSTPAT_STATUS),
0444     REG_RESERVED(DEV_PCS_FX100_CFG),
0445     REG_RESERVED(DEV_PCS_FX100_STATUS),
0446 };
0447 
0448 static const u32 *vsc9953_regmap[TARGET_MAX] = {
0449     [ANA]       = vsc9953_ana_regmap,
0450     [QS]        = vsc9953_qs_regmap,
0451     [QSYS]      = vsc9953_qsys_regmap,
0452     [REW]       = vsc9953_rew_regmap,
0453     [SYS]       = vsc9953_sys_regmap,
0454     [S0]        = vsc9953_vcap_regmap,
0455     [S1]        = vsc9953_vcap_regmap,
0456     [S2]        = vsc9953_vcap_regmap,
0457     [GCB]       = vsc9953_gcb_regmap,
0458     [DEV_GMII]  = vsc9953_dev_gmii_regmap,
0459 };
0460 
0461 /* Addresses are relative to the device's base address */
0462 static const struct resource vsc9953_target_io_res[TARGET_MAX] = {
0463     [ANA] = {
0464         .start  = 0x0280000,
0465         .end    = 0x028ffff,
0466         .name   = "ana",
0467     },
0468     [QS] = {
0469         .start  = 0x0080000,
0470         .end    = 0x00800ff,
0471         .name   = "qs",
0472     },
0473     [QSYS] = {
0474         .start  = 0x0200000,
0475         .end    = 0x021ffff,
0476         .name   = "qsys",
0477     },
0478     [REW] = {
0479         .start  = 0x0030000,
0480         .end    = 0x003ffff,
0481         .name   = "rew",
0482     },
0483     [SYS] = {
0484         .start  = 0x0010000,
0485         .end    = 0x001ffff,
0486         .name   = "sys",
0487     },
0488     [S0] = {
0489         .start  = 0x0040000,
0490         .end    = 0x00403ff,
0491         .name   = "s0",
0492     },
0493     [S1] = {
0494         .start  = 0x0050000,
0495         .end    = 0x00503ff,
0496         .name   = "s1",
0497     },
0498     [S2] = {
0499         .start  = 0x0060000,
0500         .end    = 0x00603ff,
0501         .name   = "s2",
0502     },
0503     [PTP] = {
0504         .start  = 0x0090000,
0505         .end    = 0x00900cb,
0506         .name   = "ptp",
0507     },
0508     [GCB] = {
0509         .start  = 0x0070000,
0510         .end    = 0x00701ff,
0511         .name   = "devcpu_gcb",
0512     },
0513 };
0514 
0515 static const struct resource vsc9953_port_io_res[] = {
0516     {
0517         .start  = 0x0100000,
0518         .end    = 0x010ffff,
0519         .name   = "port0",
0520     },
0521     {
0522         .start  = 0x0110000,
0523         .end    = 0x011ffff,
0524         .name   = "port1",
0525     },
0526     {
0527         .start  = 0x0120000,
0528         .end    = 0x012ffff,
0529         .name   = "port2",
0530     },
0531     {
0532         .start  = 0x0130000,
0533         .end    = 0x013ffff,
0534         .name   = "port3",
0535     },
0536     {
0537         .start  = 0x0140000,
0538         .end    = 0x014ffff,
0539         .name   = "port4",
0540     },
0541     {
0542         .start  = 0x0150000,
0543         .end    = 0x015ffff,
0544         .name   = "port5",
0545     },
0546     {
0547         .start  = 0x0160000,
0548         .end    = 0x016ffff,
0549         .name   = "port6",
0550     },
0551     {
0552         .start  = 0x0170000,
0553         .end    = 0x017ffff,
0554         .name   = "port7",
0555     },
0556     {
0557         .start  = 0x0180000,
0558         .end    = 0x018ffff,
0559         .name   = "port8",
0560     },
0561     {
0562         .start  = 0x0190000,
0563         .end    = 0x019ffff,
0564         .name   = "port9",
0565     },
0566 };
0567 
0568 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {
0569     [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10),
0570     [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9),
0571     [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
0572     [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
0573     [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
0574     [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
0575     [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
0576     [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
0577     [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
0578     [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
0579     [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
0580     [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
0581     [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
0582     [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
0583     [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
0584     [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
0585     [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
0586     [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
0587     [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
0588     [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
0589     [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
0590     [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
0591     [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
0592     [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
0593     [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
0594     [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
0595     [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
0596     [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
0597     [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7),
0598     [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6),
0599     [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5),
0600     [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
0601     [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2),
0602     [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3),
0603     /* Replicated per number of ports (11), register size 4 per port */
0604     [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4),
0605     [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4),
0606     [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4),
0607     [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4),
0608     [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4),
0609     [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4),
0610     [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4),
0611     [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4),
0612     [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4),
0613     [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4),
0614     [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4),
0615 };
0616 
0617 static const struct ocelot_stat_layout vsc9953_stats_layout[OCELOT_NUM_STATS] = {
0618     [OCELOT_STAT_RX_OCTETS] = {
0619         .name = "rx_octets",
0620         .reg = SYS_COUNT_RX_OCTETS,
0621     },
0622     [OCELOT_STAT_RX_UNICAST] = {
0623         .name = "rx_unicast",
0624         .reg = SYS_COUNT_RX_UNICAST,
0625     },
0626     [OCELOT_STAT_RX_MULTICAST] = {
0627         .name = "rx_multicast",
0628         .reg = SYS_COUNT_RX_MULTICAST,
0629     },
0630     [OCELOT_STAT_RX_BROADCAST] = {
0631         .name = "rx_broadcast",
0632         .reg = SYS_COUNT_RX_BROADCAST,
0633     },
0634     [OCELOT_STAT_RX_SHORTS] = {
0635         .name = "rx_shorts",
0636         .reg = SYS_COUNT_RX_SHORTS,
0637     },
0638     [OCELOT_STAT_RX_FRAGMENTS] = {
0639         .name = "rx_fragments",
0640         .reg = SYS_COUNT_RX_FRAGMENTS,
0641     },
0642     [OCELOT_STAT_RX_JABBERS] = {
0643         .name = "rx_jabbers",
0644         .reg = SYS_COUNT_RX_JABBERS,
0645     },
0646     [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = {
0647         .name = "rx_crc_align_errs",
0648         .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS,
0649     },
0650     [OCELOT_STAT_RX_SYM_ERRS] = {
0651         .name = "rx_sym_errs",
0652         .reg = SYS_COUNT_RX_SYM_ERRS,
0653     },
0654     [OCELOT_STAT_RX_64] = {
0655         .name = "rx_frames_below_65_octets",
0656         .reg = SYS_COUNT_RX_64,
0657     },
0658     [OCELOT_STAT_RX_65_127] = {
0659         .name = "rx_frames_65_to_127_octets",
0660         .reg = SYS_COUNT_RX_65_127,
0661     },
0662     [OCELOT_STAT_RX_128_255] = {
0663         .name = "rx_frames_128_to_255_octets",
0664         .reg = SYS_COUNT_RX_128_255,
0665     },
0666     [OCELOT_STAT_RX_256_511] = {
0667         .name = "rx_frames_256_to_511_octets",
0668         .reg = SYS_COUNT_RX_256_511,
0669     },
0670     [OCELOT_STAT_RX_512_1023] = {
0671         .name = "rx_frames_512_to_1023_octets",
0672         .reg = SYS_COUNT_RX_512_1023,
0673     },
0674     [OCELOT_STAT_RX_1024_1526] = {
0675         .name = "rx_frames_1024_to_1526_octets",
0676         .reg = SYS_COUNT_RX_1024_1526,
0677     },
0678     [OCELOT_STAT_RX_1527_MAX] = {
0679         .name = "rx_frames_over_1526_octets",
0680         .reg = SYS_COUNT_RX_1527_MAX,
0681     },
0682     [OCELOT_STAT_RX_PAUSE] = {
0683         .name = "rx_pause",
0684         .reg = SYS_COUNT_RX_PAUSE,
0685     },
0686     [OCELOT_STAT_RX_CONTROL] = {
0687         .name = "rx_control",
0688         .reg = SYS_COUNT_RX_CONTROL,
0689     },
0690     [OCELOT_STAT_RX_LONGS] = {
0691         .name = "rx_longs",
0692         .reg = SYS_COUNT_RX_LONGS,
0693     },
0694     [OCELOT_STAT_RX_CLASSIFIED_DROPS] = {
0695         .name = "rx_classified_drops",
0696         .reg = SYS_COUNT_RX_CLASSIFIED_DROPS,
0697     },
0698     [OCELOT_STAT_RX_RED_PRIO_0] = {
0699         .name = "rx_red_prio_0",
0700         .reg = SYS_COUNT_RX_RED_PRIO_0,
0701     },
0702     [OCELOT_STAT_RX_RED_PRIO_1] = {
0703         .name = "rx_red_prio_1",
0704         .reg = SYS_COUNT_RX_RED_PRIO_1,
0705     },
0706     [OCELOT_STAT_RX_RED_PRIO_2] = {
0707         .name = "rx_red_prio_2",
0708         .reg = SYS_COUNT_RX_RED_PRIO_2,
0709     },
0710     [OCELOT_STAT_RX_RED_PRIO_3] = {
0711         .name = "rx_red_prio_3",
0712         .reg = SYS_COUNT_RX_RED_PRIO_3,
0713     },
0714     [OCELOT_STAT_RX_RED_PRIO_4] = {
0715         .name = "rx_red_prio_4",
0716         .reg = SYS_COUNT_RX_RED_PRIO_4,
0717     },
0718     [OCELOT_STAT_RX_RED_PRIO_5] = {
0719         .name = "rx_red_prio_5",
0720         .reg = SYS_COUNT_RX_RED_PRIO_5,
0721     },
0722     [OCELOT_STAT_RX_RED_PRIO_6] = {
0723         .name = "rx_red_prio_6",
0724         .reg = SYS_COUNT_RX_RED_PRIO_6,
0725     },
0726     [OCELOT_STAT_RX_RED_PRIO_7] = {
0727         .name = "rx_red_prio_7",
0728         .reg = SYS_COUNT_RX_RED_PRIO_7,
0729     },
0730     [OCELOT_STAT_RX_YELLOW_PRIO_0] = {
0731         .name = "rx_yellow_prio_0",
0732         .reg = SYS_COUNT_RX_YELLOW_PRIO_0,
0733     },
0734     [OCELOT_STAT_RX_YELLOW_PRIO_1] = {
0735         .name = "rx_yellow_prio_1",
0736         .reg = SYS_COUNT_RX_YELLOW_PRIO_1,
0737     },
0738     [OCELOT_STAT_RX_YELLOW_PRIO_2] = {
0739         .name = "rx_yellow_prio_2",
0740         .reg = SYS_COUNT_RX_YELLOW_PRIO_2,
0741     },
0742     [OCELOT_STAT_RX_YELLOW_PRIO_3] = {
0743         .name = "rx_yellow_prio_3",
0744         .reg = SYS_COUNT_RX_YELLOW_PRIO_3,
0745     },
0746     [OCELOT_STAT_RX_YELLOW_PRIO_4] = {
0747         .name = "rx_yellow_prio_4",
0748         .reg = SYS_COUNT_RX_YELLOW_PRIO_4,
0749     },
0750     [OCELOT_STAT_RX_YELLOW_PRIO_5] = {
0751         .name = "rx_yellow_prio_5",
0752         .reg = SYS_COUNT_RX_YELLOW_PRIO_5,
0753     },
0754     [OCELOT_STAT_RX_YELLOW_PRIO_6] = {
0755         .name = "rx_yellow_prio_6",
0756         .reg = SYS_COUNT_RX_YELLOW_PRIO_6,
0757     },
0758     [OCELOT_STAT_RX_YELLOW_PRIO_7] = {
0759         .name = "rx_yellow_prio_7",
0760         .reg = SYS_COUNT_RX_YELLOW_PRIO_7,
0761     },
0762     [OCELOT_STAT_RX_GREEN_PRIO_0] = {
0763         .name = "rx_green_prio_0",
0764         .reg = SYS_COUNT_RX_GREEN_PRIO_0,
0765     },
0766     [OCELOT_STAT_RX_GREEN_PRIO_1] = {
0767         .name = "rx_green_prio_1",
0768         .reg = SYS_COUNT_RX_GREEN_PRIO_1,
0769     },
0770     [OCELOT_STAT_RX_GREEN_PRIO_2] = {
0771         .name = "rx_green_prio_2",
0772         .reg = SYS_COUNT_RX_GREEN_PRIO_2,
0773     },
0774     [OCELOT_STAT_RX_GREEN_PRIO_3] = {
0775         .name = "rx_green_prio_3",
0776         .reg = SYS_COUNT_RX_GREEN_PRIO_3,
0777     },
0778     [OCELOT_STAT_RX_GREEN_PRIO_4] = {
0779         .name = "rx_green_prio_4",
0780         .reg = SYS_COUNT_RX_GREEN_PRIO_4,
0781     },
0782     [OCELOT_STAT_RX_GREEN_PRIO_5] = {
0783         .name = "rx_green_prio_5",
0784         .reg = SYS_COUNT_RX_GREEN_PRIO_5,
0785     },
0786     [OCELOT_STAT_RX_GREEN_PRIO_6] = {
0787         .name = "rx_green_prio_6",
0788         .reg = SYS_COUNT_RX_GREEN_PRIO_6,
0789     },
0790     [OCELOT_STAT_RX_GREEN_PRIO_7] = {
0791         .name = "rx_green_prio_7",
0792         .reg = SYS_COUNT_RX_GREEN_PRIO_7,
0793     },
0794     [OCELOT_STAT_TX_OCTETS] = {
0795         .name = "tx_octets",
0796         .reg = SYS_COUNT_TX_OCTETS,
0797     },
0798     [OCELOT_STAT_TX_UNICAST] = {
0799         .name = "tx_unicast",
0800         .reg = SYS_COUNT_TX_UNICAST,
0801     },
0802     [OCELOT_STAT_TX_MULTICAST] = {
0803         .name = "tx_multicast",
0804         .reg = SYS_COUNT_TX_MULTICAST,
0805     },
0806     [OCELOT_STAT_TX_BROADCAST] = {
0807         .name = "tx_broadcast",
0808         .reg = SYS_COUNT_TX_BROADCAST,
0809     },
0810     [OCELOT_STAT_TX_COLLISION] = {
0811         .name = "tx_collision",
0812         .reg = SYS_COUNT_TX_COLLISION,
0813     },
0814     [OCELOT_STAT_TX_DROPS] = {
0815         .name = "tx_drops",
0816         .reg = SYS_COUNT_TX_DROPS,
0817     },
0818     [OCELOT_STAT_TX_PAUSE] = {
0819         .name = "tx_pause",
0820         .reg = SYS_COUNT_TX_PAUSE,
0821     },
0822     [OCELOT_STAT_TX_64] = {
0823         .name = "tx_frames_below_65_octets",
0824         .reg = SYS_COUNT_TX_64,
0825     },
0826     [OCELOT_STAT_TX_65_127] = {
0827         .name = "tx_frames_65_to_127_octets",
0828         .reg = SYS_COUNT_TX_65_127,
0829     },
0830     [OCELOT_STAT_TX_128_255] = {
0831         .name = "tx_frames_128_255_octets",
0832         .reg = SYS_COUNT_TX_128_255,
0833     },
0834     [OCELOT_STAT_TX_256_511] = {
0835         .name = "tx_frames_256_511_octets",
0836         .reg = SYS_COUNT_TX_256_511,
0837     },
0838     [OCELOT_STAT_TX_512_1023] = {
0839         .name = "tx_frames_512_1023_octets",
0840         .reg = SYS_COUNT_TX_512_1023,
0841     },
0842     [OCELOT_STAT_TX_1024_1526] = {
0843         .name = "tx_frames_1024_1526_octets",
0844         .reg = SYS_COUNT_TX_1024_1526,
0845     },
0846     [OCELOT_STAT_TX_1527_MAX] = {
0847         .name = "tx_frames_over_1526_octets",
0848         .reg = SYS_COUNT_TX_1527_MAX,
0849     },
0850     [OCELOT_STAT_TX_YELLOW_PRIO_0] = {
0851         .name = "tx_yellow_prio_0",
0852         .reg = SYS_COUNT_TX_YELLOW_PRIO_0,
0853     },
0854     [OCELOT_STAT_TX_YELLOW_PRIO_1] = {
0855         .name = "tx_yellow_prio_1",
0856         .reg = SYS_COUNT_TX_YELLOW_PRIO_1,
0857     },
0858     [OCELOT_STAT_TX_YELLOW_PRIO_2] = {
0859         .name = "tx_yellow_prio_2",
0860         .reg = SYS_COUNT_TX_YELLOW_PRIO_2,
0861     },
0862     [OCELOT_STAT_TX_YELLOW_PRIO_3] = {
0863         .name = "tx_yellow_prio_3",
0864         .reg = SYS_COUNT_TX_YELLOW_PRIO_3,
0865     },
0866     [OCELOT_STAT_TX_YELLOW_PRIO_4] = {
0867         .name = "tx_yellow_prio_4",
0868         .reg = SYS_COUNT_TX_YELLOW_PRIO_4,
0869     },
0870     [OCELOT_STAT_TX_YELLOW_PRIO_5] = {
0871         .name = "tx_yellow_prio_5",
0872         .reg = SYS_COUNT_TX_YELLOW_PRIO_5,
0873     },
0874     [OCELOT_STAT_TX_YELLOW_PRIO_6] = {
0875         .name = "tx_yellow_prio_6",
0876         .reg = SYS_COUNT_TX_YELLOW_PRIO_6,
0877     },
0878     [OCELOT_STAT_TX_YELLOW_PRIO_7] = {
0879         .name = "tx_yellow_prio_7",
0880         .reg = SYS_COUNT_TX_YELLOW_PRIO_7,
0881     },
0882     [OCELOT_STAT_TX_GREEN_PRIO_0] = {
0883         .name = "tx_green_prio_0",
0884         .reg = SYS_COUNT_TX_GREEN_PRIO_0,
0885     },
0886     [OCELOT_STAT_TX_GREEN_PRIO_1] = {
0887         .name = "tx_green_prio_1",
0888         .reg = SYS_COUNT_TX_GREEN_PRIO_1,
0889     },
0890     [OCELOT_STAT_TX_GREEN_PRIO_2] = {
0891         .name = "tx_green_prio_2",
0892         .reg = SYS_COUNT_TX_GREEN_PRIO_2,
0893     },
0894     [OCELOT_STAT_TX_GREEN_PRIO_3] = {
0895         .name = "tx_green_prio_3",
0896         .reg = SYS_COUNT_TX_GREEN_PRIO_3,
0897     },
0898     [OCELOT_STAT_TX_GREEN_PRIO_4] = {
0899         .name = "tx_green_prio_4",
0900         .reg = SYS_COUNT_TX_GREEN_PRIO_4,
0901     },
0902     [OCELOT_STAT_TX_GREEN_PRIO_5] = {
0903         .name = "tx_green_prio_5",
0904         .reg = SYS_COUNT_TX_GREEN_PRIO_5,
0905     },
0906     [OCELOT_STAT_TX_GREEN_PRIO_6] = {
0907         .name = "tx_green_prio_6",
0908         .reg = SYS_COUNT_TX_GREEN_PRIO_6,
0909     },
0910     [OCELOT_STAT_TX_GREEN_PRIO_7] = {
0911         .name = "tx_green_prio_7",
0912         .reg = SYS_COUNT_TX_GREEN_PRIO_7,
0913     },
0914     [OCELOT_STAT_TX_AGED] = {
0915         .name = "tx_aged",
0916         .reg = SYS_COUNT_TX_AGING,
0917     },
0918     [OCELOT_STAT_DROP_LOCAL] = {
0919         .name = "drop_local",
0920         .reg = SYS_COUNT_DROP_LOCAL,
0921     },
0922     [OCELOT_STAT_DROP_TAIL] = {
0923         .name = "drop_tail",
0924         .reg = SYS_COUNT_DROP_TAIL,
0925     },
0926     [OCELOT_STAT_DROP_YELLOW_PRIO_0] = {
0927         .name = "drop_yellow_prio_0",
0928         .reg = SYS_COUNT_DROP_YELLOW_PRIO_0,
0929     },
0930     [OCELOT_STAT_DROP_YELLOW_PRIO_1] = {
0931         .name = "drop_yellow_prio_1",
0932         .reg = SYS_COUNT_DROP_YELLOW_PRIO_1,
0933     },
0934     [OCELOT_STAT_DROP_YELLOW_PRIO_2] = {
0935         .name = "drop_yellow_prio_2",
0936         .reg = SYS_COUNT_DROP_YELLOW_PRIO_2,
0937     },
0938     [OCELOT_STAT_DROP_YELLOW_PRIO_3] = {
0939         .name = "drop_yellow_prio_3",
0940         .reg = SYS_COUNT_DROP_YELLOW_PRIO_3,
0941     },
0942     [OCELOT_STAT_DROP_YELLOW_PRIO_4] = {
0943         .name = "drop_yellow_prio_4",
0944         .reg = SYS_COUNT_DROP_YELLOW_PRIO_4,
0945     },
0946     [OCELOT_STAT_DROP_YELLOW_PRIO_5] = {
0947         .name = "drop_yellow_prio_5",
0948         .reg = SYS_COUNT_DROP_YELLOW_PRIO_5,
0949     },
0950     [OCELOT_STAT_DROP_YELLOW_PRIO_6] = {
0951         .name = "drop_yellow_prio_6",
0952         .reg = SYS_COUNT_DROP_YELLOW_PRIO_6,
0953     },
0954     [OCELOT_STAT_DROP_YELLOW_PRIO_7] = {
0955         .name = "drop_yellow_prio_7",
0956         .reg = SYS_COUNT_DROP_YELLOW_PRIO_7,
0957     },
0958     [OCELOT_STAT_DROP_GREEN_PRIO_0] = {
0959         .name = "drop_green_prio_0",
0960         .reg = SYS_COUNT_DROP_GREEN_PRIO_0,
0961     },
0962     [OCELOT_STAT_DROP_GREEN_PRIO_1] = {
0963         .name = "drop_green_prio_1",
0964         .reg = SYS_COUNT_DROP_GREEN_PRIO_1,
0965     },
0966     [OCELOT_STAT_DROP_GREEN_PRIO_2] = {
0967         .name = "drop_green_prio_2",
0968         .reg = SYS_COUNT_DROP_GREEN_PRIO_2,
0969     },
0970     [OCELOT_STAT_DROP_GREEN_PRIO_3] = {
0971         .name = "drop_green_prio_3",
0972         .reg = SYS_COUNT_DROP_GREEN_PRIO_3,
0973     },
0974     [OCELOT_STAT_DROP_GREEN_PRIO_4] = {
0975         .name = "drop_green_prio_4",
0976         .reg = SYS_COUNT_DROP_GREEN_PRIO_4,
0977     },
0978     [OCELOT_STAT_DROP_GREEN_PRIO_5] = {
0979         .name = "drop_green_prio_5",
0980         .reg = SYS_COUNT_DROP_GREEN_PRIO_5,
0981     },
0982     [OCELOT_STAT_DROP_GREEN_PRIO_6] = {
0983         .name = "drop_green_prio_6",
0984         .reg = SYS_COUNT_DROP_GREEN_PRIO_6,
0985     },
0986     [OCELOT_STAT_DROP_GREEN_PRIO_7] = {
0987         .name = "drop_green_prio_7",
0988         .reg = SYS_COUNT_DROP_GREEN_PRIO_7,
0989     },
0990 };
0991 
0992 static const struct vcap_field vsc9953_vcap_es0_keys[] = {
0993     [VCAP_ES0_EGR_PORT]         = {  0,  4},
0994     [VCAP_ES0_IGR_PORT]         = {  4,  4},
0995     [VCAP_ES0_RSV]              = {  8,  2},
0996     [VCAP_ES0_L2_MC]            = { 10,  1},
0997     [VCAP_ES0_L2_BC]            = { 11,  1},
0998     [VCAP_ES0_VID]              = { 12, 12},
0999     [VCAP_ES0_DP]               = { 24,  1},
1000     [VCAP_ES0_PCP]              = { 25,  3},
1001 };
1002 
1003 static const struct vcap_field vsc9953_vcap_es0_actions[] = {
1004     [VCAP_ES0_ACT_PUSH_OUTER_TAG]       = {  0,  2},
1005     [VCAP_ES0_ACT_PUSH_INNER_TAG]       = {  2,  1},
1006     [VCAP_ES0_ACT_TAG_A_TPID_SEL]       = {  3,  2},
1007     [VCAP_ES0_ACT_TAG_A_VID_SEL]        = {  5,  1},
1008     [VCAP_ES0_ACT_TAG_A_PCP_SEL]        = {  6,  2},
1009     [VCAP_ES0_ACT_TAG_A_DEI_SEL]        = {  8,  2},
1010     [VCAP_ES0_ACT_TAG_B_TPID_SEL]       = { 10,  2},
1011     [VCAP_ES0_ACT_TAG_B_VID_SEL]        = { 12,  1},
1012     [VCAP_ES0_ACT_TAG_B_PCP_SEL]        = { 13,  2},
1013     [VCAP_ES0_ACT_TAG_B_DEI_SEL]        = { 15,  2},
1014     [VCAP_ES0_ACT_VID_A_VAL]        = { 17, 12},
1015     [VCAP_ES0_ACT_PCP_A_VAL]        = { 29,  3},
1016     [VCAP_ES0_ACT_DEI_A_VAL]        = { 32,  1},
1017     [VCAP_ES0_ACT_VID_B_VAL]        = { 33, 12},
1018     [VCAP_ES0_ACT_PCP_B_VAL]        = { 45,  3},
1019     [VCAP_ES0_ACT_DEI_B_VAL]        = { 48,  1},
1020     [VCAP_ES0_ACT_RSV]          = { 49, 24},
1021     [VCAP_ES0_ACT_HIT_STICKY]       = { 73,  1},
1022 };
1023 
1024 static const struct vcap_field vsc9953_vcap_is1_keys[] = {
1025     [VCAP_IS1_HK_TYPE]          = {  0,   1},
1026     [VCAP_IS1_HK_LOOKUP]            = {  1,   2},
1027     [VCAP_IS1_HK_IGR_PORT_MASK]     = {  3,  11},
1028     [VCAP_IS1_HK_RSV]           = { 14,  10},
1029     /* VCAP_IS1_HK_OAM_Y1731 not supported */
1030     [VCAP_IS1_HK_L2_MC]         = { 24,   1},
1031     [VCAP_IS1_HK_L2_BC]         = { 25,   1},
1032     [VCAP_IS1_HK_IP_MC]         = { 26,   1},
1033     [VCAP_IS1_HK_VLAN_TAGGED]       = { 27,   1},
1034     [VCAP_IS1_HK_VLAN_DBL_TAGGED]       = { 28,   1},
1035     [VCAP_IS1_HK_TPID]          = { 29,   1},
1036     [VCAP_IS1_HK_VID]           = { 30,  12},
1037     [VCAP_IS1_HK_DEI]           = { 42,   1},
1038     [VCAP_IS1_HK_PCP]           = { 43,   3},
1039     /* Specific Fields for IS1 Half Key S1_NORMAL */
1040     [VCAP_IS1_HK_L2_SMAC]           = { 46,  48},
1041     [VCAP_IS1_HK_ETYPE_LEN]         = { 94,   1},
1042     [VCAP_IS1_HK_ETYPE]         = { 95,  16},
1043     [VCAP_IS1_HK_IP_SNAP]           = {111,   1},
1044     [VCAP_IS1_HK_IP4]           = {112,   1},
1045     /* Layer-3 Information */
1046     [VCAP_IS1_HK_L3_FRAGMENT]       = {113,   1},
1047     [VCAP_IS1_HK_L3_FRAG_OFS_GT0]       = {114,   1},
1048     [VCAP_IS1_HK_L3_OPTIONS]        = {115,   1},
1049     [VCAP_IS1_HK_L3_DSCP]           = {116,   6},
1050     [VCAP_IS1_HK_L3_IP4_SIP]        = {122,  32},
1051     /* Layer-4 Information */
1052     [VCAP_IS1_HK_TCP_UDP]           = {154,   1},
1053     [VCAP_IS1_HK_TCP]           = {155,   1},
1054     [VCAP_IS1_HK_L4_SPORT]          = {156,  16},
1055     [VCAP_IS1_HK_L4_RNG]            = {172,   8},
1056     /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
1057     [VCAP_IS1_HK_IP4_INNER_TPID]            = { 46,   1},
1058     [VCAP_IS1_HK_IP4_INNER_VID]     = { 47,  12},
1059     [VCAP_IS1_HK_IP4_INNER_DEI]     = { 59,   1},
1060     [VCAP_IS1_HK_IP4_INNER_PCP]     = { 60,   3},
1061     [VCAP_IS1_HK_IP4_IP4]           = { 63,   1},
1062     [VCAP_IS1_HK_IP4_L3_FRAGMENT]       = { 64,   1},
1063     [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]   = { 65,   1},
1064     [VCAP_IS1_HK_IP4_L3_OPTIONS]        = { 66,   1},
1065     [VCAP_IS1_HK_IP4_L3_DSCP]       = { 67,   6},
1066     [VCAP_IS1_HK_IP4_L3_IP4_DIP]        = { 73,  32},
1067     [VCAP_IS1_HK_IP4_L3_IP4_SIP]        = {105,  32},
1068     [VCAP_IS1_HK_IP4_L3_PROTO]      = {137,   8},
1069     [VCAP_IS1_HK_IP4_TCP_UDP]       = {145,   1},
1070     [VCAP_IS1_HK_IP4_TCP]           = {146,   1},
1071     [VCAP_IS1_HK_IP4_L4_RNG]        = {147,   8},
1072     [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = {155,  32},
1073 };
1074 
1075 static const struct vcap_field vsc9953_vcap_is1_actions[] = {
1076     [VCAP_IS1_ACT_DSCP_ENA]         = {  0,  1},
1077     [VCAP_IS1_ACT_DSCP_VAL]         = {  1,  6},
1078     [VCAP_IS1_ACT_QOS_ENA]          = {  7,  1},
1079     [VCAP_IS1_ACT_QOS_VAL]          = {  8,  3},
1080     [VCAP_IS1_ACT_DP_ENA]           = { 11,  1},
1081     [VCAP_IS1_ACT_DP_VAL]           = { 12,  1},
1082     [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]    = { 13,  8},
1083     [VCAP_IS1_ACT_PAG_VAL]          = { 21,  8},
1084     [VCAP_IS1_ACT_RSV]          = { 29, 11},
1085     [VCAP_IS1_ACT_VID_REPLACE_ENA]      = { 40,  1},
1086     [VCAP_IS1_ACT_VID_ADD_VAL]      = { 41, 12},
1087     [VCAP_IS1_ACT_FID_SEL]          = { 53,  2},
1088     [VCAP_IS1_ACT_FID_VAL]          = { 55, 13},
1089     [VCAP_IS1_ACT_PCP_DEI_ENA]      = { 68,  1},
1090     [VCAP_IS1_ACT_PCP_VAL]          = { 69,  3},
1091     [VCAP_IS1_ACT_DEI_VAL]          = { 72,  1},
1092     [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]     = { 73,  1},
1093     [VCAP_IS1_ACT_VLAN_POP_CNT]     = { 74,  2},
1094     [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]  = { 76,  4},
1095     [VCAP_IS1_ACT_HIT_STICKY]       = { 80,  1},
1096 };
1097 
1098 static struct vcap_field vsc9953_vcap_is2_keys[] = {
1099     /* Common: 41 bits */
1100     [VCAP_IS2_TYPE]             = {  0,   4},
1101     [VCAP_IS2_HK_FIRST]         = {  4,   1},
1102     [VCAP_IS2_HK_PAG]           = {  5,   8},
1103     [VCAP_IS2_HK_IGR_PORT_MASK]     = { 13,  11},
1104     [VCAP_IS2_HK_RSV2]          = { 24,   1},
1105     [VCAP_IS2_HK_HOST_MATCH]        = { 25,   1},
1106     [VCAP_IS2_HK_L2_MC]         = { 26,   1},
1107     [VCAP_IS2_HK_L2_BC]         = { 27,   1},
1108     [VCAP_IS2_HK_VLAN_TAGGED]       = { 28,   1},
1109     [VCAP_IS2_HK_VID]           = { 29,  12},
1110     [VCAP_IS2_HK_DEI]           = { 41,   1},
1111     [VCAP_IS2_HK_PCP]           = { 42,   3},
1112     /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
1113     [VCAP_IS2_HK_L2_DMAC]           = { 45,  48},
1114     [VCAP_IS2_HK_L2_SMAC]           = { 93,  48},
1115     /* MAC_ETYPE (TYPE=000) */
1116     [VCAP_IS2_HK_MAC_ETYPE_ETYPE]       = {141,  16},
1117     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157,  16},
1118     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173,   8},
1119     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181,   3},
1120     /* MAC_LLC (TYPE=001) */
1121     [VCAP_IS2_HK_MAC_LLC_L2_LLC]        = {141,  40},
1122     /* MAC_SNAP (TYPE=010) */
1123     [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]      = {141,  40},
1124     /* MAC_ARP (TYPE=011) */
1125     [VCAP_IS2_HK_MAC_ARP_SMAC]      = { 45,  48},
1126     [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93,   1},
1127     [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 94,   1},
1128     [VCAP_IS2_HK_MAC_ARP_LEN_OK]        = { 95,   1},
1129     [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]  = { 96,   1},
1130     [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]  = { 97,   1},
1131     [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 98,   1},
1132     [VCAP_IS2_HK_MAC_ARP_OPCODE]        = { 99,   2},
1133     [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]    = {101,  32},
1134     [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]    = {133,  32},
1135     [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]    = {165,   1},
1136     /* IP4_TCP_UDP / IP4_OTHER common */
1137     [VCAP_IS2_HK_IP4]           = { 45,   1},
1138     [VCAP_IS2_HK_L3_FRAGMENT]       = { 46,   1},
1139     [VCAP_IS2_HK_L3_FRAG_OFS_GT0]       = { 47,   1},
1140     [VCAP_IS2_HK_L3_OPTIONS]        = { 48,   1},
1141     [VCAP_IS2_HK_IP4_L3_TTL_GT0]        = { 49,   1},
1142     [VCAP_IS2_HK_L3_TOS]            = { 50,   8},
1143     [VCAP_IS2_HK_L3_IP4_DIP]        = { 58,  32},
1144     [VCAP_IS2_HK_L3_IP4_SIP]        = { 90,  32},
1145     [VCAP_IS2_HK_DIP_EQ_SIP]        = {122,   1},
1146     /* IP4_TCP_UDP (TYPE=100) */
1147     [VCAP_IS2_HK_TCP]           = {123,   1},
1148     [VCAP_IS2_HK_L4_DPORT]          = {124,  16},
1149     [VCAP_IS2_HK_L4_SPORT]          = {140,  16},
1150     [VCAP_IS2_HK_L4_RNG]            = {156,   8},
1151     [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]     = {164,   1},
1152     [VCAP_IS2_HK_L4_SEQUENCE_EQ0]       = {165,   1},
1153     [VCAP_IS2_HK_L4_FIN]            = {166,   1},
1154     [VCAP_IS2_HK_L4_SYN]            = {167,   1},
1155     [VCAP_IS2_HK_L4_RST]            = {168,   1},
1156     [VCAP_IS2_HK_L4_PSH]            = {169,   1},
1157     [VCAP_IS2_HK_L4_ACK]            = {170,   1},
1158     [VCAP_IS2_HK_L4_URG]            = {171,   1},
1159     /* IP4_OTHER (TYPE=101) */
1160     [VCAP_IS2_HK_IP4_L3_PROTO]      = {123,   8},
1161     [VCAP_IS2_HK_L3_PAYLOAD]        = {131,  56},
1162     /* IP6_STD (TYPE=110) */
1163     [VCAP_IS2_HK_IP6_L3_TTL_GT0]        = { 45,   1},
1164     [VCAP_IS2_HK_L3_IP6_SIP]        = { 46, 128},
1165     [VCAP_IS2_HK_IP6_L3_PROTO]      = {174,   8},
1166 };
1167 
1168 static struct vcap_field vsc9953_vcap_is2_actions[] = {
1169     [VCAP_IS2_ACT_HIT_ME_ONCE]      = {  0,  1},
1170     [VCAP_IS2_ACT_CPU_COPY_ENA]     = {  1,  1},
1171     [VCAP_IS2_ACT_CPU_QU_NUM]       = {  2,  3},
1172     [VCAP_IS2_ACT_MASK_MODE]        = {  5,  2},
1173     [VCAP_IS2_ACT_MIRROR_ENA]       = {  7,  1},
1174     [VCAP_IS2_ACT_LRN_DIS]          = {  8,  1},
1175     [VCAP_IS2_ACT_POLICE_ENA]       = {  9,  1},
1176     [VCAP_IS2_ACT_POLICE_IDX]       = { 10,  8},
1177     [VCAP_IS2_ACT_POLICE_VCAP_ONLY]     = { 21,  1},
1178     [VCAP_IS2_ACT_PORT_MASK]        = { 22, 10},
1179     [VCAP_IS2_ACT_ACL_ID]           = { 44,  6},
1180     [VCAP_IS2_ACT_HIT_CNT]          = { 50, 32},
1181 };
1182 
1183 static struct vcap_props vsc9953_vcap_props[] = {
1184     [VCAP_ES0] = {
1185         .action_type_width = 0,
1186         .action_table = {
1187             [ES0_ACTION_TYPE_NORMAL] = {
1188                 .width = 73, /* HIT_STICKY not included */
1189                 .count = 1,
1190             },
1191         },
1192         .target = S0,
1193         .keys = vsc9953_vcap_es0_keys,
1194         .actions = vsc9953_vcap_es0_actions,
1195     },
1196     [VCAP_IS1] = {
1197         .action_type_width = 0,
1198         .action_table = {
1199             [IS1_ACTION_TYPE_NORMAL] = {
1200                 .width = 80, /* HIT_STICKY not included */
1201                 .count = 4,
1202             },
1203         },
1204         .target = S1,
1205         .keys = vsc9953_vcap_is1_keys,
1206         .actions = vsc9953_vcap_is1_actions,
1207     },
1208     [VCAP_IS2] = {
1209         .action_type_width = 1,
1210         .action_table = {
1211             [IS2_ACTION_TYPE_NORMAL] = {
1212                 .width = 50, /* HIT_CNT not included */
1213                 .count = 2
1214             },
1215             [IS2_ACTION_TYPE_SMAC_SIP] = {
1216                 .width = 6,
1217                 .count = 4
1218             },
1219         },
1220         .target = S2,
1221         .keys = vsc9953_vcap_is2_keys,
1222         .actions = vsc9953_vcap_is2_actions,
1223     },
1224 };
1225 
1226 #define VSC9953_INIT_TIMEOUT            50000
1227 #define VSC9953_GCB_RST_SLEEP           100
1228 #define VSC9953_SYS_RAMINIT_SLEEP       80
1229 
1230 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
1231 {
1232     int val;
1233 
1234     ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
1235 
1236     return val;
1237 }
1238 
1239 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
1240 {
1241     int val;
1242 
1243     ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val);
1244 
1245     return val;
1246 }
1247 
1248 
1249 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
1250  * MEM_INIT is in SYS:SYSTEM:RESET_CFG
1251  * MEM_ENA is in SYS:SYSTEM:RESET_CFG
1252  */
1253 static int vsc9953_reset(struct ocelot *ocelot)
1254 {
1255     int val, err;
1256 
1257     /* soft-reset the switch core */
1258     ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
1259 
1260     err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val,
1261                  VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT);
1262     if (err) {
1263         dev_err(ocelot->dev, "timeout: switch core reset\n");
1264         return err;
1265     }
1266 
1267     /* initialize switch mem ~40us */
1268     ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
1269     ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1);
1270 
1271     err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val,
1272                  VSC9953_SYS_RAMINIT_SLEEP,
1273                  VSC9953_INIT_TIMEOUT);
1274     if (err) {
1275         dev_err(ocelot->dev, "timeout: switch sram init\n");
1276         return err;
1277     }
1278 
1279     /* enable switch core */
1280     ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
1281 
1282     return 0;
1283 }
1284 
1285 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port,
1286                      unsigned long *supported,
1287                      struct phylink_link_state *state)
1288 {
1289     __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1290 
1291     phylink_set_port_modes(mask);
1292     phylink_set(mask, Autoneg);
1293     phylink_set(mask, Pause);
1294     phylink_set(mask, Asym_Pause);
1295     phylink_set(mask, 10baseT_Full);
1296     phylink_set(mask, 10baseT_Half);
1297     phylink_set(mask, 100baseT_Full);
1298     phylink_set(mask, 100baseT_Half);
1299     phylink_set(mask, 1000baseT_Full);
1300     phylink_set(mask, 1000baseX_Full);
1301 
1302     if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
1303         phylink_set(mask, 2500baseT_Full);
1304         phylink_set(mask, 2500baseX_Full);
1305     }
1306 
1307     linkmode_and(supported, supported, mask);
1308     linkmode_and(state->advertising, state->advertising, mask);
1309 }
1310 
1311 /* Watermark encode
1312  * Bit 9:   Unit; 0:1, 1:16
1313  * Bit 8-0: Value to be multiplied with unit
1314  */
1315 static u16 vsc9953_wm_enc(u16 value)
1316 {
1317     WARN_ON(value >= 16 * BIT(9));
1318 
1319     if (value >= BIT(9))
1320         return BIT(9) | (value / 16);
1321 
1322     return value;
1323 }
1324 
1325 static u16 vsc9953_wm_dec(u16 wm)
1326 {
1327     WARN_ON(wm & ~GENMASK(9, 0));
1328 
1329     if (wm & BIT(9))
1330         return (wm & GENMASK(8, 0)) * 16;
1331 
1332     return wm;
1333 }
1334 
1335 static void vsc9953_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1336 {
1337     *inuse = (val & GENMASK(25, 13)) >> 13;
1338     *maxuse = val & GENMASK(12, 0);
1339 }
1340 
1341 static const struct ocelot_ops vsc9953_ops = {
1342     .reset          = vsc9953_reset,
1343     .wm_enc         = vsc9953_wm_enc,
1344     .wm_dec         = vsc9953_wm_dec,
1345     .wm_stat        = vsc9953_wm_stat,
1346     .port_to_netdev     = felix_port_to_netdev,
1347     .netdev_to_port     = felix_netdev_to_port,
1348 };
1349 
1350 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
1351 {
1352     struct felix *felix = ocelot_to_felix(ocelot);
1353     struct device *dev = ocelot->dev;
1354     struct mii_bus *bus;
1355     int port;
1356     int rc;
1357 
1358     felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1359                   sizeof(struct phylink_pcs *),
1360                   GFP_KERNEL);
1361     if (!felix->pcs) {
1362         dev_err(dev, "failed to allocate array for PCS PHYs\n");
1363         return -ENOMEM;
1364     }
1365 
1366     rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus",
1367                  ocelot->targets[GCB],
1368                  ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]);
1369 
1370     if (rc) {
1371         dev_err(dev, "failed to setup MDIO bus\n");
1372         return rc;
1373     }
1374 
1375     /* Needed in order to initialize the bus mutex lock */
1376     rc = devm_of_mdiobus_register(dev, bus, NULL);
1377     if (rc < 0) {
1378         dev_err(dev, "failed to register MDIO bus\n");
1379         return rc;
1380     }
1381 
1382     felix->imdio = bus;
1383 
1384     for (port = 0; port < felix->info->num_ports; port++) {
1385         struct ocelot_port *ocelot_port = ocelot->ports[port];
1386         struct phylink_pcs *phylink_pcs;
1387         struct mdio_device *mdio_device;
1388         int addr = port + 4;
1389 
1390         if (dsa_is_unused_port(felix->ds, port))
1391             continue;
1392 
1393         if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1394             continue;
1395 
1396         mdio_device = mdio_device_create(felix->imdio, addr);
1397         if (IS_ERR(mdio_device))
1398             continue;
1399 
1400         phylink_pcs = lynx_pcs_create(mdio_device);
1401         if (!phylink_pcs) {
1402             mdio_device_free(mdio_device);
1403             continue;
1404         }
1405 
1406         felix->pcs[port] = phylink_pcs;
1407 
1408         dev_info(dev, "Found PCS at internal MDIO address %d\n", addr);
1409     }
1410 
1411     return 0;
1412 }
1413 
1414 static void vsc9953_mdio_bus_free(struct ocelot *ocelot)
1415 {
1416     struct felix *felix = ocelot_to_felix(ocelot);
1417     int port;
1418 
1419     for (port = 0; port < ocelot->num_phys_ports; port++) {
1420         struct phylink_pcs *phylink_pcs = felix->pcs[port];
1421         struct mdio_device *mdio_device;
1422 
1423         if (!phylink_pcs)
1424             continue;
1425 
1426         mdio_device = lynx_get_mdio_device(phylink_pcs);
1427         mdio_device_free(mdio_device);
1428         lynx_pcs_destroy(phylink_pcs);
1429     }
1430 
1431     /* mdiobus_unregister and mdiobus_free handled by devres */
1432 }
1433 
1434 static const struct felix_info seville_info_vsc9953 = {
1435     .target_io_res      = vsc9953_target_io_res,
1436     .port_io_res        = vsc9953_port_io_res,
1437     .regfields      = vsc9953_regfields,
1438     .map            = vsc9953_regmap,
1439     .ops            = &vsc9953_ops,
1440     .stats_layout       = vsc9953_stats_layout,
1441     .vcap           = vsc9953_vcap_props,
1442     .vcap_pol_base      = VSC9953_VCAP_POLICER_BASE,
1443     .vcap_pol_max       = VSC9953_VCAP_POLICER_MAX,
1444     .vcap_pol_base2     = VSC9953_VCAP_POLICER_BASE2,
1445     .vcap_pol_max2      = VSC9953_VCAP_POLICER_MAX2,
1446     .num_mact_rows      = 2048,
1447     .num_ports      = VSC9953_NUM_PORTS,
1448     .num_tx_queues      = OCELOT_NUM_TC,
1449     .mdio_bus_alloc     = vsc9953_mdio_bus_alloc,
1450     .mdio_bus_free      = vsc9953_mdio_bus_free,
1451     .phylink_validate   = vsc9953_phylink_validate,
1452     .port_modes     = vsc9953_port_modes,
1453     .init_regmap        = ocelot_regmap_init,
1454 };
1455 
1456 static int seville_probe(struct platform_device *pdev)
1457 {
1458     struct dsa_switch *ds;
1459     struct ocelot *ocelot;
1460     struct resource *res;
1461     struct felix *felix;
1462     int err;
1463 
1464     felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1465     if (!felix) {
1466         err = -ENOMEM;
1467         dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1468         goto err_alloc_felix;
1469     }
1470 
1471     platform_set_drvdata(pdev, felix);
1472 
1473     ocelot = &felix->ocelot;
1474     ocelot->dev = &pdev->dev;
1475     ocelot->num_flooding_pgids = 1;
1476     felix->info = &seville_info_vsc9953;
1477 
1478     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479     if (!res) {
1480         err = -EINVAL;
1481         dev_err(&pdev->dev, "Invalid resource\n");
1482         goto err_alloc_felix;
1483     }
1484     felix->switch_base = res->start;
1485 
1486     ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1487     if (!ds) {
1488         err = -ENOMEM;
1489         dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1490         goto err_alloc_ds;
1491     }
1492 
1493     ds->dev = &pdev->dev;
1494     ds->num_ports = felix->info->num_ports;
1495     ds->ops = &felix_switch_ops;
1496     ds->priv = ocelot;
1497     felix->ds = ds;
1498     felix->tag_proto = DSA_TAG_PROTO_SEVILLE;
1499 
1500     err = dsa_register_switch(ds);
1501     if (err) {
1502         dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1503         goto err_register_ds;
1504     }
1505 
1506     return 0;
1507 
1508 err_register_ds:
1509     kfree(ds);
1510 err_alloc_ds:
1511 err_alloc_felix:
1512     kfree(felix);
1513     return err;
1514 }
1515 
1516 static int seville_remove(struct platform_device *pdev)
1517 {
1518     struct felix *felix = platform_get_drvdata(pdev);
1519 
1520     if (!felix)
1521         return 0;
1522 
1523     dsa_unregister_switch(felix->ds);
1524 
1525     kfree(felix->ds);
1526     kfree(felix);
1527 
1528     platform_set_drvdata(pdev, NULL);
1529 
1530     return 0;
1531 }
1532 
1533 static void seville_shutdown(struct platform_device *pdev)
1534 {
1535     struct felix *felix = platform_get_drvdata(pdev);
1536 
1537     if (!felix)
1538         return;
1539 
1540     dsa_switch_shutdown(felix->ds);
1541 
1542     platform_set_drvdata(pdev, NULL);
1543 }
1544 
1545 static const struct of_device_id seville_of_match[] = {
1546     { .compatible = "mscc,vsc9953-switch" },
1547     { },
1548 };
1549 MODULE_DEVICE_TABLE(of, seville_of_match);
1550 
1551 static struct platform_driver seville_vsc9953_driver = {
1552     .probe      = seville_probe,
1553     .remove     = seville_remove,
1554     .shutdown   = seville_shutdown,
1555     .driver = {
1556         .name       = "mscc_seville",
1557         .of_match_table = of_match_ptr(seville_of_match),
1558     },
1559 };
1560 module_platform_driver(seville_vsc9953_driver);
1561 
1562 MODULE_DESCRIPTION("Seville Switch driver");
1563 MODULE_LICENSE("GPL v2");
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