Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /* Copyright 2017 Microsemi Corporation
0003  * Copyright 2018-2019 NXP
0004  */
0005 #include <linux/fsl/enetc_mdio.h>
0006 #include <soc/mscc/ocelot_qsys.h>
0007 #include <soc/mscc/ocelot_vcap.h>
0008 #include <soc/mscc/ocelot_ana.h>
0009 #include <soc/mscc/ocelot_ptp.h>
0010 #include <soc/mscc/ocelot_sys.h>
0011 #include <net/tc_act/tc_gate.h>
0012 #include <soc/mscc/ocelot.h>
0013 #include <linux/dsa/ocelot.h>
0014 #include <linux/pcs-lynx.h>
0015 #include <net/pkt_sched.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/mdio.h>
0018 #include <linux/pci.h>
0019 #include <linux/time.h>
0020 #include "felix.h"
0021 
0022 #define VSC9959_NUM_PORTS       6
0023 
0024 #define VSC9959_TAS_GCL_ENTRY_MAX   63
0025 #define VSC9959_TAS_MIN_GATE_LEN_NS 33
0026 #define VSC9959_VCAP_POLICER_BASE   63
0027 #define VSC9959_VCAP_POLICER_MAX    383
0028 #define VSC9959_SWITCH_PCI_BAR      4
0029 #define VSC9959_IMDIO_PCI_BAR       0
0030 
0031 #define VSC9959_PORT_MODE_SERDES    (OCELOT_PORT_MODE_SGMII | \
0032                      OCELOT_PORT_MODE_QSGMII | \
0033                      OCELOT_PORT_MODE_1000BASEX | \
0034                      OCELOT_PORT_MODE_2500BASEX | \
0035                      OCELOT_PORT_MODE_USXGMII)
0036 
0037 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
0038     VSC9959_PORT_MODE_SERDES,
0039     VSC9959_PORT_MODE_SERDES,
0040     VSC9959_PORT_MODE_SERDES,
0041     VSC9959_PORT_MODE_SERDES,
0042     OCELOT_PORT_MODE_INTERNAL,
0043     OCELOT_PORT_MODE_INTERNAL,
0044 };
0045 
0046 static const u32 vsc9959_ana_regmap[] = {
0047     REG(ANA_ADVLEARN,           0x0089a0),
0048     REG(ANA_VLANMASK,           0x0089a4),
0049     REG_RESERVED(ANA_PORT_B_DOMAIN),
0050     REG(ANA_ANAGEFIL,           0x0089ac),
0051     REG(ANA_ANEVENTS,           0x0089b0),
0052     REG(ANA_STORMLIMIT_BURST,       0x0089b4),
0053     REG(ANA_STORMLIMIT_CFG,         0x0089b8),
0054     REG(ANA_ISOLATED_PORTS,         0x0089c8),
0055     REG(ANA_COMMUNITY_PORTS,        0x0089cc),
0056     REG(ANA_AUTOAGE,            0x0089d0),
0057     REG(ANA_MACTOPTIONS,            0x0089d4),
0058     REG(ANA_LEARNDISC,          0x0089d8),
0059     REG(ANA_AGENCTRL,           0x0089dc),
0060     REG(ANA_MIRRORPORTS,            0x0089e0),
0061     REG(ANA_EMIRRORPORTS,           0x0089e4),
0062     REG(ANA_FLOODING,           0x0089e8),
0063     REG(ANA_FLOODING_IPMC,          0x008a08),
0064     REG(ANA_SFLOW_CFG,          0x008a0c),
0065     REG(ANA_PORT_MODE,          0x008a28),
0066     REG(ANA_CUT_THRU_CFG,           0x008a48),
0067     REG(ANA_PGID_PGID,          0x008400),
0068     REG(ANA_TABLES_ANMOVED,         0x007f1c),
0069     REG(ANA_TABLES_MACHDATA,        0x007f20),
0070     REG(ANA_TABLES_MACLDATA,        0x007f24),
0071     REG(ANA_TABLES_STREAMDATA,      0x007f28),
0072     REG(ANA_TABLES_MACACCESS,       0x007f2c),
0073     REG(ANA_TABLES_MACTINDX,        0x007f30),
0074     REG(ANA_TABLES_VLANACCESS,      0x007f34),
0075     REG(ANA_TABLES_VLANTIDX,        0x007f38),
0076     REG(ANA_TABLES_ISDXACCESS,      0x007f3c),
0077     REG(ANA_TABLES_ISDXTIDX,        0x007f40),
0078     REG(ANA_TABLES_ENTRYLIM,        0x007f00),
0079     REG(ANA_TABLES_PTP_ID_HIGH,     0x007f44),
0080     REG(ANA_TABLES_PTP_ID_LOW,      0x007f48),
0081     REG(ANA_TABLES_STREAMACCESS,        0x007f4c),
0082     REG(ANA_TABLES_STREAMTIDX,      0x007f50),
0083     REG(ANA_TABLES_SEQ_HISTORY,     0x007f54),
0084     REG(ANA_TABLES_SEQ_MASK,        0x007f58),
0085     REG(ANA_TABLES_SFID_MASK,       0x007f5c),
0086     REG(ANA_TABLES_SFIDACCESS,      0x007f60),
0087     REG(ANA_TABLES_SFIDTIDX,        0x007f64),
0088     REG(ANA_MSTI_STATE,         0x008600),
0089     REG(ANA_OAM_UPM_LM_CNT,         0x008000),
0090     REG(ANA_SG_ACCESS_CTRL,         0x008a64),
0091     REG(ANA_SG_CONFIG_REG_1,        0x007fb0),
0092     REG(ANA_SG_CONFIG_REG_2,        0x007fb4),
0093     REG(ANA_SG_CONFIG_REG_3,        0x007fb8),
0094     REG(ANA_SG_CONFIG_REG_4,        0x007fbc),
0095     REG(ANA_SG_CONFIG_REG_5,        0x007fc0),
0096     REG(ANA_SG_GCL_GS_CONFIG,       0x007f80),
0097     REG(ANA_SG_GCL_TI_CONFIG,       0x007f90),
0098     REG(ANA_SG_STATUS_REG_1,        0x008980),
0099     REG(ANA_SG_STATUS_REG_2,        0x008984),
0100     REG(ANA_SG_STATUS_REG_3,        0x008988),
0101     REG(ANA_PORT_VLAN_CFG,          0x007800),
0102     REG(ANA_PORT_DROP_CFG,          0x007804),
0103     REG(ANA_PORT_QOS_CFG,           0x007808),
0104     REG(ANA_PORT_VCAP_CFG,          0x00780c),
0105     REG(ANA_PORT_VCAP_S1_KEY_CFG,       0x007810),
0106     REG(ANA_PORT_VCAP_S2_CFG,       0x00781c),
0107     REG(ANA_PORT_PCP_DEI_MAP,       0x007820),
0108     REG(ANA_PORT_CPU_FWD_CFG,       0x007860),
0109     REG(ANA_PORT_CPU_FWD_BPDU_CFG,      0x007864),
0110     REG(ANA_PORT_CPU_FWD_GARP_CFG,      0x007868),
0111     REG(ANA_PORT_CPU_FWD_CCM_CFG,       0x00786c),
0112     REG(ANA_PORT_PORT_CFG,          0x007870),
0113     REG(ANA_PORT_POL_CFG,           0x007874),
0114     REG(ANA_PORT_PTP_CFG,           0x007878),
0115     REG(ANA_PORT_PTP_DLY1_CFG,      0x00787c),
0116     REG(ANA_PORT_PTP_DLY2_CFG,      0x007880),
0117     REG(ANA_PORT_SFID_CFG,          0x007884),
0118     REG(ANA_PFC_PFC_CFG,            0x008800),
0119     REG_RESERVED(ANA_PFC_PFC_TIMER),
0120     REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
0121     REG_RESERVED(ANA_IPT_IPT),
0122     REG_RESERVED(ANA_PPT_PPT),
0123     REG_RESERVED(ANA_FID_MAP_FID_MAP),
0124     REG(ANA_AGGR_CFG,           0x008a68),
0125     REG(ANA_CPUQ_CFG,           0x008a6c),
0126     REG_RESERVED(ANA_CPUQ_CFG2),
0127     REG(ANA_CPUQ_8021_CFG,          0x008a74),
0128     REG(ANA_DSCP_CFG,           0x008ab4),
0129     REG(ANA_DSCP_REWR_CFG,          0x008bb4),
0130     REG(ANA_VCAP_RNG_TYPE_CFG,      0x008bf4),
0131     REG(ANA_VCAP_RNG_VAL_CFG,       0x008c14),
0132     REG_RESERVED(ANA_VRAP_CFG),
0133     REG_RESERVED(ANA_VRAP_HDR_DATA),
0134     REG_RESERVED(ANA_VRAP_HDR_MASK),
0135     REG(ANA_DISCARD_CFG,            0x008c40),
0136     REG(ANA_FID_CFG,            0x008c44),
0137     REG(ANA_POL_PIR_CFG,            0x004000),
0138     REG(ANA_POL_CIR_CFG,            0x004004),
0139     REG(ANA_POL_MODE_CFG,           0x004008),
0140     REG(ANA_POL_PIR_STATE,          0x00400c),
0141     REG(ANA_POL_CIR_STATE,          0x004010),
0142     REG_RESERVED(ANA_POL_STATE),
0143     REG(ANA_POL_FLOWC,          0x008c48),
0144     REG(ANA_POL_HYST,           0x008cb4),
0145     REG_RESERVED(ANA_POL_MISC_CFG),
0146 };
0147 
0148 static const u32 vsc9959_qs_regmap[] = {
0149     REG(QS_XTR_GRP_CFG,         0x000000),
0150     REG(QS_XTR_RD,              0x000008),
0151     REG(QS_XTR_FRM_PRUNING,         0x000010),
0152     REG(QS_XTR_FLUSH,           0x000018),
0153     REG(QS_XTR_DATA_PRESENT,        0x00001c),
0154     REG(QS_XTR_CFG,             0x000020),
0155     REG(QS_INJ_GRP_CFG,         0x000024),
0156     REG(QS_INJ_WR,              0x00002c),
0157     REG(QS_INJ_CTRL,            0x000034),
0158     REG(QS_INJ_STATUS,          0x00003c),
0159     REG(QS_INJ_ERR,             0x000040),
0160     REG_RESERVED(QS_INH_DBG),
0161 };
0162 
0163 static const u32 vsc9959_vcap_regmap[] = {
0164     /* VCAP_CORE_CFG */
0165     REG(VCAP_CORE_UPDATE_CTRL,      0x000000),
0166     REG(VCAP_CORE_MV_CFG,           0x000004),
0167     /* VCAP_CORE_CACHE */
0168     REG(VCAP_CACHE_ENTRY_DAT,       0x000008),
0169     REG(VCAP_CACHE_MASK_DAT,        0x000108),
0170     REG(VCAP_CACHE_ACTION_DAT,      0x000208),
0171     REG(VCAP_CACHE_CNT_DAT,         0x000308),
0172     REG(VCAP_CACHE_TG_DAT,          0x000388),
0173     /* VCAP_CONST */
0174     REG(VCAP_CONST_VCAP_VER,        0x000398),
0175     REG(VCAP_CONST_ENTRY_WIDTH,     0x00039c),
0176     REG(VCAP_CONST_ENTRY_CNT,       0x0003a0),
0177     REG(VCAP_CONST_ENTRY_SWCNT,     0x0003a4),
0178     REG(VCAP_CONST_ENTRY_TG_WIDTH,      0x0003a8),
0179     REG(VCAP_CONST_ACTION_DEF_CNT,      0x0003ac),
0180     REG(VCAP_CONST_ACTION_WIDTH,        0x0003b0),
0181     REG(VCAP_CONST_CNT_WIDTH,       0x0003b4),
0182     REG(VCAP_CONST_CORE_CNT,        0x0003b8),
0183     REG(VCAP_CONST_IF_CNT,          0x0003bc),
0184 };
0185 
0186 static const u32 vsc9959_qsys_regmap[] = {
0187     REG(QSYS_PORT_MODE,         0x00f460),
0188     REG(QSYS_SWITCH_PORT_MODE,      0x00f480),
0189     REG(QSYS_STAT_CNT_CFG,          0x00f49c),
0190     REG(QSYS_EEE_CFG,           0x00f4a0),
0191     REG(QSYS_EEE_THRES,         0x00f4b8),
0192     REG(QSYS_IGR_NO_SHARING,        0x00f4bc),
0193     REG(QSYS_EGR_NO_SHARING,        0x00f4c0),
0194     REG(QSYS_SW_STATUS,         0x00f4c4),
0195     REG(QSYS_EXT_CPU_CFG,           0x00f4e0),
0196     REG_RESERVED(QSYS_PAD_CFG),
0197     REG(QSYS_CPU_GROUP_MAP,         0x00f4e8),
0198     REG_RESERVED(QSYS_QMAP),
0199     REG_RESERVED(QSYS_ISDX_SGRP),
0200     REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
0201     REG(QSYS_TFRM_MISC,         0x00f50c),
0202     REG(QSYS_TFRM_PORT_DLY,         0x00f510),
0203     REG(QSYS_TFRM_TIMER_CFG_1,      0x00f514),
0204     REG(QSYS_TFRM_TIMER_CFG_2,      0x00f518),
0205     REG(QSYS_TFRM_TIMER_CFG_3,      0x00f51c),
0206     REG(QSYS_TFRM_TIMER_CFG_4,      0x00f520),
0207     REG(QSYS_TFRM_TIMER_CFG_5,      0x00f524),
0208     REG(QSYS_TFRM_TIMER_CFG_6,      0x00f528),
0209     REG(QSYS_TFRM_TIMER_CFG_7,      0x00f52c),
0210     REG(QSYS_TFRM_TIMER_CFG_8,      0x00f530),
0211     REG(QSYS_RED_PROFILE,           0x00f534),
0212     REG(QSYS_RES_QOS_MODE,          0x00f574),
0213     REG(QSYS_RES_CFG,           0x00c000),
0214     REG(QSYS_RES_STAT,          0x00c004),
0215     REG(QSYS_EGR_DROP_MODE,         0x00f578),
0216     REG(QSYS_EQ_CTRL,           0x00f57c),
0217     REG_RESERVED(QSYS_EVENTS_CORE),
0218     REG(QSYS_QMAXSDU_CFG_0,         0x00f584),
0219     REG(QSYS_QMAXSDU_CFG_1,         0x00f5a0),
0220     REG(QSYS_QMAXSDU_CFG_2,         0x00f5bc),
0221     REG(QSYS_QMAXSDU_CFG_3,         0x00f5d8),
0222     REG(QSYS_QMAXSDU_CFG_4,         0x00f5f4),
0223     REG(QSYS_QMAXSDU_CFG_5,         0x00f610),
0224     REG(QSYS_QMAXSDU_CFG_6,         0x00f62c),
0225     REG(QSYS_QMAXSDU_CFG_7,         0x00f648),
0226     REG(QSYS_PREEMPTION_CFG,        0x00f664),
0227     REG(QSYS_CIR_CFG,           0x000000),
0228     REG(QSYS_EIR_CFG,           0x000004),
0229     REG(QSYS_SE_CFG,            0x000008),
0230     REG(QSYS_SE_DWRR_CFG,           0x00000c),
0231     REG_RESERVED(QSYS_SE_CONNECT),
0232     REG(QSYS_SE_DLB_SENSE,          0x000040),
0233     REG(QSYS_CIR_STATE,         0x000044),
0234     REG(QSYS_EIR_STATE,         0x000048),
0235     REG_RESERVED(QSYS_SE_STATE),
0236     REG(QSYS_HSCH_MISC_CFG,         0x00f67c),
0237     REG(QSYS_TAG_CONFIG,            0x00f680),
0238     REG(QSYS_TAS_PARAM_CFG_CTRL,        0x00f698),
0239     REG(QSYS_PORT_MAX_SDU,          0x00f69c),
0240     REG(QSYS_PARAM_CFG_REG_1,       0x00f440),
0241     REG(QSYS_PARAM_CFG_REG_2,       0x00f444),
0242     REG(QSYS_PARAM_CFG_REG_3,       0x00f448),
0243     REG(QSYS_PARAM_CFG_REG_4,       0x00f44c),
0244     REG(QSYS_PARAM_CFG_REG_5,       0x00f450),
0245     REG(QSYS_GCL_CFG_REG_1,         0x00f454),
0246     REG(QSYS_GCL_CFG_REG_2,         0x00f458),
0247     REG(QSYS_PARAM_STATUS_REG_1,        0x00f400),
0248     REG(QSYS_PARAM_STATUS_REG_2,        0x00f404),
0249     REG(QSYS_PARAM_STATUS_REG_3,        0x00f408),
0250     REG(QSYS_PARAM_STATUS_REG_4,        0x00f40c),
0251     REG(QSYS_PARAM_STATUS_REG_5,        0x00f410),
0252     REG(QSYS_PARAM_STATUS_REG_6,        0x00f414),
0253     REG(QSYS_PARAM_STATUS_REG_7,        0x00f418),
0254     REG(QSYS_PARAM_STATUS_REG_8,        0x00f41c),
0255     REG(QSYS_PARAM_STATUS_REG_9,        0x00f420),
0256     REG(QSYS_GCL_STATUS_REG_1,      0x00f424),
0257     REG(QSYS_GCL_STATUS_REG_2,      0x00f428),
0258 };
0259 
0260 static const u32 vsc9959_rew_regmap[] = {
0261     REG(REW_PORT_VLAN_CFG,          0x000000),
0262     REG(REW_TAG_CFG,            0x000004),
0263     REG(REW_PORT_CFG,           0x000008),
0264     REG(REW_DSCP_CFG,           0x00000c),
0265     REG(REW_PCP_DEI_QOS_MAP_CFG,        0x000010),
0266     REG(REW_PTP_CFG,            0x000050),
0267     REG(REW_PTP_DLY1_CFG,           0x000054),
0268     REG(REW_RED_TAG_CFG,            0x000058),
0269     REG(REW_DSCP_REMAP_DP1_CFG,     0x000410),
0270     REG(REW_DSCP_REMAP_CFG,         0x000510),
0271     REG_RESERVED(REW_STAT_CFG),
0272     REG_RESERVED(REW_REW_STICKY),
0273     REG_RESERVED(REW_PPT),
0274 };
0275 
0276 static const u32 vsc9959_sys_regmap[] = {
0277     REG(SYS_COUNT_RX_OCTETS,        0x000000),
0278     REG(SYS_COUNT_RX_UNICAST,       0x000004),
0279     REG(SYS_COUNT_RX_MULTICAST,     0x000008),
0280     REG(SYS_COUNT_RX_BROADCAST,     0x00000c),
0281     REG(SYS_COUNT_RX_SHORTS,        0x000010),
0282     REG(SYS_COUNT_RX_FRAGMENTS,     0x000014),
0283     REG(SYS_COUNT_RX_JABBERS,       0x000018),
0284     REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,    0x00001c),
0285     REG(SYS_COUNT_RX_SYM_ERRS,      0x000020),
0286     REG(SYS_COUNT_RX_64,            0x000024),
0287     REG(SYS_COUNT_RX_65_127,        0x000028),
0288     REG(SYS_COUNT_RX_128_255,       0x00002c),
0289     REG(SYS_COUNT_RX_256_511,       0x000030),
0290     REG(SYS_COUNT_RX_512_1023,      0x000034),
0291     REG(SYS_COUNT_RX_1024_1526,     0x000038),
0292     REG(SYS_COUNT_RX_1527_MAX,      0x00003c),
0293     REG(SYS_COUNT_RX_PAUSE,         0x000040),
0294     REG(SYS_COUNT_RX_CONTROL,       0x000044),
0295     REG(SYS_COUNT_RX_LONGS,         0x000048),
0296     REG(SYS_COUNT_RX_CLASSIFIED_DROPS,  0x00004c),
0297     REG(SYS_COUNT_RX_RED_PRIO_0,        0x000050),
0298     REG(SYS_COUNT_RX_RED_PRIO_1,        0x000054),
0299     REG(SYS_COUNT_RX_RED_PRIO_2,        0x000058),
0300     REG(SYS_COUNT_RX_RED_PRIO_3,        0x00005c),
0301     REG(SYS_COUNT_RX_RED_PRIO_4,        0x000060),
0302     REG(SYS_COUNT_RX_RED_PRIO_5,        0x000064),
0303     REG(SYS_COUNT_RX_RED_PRIO_6,        0x000068),
0304     REG(SYS_COUNT_RX_RED_PRIO_7,        0x00006c),
0305     REG(SYS_COUNT_RX_YELLOW_PRIO_0,     0x000070),
0306     REG(SYS_COUNT_RX_YELLOW_PRIO_1,     0x000074),
0307     REG(SYS_COUNT_RX_YELLOW_PRIO_2,     0x000078),
0308     REG(SYS_COUNT_RX_YELLOW_PRIO_3,     0x00007c),
0309     REG(SYS_COUNT_RX_YELLOW_PRIO_4,     0x000080),
0310     REG(SYS_COUNT_RX_YELLOW_PRIO_5,     0x000084),
0311     REG(SYS_COUNT_RX_YELLOW_PRIO_6,     0x000088),
0312     REG(SYS_COUNT_RX_YELLOW_PRIO_7,     0x00008c),
0313     REG(SYS_COUNT_RX_GREEN_PRIO_0,      0x000090),
0314     REG(SYS_COUNT_RX_GREEN_PRIO_1,      0x000094),
0315     REG(SYS_COUNT_RX_GREEN_PRIO_2,      0x000098),
0316     REG(SYS_COUNT_RX_GREEN_PRIO_3,      0x00009c),
0317     REG(SYS_COUNT_RX_GREEN_PRIO_4,      0x0000a0),
0318     REG(SYS_COUNT_RX_GREEN_PRIO_5,      0x0000a4),
0319     REG(SYS_COUNT_RX_GREEN_PRIO_6,      0x0000a8),
0320     REG(SYS_COUNT_RX_GREEN_PRIO_7,      0x0000ac),
0321     REG(SYS_COUNT_TX_OCTETS,        0x000200),
0322     REG(SYS_COUNT_TX_UNICAST,       0x000204),
0323     REG(SYS_COUNT_TX_MULTICAST,     0x000208),
0324     REG(SYS_COUNT_TX_BROADCAST,     0x00020c),
0325     REG(SYS_COUNT_TX_COLLISION,     0x000210),
0326     REG(SYS_COUNT_TX_DROPS,         0x000214),
0327     REG(SYS_COUNT_TX_PAUSE,         0x000218),
0328     REG(SYS_COUNT_TX_64,            0x00021c),
0329     REG(SYS_COUNT_TX_65_127,        0x000220),
0330     REG(SYS_COUNT_TX_128_255,       0x000224),
0331     REG(SYS_COUNT_TX_256_511,       0x000228),
0332     REG(SYS_COUNT_TX_512_1023,      0x00022c),
0333     REG(SYS_COUNT_TX_1024_1526,     0x000230),
0334     REG(SYS_COUNT_TX_1527_MAX,      0x000234),
0335     REG(SYS_COUNT_TX_YELLOW_PRIO_0,     0x000238),
0336     REG(SYS_COUNT_TX_YELLOW_PRIO_1,     0x00023c),
0337     REG(SYS_COUNT_TX_YELLOW_PRIO_2,     0x000240),
0338     REG(SYS_COUNT_TX_YELLOW_PRIO_3,     0x000244),
0339     REG(SYS_COUNT_TX_YELLOW_PRIO_4,     0x000248),
0340     REG(SYS_COUNT_TX_YELLOW_PRIO_5,     0x00024c),
0341     REG(SYS_COUNT_TX_YELLOW_PRIO_6,     0x000250),
0342     REG(SYS_COUNT_TX_YELLOW_PRIO_7,     0x000254),
0343     REG(SYS_COUNT_TX_GREEN_PRIO_0,      0x000258),
0344     REG(SYS_COUNT_TX_GREEN_PRIO_1,      0x00025c),
0345     REG(SYS_COUNT_TX_GREEN_PRIO_2,      0x000260),
0346     REG(SYS_COUNT_TX_GREEN_PRIO_3,      0x000264),
0347     REG(SYS_COUNT_TX_GREEN_PRIO_4,      0x000268),
0348     REG(SYS_COUNT_TX_GREEN_PRIO_5,      0x00026c),
0349     REG(SYS_COUNT_TX_GREEN_PRIO_6,      0x000270),
0350     REG(SYS_COUNT_TX_GREEN_PRIO_7,      0x000274),
0351     REG(SYS_COUNT_TX_AGING,         0x000278),
0352     REG(SYS_COUNT_DROP_LOCAL,       0x000400),
0353     REG(SYS_COUNT_DROP_TAIL,        0x000404),
0354     REG(SYS_COUNT_DROP_YELLOW_PRIO_0,   0x000408),
0355     REG(SYS_COUNT_DROP_YELLOW_PRIO_1,   0x00040c),
0356     REG(SYS_COUNT_DROP_YELLOW_PRIO_2,   0x000410),
0357     REG(SYS_COUNT_DROP_YELLOW_PRIO_3,   0x000414),
0358     REG(SYS_COUNT_DROP_YELLOW_PRIO_4,   0x000418),
0359     REG(SYS_COUNT_DROP_YELLOW_PRIO_5,   0x00041c),
0360     REG(SYS_COUNT_DROP_YELLOW_PRIO_6,   0x000420),
0361     REG(SYS_COUNT_DROP_YELLOW_PRIO_7,   0x000424),
0362     REG(SYS_COUNT_DROP_GREEN_PRIO_0,    0x000428),
0363     REG(SYS_COUNT_DROP_GREEN_PRIO_1,    0x00042c),
0364     REG(SYS_COUNT_DROP_GREEN_PRIO_2,    0x000430),
0365     REG(SYS_COUNT_DROP_GREEN_PRIO_3,    0x000434),
0366     REG(SYS_COUNT_DROP_GREEN_PRIO_4,    0x000438),
0367     REG(SYS_COUNT_DROP_GREEN_PRIO_5,    0x00043c),
0368     REG(SYS_COUNT_DROP_GREEN_PRIO_6,    0x000440),
0369     REG(SYS_COUNT_DROP_GREEN_PRIO_7,    0x000444),
0370     REG(SYS_RESET_CFG,          0x000e00),
0371     REG(SYS_SR_ETYPE_CFG,           0x000e04),
0372     REG(SYS_VLAN_ETYPE_CFG,         0x000e08),
0373     REG(SYS_PORT_MODE,          0x000e0c),
0374     REG(SYS_FRONT_PORT_MODE,        0x000e2c),
0375     REG(SYS_FRM_AGING,          0x000e44),
0376     REG(SYS_STAT_CFG,           0x000e48),
0377     REG(SYS_SW_STATUS,          0x000e4c),
0378     REG_RESERVED(SYS_MISC_CFG),
0379     REG(SYS_REW_MAC_HIGH_CFG,       0x000e6c),
0380     REG(SYS_REW_MAC_LOW_CFG,        0x000e84),
0381     REG(SYS_TIMESTAMP_OFFSET,       0x000e9c),
0382     REG(SYS_PAUSE_CFG,          0x000ea0),
0383     REG(SYS_PAUSE_TOT_CFG,          0x000ebc),
0384     REG(SYS_ATOP,               0x000ec0),
0385     REG(SYS_ATOP_TOT_CFG,           0x000edc),
0386     REG(SYS_MAC_FC_CFG,         0x000ee0),
0387     REG(SYS_MMGT,               0x000ef8),
0388     REG_RESERVED(SYS_MMGT_FAST),
0389     REG_RESERVED(SYS_EVENTS_DIF),
0390     REG_RESERVED(SYS_EVENTS_CORE),
0391     REG(SYS_CNT,                0x000000),
0392     REG(SYS_PTP_STATUS,         0x000f14),
0393     REG(SYS_PTP_TXSTAMP,            0x000f18),
0394     REG(SYS_PTP_NXT,            0x000f1c),
0395     REG(SYS_PTP_CFG,            0x000f20),
0396     REG(SYS_RAM_INIT,           0x000f24),
0397     REG_RESERVED(SYS_CM_ADDR),
0398     REG_RESERVED(SYS_CM_DATA_WR),
0399     REG_RESERVED(SYS_CM_DATA_RD),
0400     REG_RESERVED(SYS_CM_OP),
0401     REG_RESERVED(SYS_CM_DATA),
0402 };
0403 
0404 static const u32 vsc9959_ptp_regmap[] = {
0405     REG(PTP_PIN_CFG,            0x000000),
0406     REG(PTP_PIN_TOD_SEC_MSB,        0x000004),
0407     REG(PTP_PIN_TOD_SEC_LSB,        0x000008),
0408     REG(PTP_PIN_TOD_NSEC,           0x00000c),
0409     REG(PTP_PIN_WF_HIGH_PERIOD,     0x000014),
0410     REG(PTP_PIN_WF_LOW_PERIOD,      0x000018),
0411     REG(PTP_CFG_MISC,           0x0000a0),
0412     REG(PTP_CLK_CFG_ADJ_CFG,        0x0000a4),
0413     REG(PTP_CLK_CFG_ADJ_FREQ,       0x0000a8),
0414 };
0415 
0416 static const u32 vsc9959_gcb_regmap[] = {
0417     REG(GCB_SOFT_RST,           0x000004),
0418 };
0419 
0420 static const u32 vsc9959_dev_gmii_regmap[] = {
0421     REG(DEV_CLOCK_CFG,          0x0),
0422     REG(DEV_PORT_MISC,          0x4),
0423     REG(DEV_EVENTS,             0x8),
0424     REG(DEV_EEE_CFG,            0xc),
0425     REG(DEV_RX_PATH_DELAY,          0x10),
0426     REG(DEV_TX_PATH_DELAY,          0x14),
0427     REG(DEV_PTP_PREDICT_CFG,        0x18),
0428     REG(DEV_MAC_ENA_CFG,            0x1c),
0429     REG(DEV_MAC_MODE_CFG,           0x20),
0430     REG(DEV_MAC_MAXLEN_CFG,         0x24),
0431     REG(DEV_MAC_TAGS_CFG,           0x28),
0432     REG(DEV_MAC_ADV_CHK_CFG,        0x2c),
0433     REG(DEV_MAC_IFG_CFG,            0x30),
0434     REG(DEV_MAC_HDX_CFG,            0x34),
0435     REG(DEV_MAC_DBG_CFG,            0x38),
0436     REG(DEV_MAC_FC_MAC_LOW_CFG,     0x3c),
0437     REG(DEV_MAC_FC_MAC_HIGH_CFG,        0x40),
0438     REG(DEV_MAC_STICKY,         0x44),
0439     REG_RESERVED(PCS1G_CFG),
0440     REG_RESERVED(PCS1G_MODE_CFG),
0441     REG_RESERVED(PCS1G_SD_CFG),
0442     REG_RESERVED(PCS1G_ANEG_CFG),
0443     REG_RESERVED(PCS1G_ANEG_NP_CFG),
0444     REG_RESERVED(PCS1G_LB_CFG),
0445     REG_RESERVED(PCS1G_DBG_CFG),
0446     REG_RESERVED(PCS1G_CDET_CFG),
0447     REG_RESERVED(PCS1G_ANEG_STATUS),
0448     REG_RESERVED(PCS1G_ANEG_NP_STATUS),
0449     REG_RESERVED(PCS1G_LINK_STATUS),
0450     REG_RESERVED(PCS1G_LINK_DOWN_CNT),
0451     REG_RESERVED(PCS1G_STICKY),
0452     REG_RESERVED(PCS1G_DEBUG_STATUS),
0453     REG_RESERVED(PCS1G_LPI_CFG),
0454     REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
0455     REG_RESERVED(PCS1G_LPI_STATUS),
0456     REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
0457     REG_RESERVED(PCS1G_TSTPAT_STATUS),
0458     REG_RESERVED(DEV_PCS_FX100_CFG),
0459     REG_RESERVED(DEV_PCS_FX100_STATUS),
0460 };
0461 
0462 static const u32 *vsc9959_regmap[TARGET_MAX] = {
0463     [ANA]   = vsc9959_ana_regmap,
0464     [QS]    = vsc9959_qs_regmap,
0465     [QSYS]  = vsc9959_qsys_regmap,
0466     [REW]   = vsc9959_rew_regmap,
0467     [SYS]   = vsc9959_sys_regmap,
0468     [S0]    = vsc9959_vcap_regmap,
0469     [S1]    = vsc9959_vcap_regmap,
0470     [S2]    = vsc9959_vcap_regmap,
0471     [PTP]   = vsc9959_ptp_regmap,
0472     [GCB]   = vsc9959_gcb_regmap,
0473     [DEV_GMII] = vsc9959_dev_gmii_regmap,
0474 };
0475 
0476 /* Addresses are relative to the PCI device's base address */
0477 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
0478     [ANA] = {
0479         .start  = 0x0280000,
0480         .end    = 0x028ffff,
0481         .name   = "ana",
0482     },
0483     [QS] = {
0484         .start  = 0x0080000,
0485         .end    = 0x00800ff,
0486         .name   = "qs",
0487     },
0488     [QSYS] = {
0489         .start  = 0x0200000,
0490         .end    = 0x021ffff,
0491         .name   = "qsys",
0492     },
0493     [REW] = {
0494         .start  = 0x0030000,
0495         .end    = 0x003ffff,
0496         .name   = "rew",
0497     },
0498     [SYS] = {
0499         .start  = 0x0010000,
0500         .end    = 0x001ffff,
0501         .name   = "sys",
0502     },
0503     [S0] = {
0504         .start  = 0x0040000,
0505         .end    = 0x00403ff,
0506         .name   = "s0",
0507     },
0508     [S1] = {
0509         .start  = 0x0050000,
0510         .end    = 0x00503ff,
0511         .name   = "s1",
0512     },
0513     [S2] = {
0514         .start  = 0x0060000,
0515         .end    = 0x00603ff,
0516         .name   = "s2",
0517     },
0518     [PTP] = {
0519         .start  = 0x0090000,
0520         .end    = 0x00900cb,
0521         .name   = "ptp",
0522     },
0523     [GCB] = {
0524         .start  = 0x0070000,
0525         .end    = 0x00701ff,
0526         .name   = "devcpu_gcb",
0527     },
0528 };
0529 
0530 static const struct resource vsc9959_port_io_res[] = {
0531     {
0532         .start  = 0x0100000,
0533         .end    = 0x010ffff,
0534         .name   = "port0",
0535     },
0536     {
0537         .start  = 0x0110000,
0538         .end    = 0x011ffff,
0539         .name   = "port1",
0540     },
0541     {
0542         .start  = 0x0120000,
0543         .end    = 0x012ffff,
0544         .name   = "port2",
0545     },
0546     {
0547         .start  = 0x0130000,
0548         .end    = 0x013ffff,
0549         .name   = "port3",
0550     },
0551     {
0552         .start  = 0x0140000,
0553         .end    = 0x014ffff,
0554         .name   = "port4",
0555     },
0556     {
0557         .start  = 0x0150000,
0558         .end    = 0x015ffff,
0559         .name   = "port5",
0560     },
0561 };
0562 
0563 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
0564  * SGMII/QSGMII MAC PCS can be found.
0565  */
0566 static const struct resource vsc9959_imdio_res = {
0567     .start      = 0x8030,
0568     .end        = 0x8040,
0569     .name       = "imdio",
0570 };
0571 
0572 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
0573     [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
0574     [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
0575     [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
0576     [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
0577     [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
0578     [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
0579     [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
0580     [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
0581     [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
0582     [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
0583     [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
0584     [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
0585     [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
0586     [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
0587     [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
0588     [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
0589     [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
0590     [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
0591     [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
0592     [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
0593     [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
0594     [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
0595     [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
0596     [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
0597     [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
0598     [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
0599     [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
0600     [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
0601     [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
0602     [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
0603     [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
0604     [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
0605     [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
0606     /* Replicated per number of ports (7), register size 4 per port */
0607     [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
0608     [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
0609     [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
0610     [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
0611     [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
0612     [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
0613     [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
0614     [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
0615     [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
0616     [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
0617     [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
0618     [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
0619     [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
0620 };
0621 
0622 static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = {
0623     [OCELOT_STAT_RX_OCTETS] = {
0624         .name = "rx_octets",
0625         .reg = SYS_COUNT_RX_OCTETS,
0626     },
0627     [OCELOT_STAT_RX_UNICAST] = {
0628         .name = "rx_unicast",
0629         .reg = SYS_COUNT_RX_UNICAST,
0630     },
0631     [OCELOT_STAT_RX_MULTICAST] = {
0632         .name = "rx_multicast",
0633         .reg = SYS_COUNT_RX_MULTICAST,
0634     },
0635     [OCELOT_STAT_RX_BROADCAST] = {
0636         .name = "rx_broadcast",
0637         .reg = SYS_COUNT_RX_BROADCAST,
0638     },
0639     [OCELOT_STAT_RX_SHORTS] = {
0640         .name = "rx_shorts",
0641         .reg = SYS_COUNT_RX_SHORTS,
0642     },
0643     [OCELOT_STAT_RX_FRAGMENTS] = {
0644         .name = "rx_fragments",
0645         .reg = SYS_COUNT_RX_FRAGMENTS,
0646     },
0647     [OCELOT_STAT_RX_JABBERS] = {
0648         .name = "rx_jabbers",
0649         .reg = SYS_COUNT_RX_JABBERS,
0650     },
0651     [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = {
0652         .name = "rx_crc_align_errs",
0653         .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS,
0654     },
0655     [OCELOT_STAT_RX_SYM_ERRS] = {
0656         .name = "rx_sym_errs",
0657         .reg = SYS_COUNT_RX_SYM_ERRS,
0658     },
0659     [OCELOT_STAT_RX_64] = {
0660         .name = "rx_frames_below_65_octets",
0661         .reg = SYS_COUNT_RX_64,
0662     },
0663     [OCELOT_STAT_RX_65_127] = {
0664         .name = "rx_frames_65_to_127_octets",
0665         .reg = SYS_COUNT_RX_65_127,
0666     },
0667     [OCELOT_STAT_RX_128_255] = {
0668         .name = "rx_frames_128_to_255_octets",
0669         .reg = SYS_COUNT_RX_128_255,
0670     },
0671     [OCELOT_STAT_RX_256_511] = {
0672         .name = "rx_frames_256_to_511_octets",
0673         .reg = SYS_COUNT_RX_256_511,
0674     },
0675     [OCELOT_STAT_RX_512_1023] = {
0676         .name = "rx_frames_512_to_1023_octets",
0677         .reg = SYS_COUNT_RX_512_1023,
0678     },
0679     [OCELOT_STAT_RX_1024_1526] = {
0680         .name = "rx_frames_1024_to_1526_octets",
0681         .reg = SYS_COUNT_RX_1024_1526,
0682     },
0683     [OCELOT_STAT_RX_1527_MAX] = {
0684         .name = "rx_frames_over_1526_octets",
0685         .reg = SYS_COUNT_RX_1527_MAX,
0686     },
0687     [OCELOT_STAT_RX_PAUSE] = {
0688         .name = "rx_pause",
0689         .reg = SYS_COUNT_RX_PAUSE,
0690     },
0691     [OCELOT_STAT_RX_CONTROL] = {
0692         .name = "rx_control",
0693         .reg = SYS_COUNT_RX_CONTROL,
0694     },
0695     [OCELOT_STAT_RX_LONGS] = {
0696         .name = "rx_longs",
0697         .reg = SYS_COUNT_RX_LONGS,
0698     },
0699     [OCELOT_STAT_RX_CLASSIFIED_DROPS] = {
0700         .name = "rx_classified_drops",
0701         .reg = SYS_COUNT_RX_CLASSIFIED_DROPS,
0702     },
0703     [OCELOT_STAT_RX_RED_PRIO_0] = {
0704         .name = "rx_red_prio_0",
0705         .reg = SYS_COUNT_RX_RED_PRIO_0,
0706     },
0707     [OCELOT_STAT_RX_RED_PRIO_1] = {
0708         .name = "rx_red_prio_1",
0709         .reg = SYS_COUNT_RX_RED_PRIO_1,
0710     },
0711     [OCELOT_STAT_RX_RED_PRIO_2] = {
0712         .name = "rx_red_prio_2",
0713         .reg = SYS_COUNT_RX_RED_PRIO_2,
0714     },
0715     [OCELOT_STAT_RX_RED_PRIO_3] = {
0716         .name = "rx_red_prio_3",
0717         .reg = SYS_COUNT_RX_RED_PRIO_3,
0718     },
0719     [OCELOT_STAT_RX_RED_PRIO_4] = {
0720         .name = "rx_red_prio_4",
0721         .reg = SYS_COUNT_RX_RED_PRIO_4,
0722     },
0723     [OCELOT_STAT_RX_RED_PRIO_5] = {
0724         .name = "rx_red_prio_5",
0725         .reg = SYS_COUNT_RX_RED_PRIO_5,
0726     },
0727     [OCELOT_STAT_RX_RED_PRIO_6] = {
0728         .name = "rx_red_prio_6",
0729         .reg = SYS_COUNT_RX_RED_PRIO_6,
0730     },
0731     [OCELOT_STAT_RX_RED_PRIO_7] = {
0732         .name = "rx_red_prio_7",
0733         .reg = SYS_COUNT_RX_RED_PRIO_7,
0734     },
0735     [OCELOT_STAT_RX_YELLOW_PRIO_0] = {
0736         .name = "rx_yellow_prio_0",
0737         .reg = SYS_COUNT_RX_YELLOW_PRIO_0,
0738     },
0739     [OCELOT_STAT_RX_YELLOW_PRIO_1] = {
0740         .name = "rx_yellow_prio_1",
0741         .reg = SYS_COUNT_RX_YELLOW_PRIO_1,
0742     },
0743     [OCELOT_STAT_RX_YELLOW_PRIO_2] = {
0744         .name = "rx_yellow_prio_2",
0745         .reg = SYS_COUNT_RX_YELLOW_PRIO_2,
0746     },
0747     [OCELOT_STAT_RX_YELLOW_PRIO_3] = {
0748         .name = "rx_yellow_prio_3",
0749         .reg = SYS_COUNT_RX_YELLOW_PRIO_3,
0750     },
0751     [OCELOT_STAT_RX_YELLOW_PRIO_4] = {
0752         .name = "rx_yellow_prio_4",
0753         .reg = SYS_COUNT_RX_YELLOW_PRIO_4,
0754     },
0755     [OCELOT_STAT_RX_YELLOW_PRIO_5] = {
0756         .name = "rx_yellow_prio_5",
0757         .reg = SYS_COUNT_RX_YELLOW_PRIO_5,
0758     },
0759     [OCELOT_STAT_RX_YELLOW_PRIO_6] = {
0760         .name = "rx_yellow_prio_6",
0761         .reg = SYS_COUNT_RX_YELLOW_PRIO_6,
0762     },
0763     [OCELOT_STAT_RX_YELLOW_PRIO_7] = {
0764         .name = "rx_yellow_prio_7",
0765         .reg = SYS_COUNT_RX_YELLOW_PRIO_7,
0766     },
0767     [OCELOT_STAT_RX_GREEN_PRIO_0] = {
0768         .name = "rx_green_prio_0",
0769         .reg = SYS_COUNT_RX_GREEN_PRIO_0,
0770     },
0771     [OCELOT_STAT_RX_GREEN_PRIO_1] = {
0772         .name = "rx_green_prio_1",
0773         .reg = SYS_COUNT_RX_GREEN_PRIO_1,
0774     },
0775     [OCELOT_STAT_RX_GREEN_PRIO_2] = {
0776         .name = "rx_green_prio_2",
0777         .reg = SYS_COUNT_RX_GREEN_PRIO_2,
0778     },
0779     [OCELOT_STAT_RX_GREEN_PRIO_3] = {
0780         .name = "rx_green_prio_3",
0781         .reg = SYS_COUNT_RX_GREEN_PRIO_3,
0782     },
0783     [OCELOT_STAT_RX_GREEN_PRIO_4] = {
0784         .name = "rx_green_prio_4",
0785         .reg = SYS_COUNT_RX_GREEN_PRIO_4,
0786     },
0787     [OCELOT_STAT_RX_GREEN_PRIO_5] = {
0788         .name = "rx_green_prio_5",
0789         .reg = SYS_COUNT_RX_GREEN_PRIO_5,
0790     },
0791     [OCELOT_STAT_RX_GREEN_PRIO_6] = {
0792         .name = "rx_green_prio_6",
0793         .reg = SYS_COUNT_RX_GREEN_PRIO_6,
0794     },
0795     [OCELOT_STAT_RX_GREEN_PRIO_7] = {
0796         .name = "rx_green_prio_7",
0797         .reg = SYS_COUNT_RX_GREEN_PRIO_7,
0798     },
0799     [OCELOT_STAT_TX_OCTETS] = {
0800         .name = "tx_octets",
0801         .reg = SYS_COUNT_TX_OCTETS,
0802     },
0803     [OCELOT_STAT_TX_UNICAST] = {
0804         .name = "tx_unicast",
0805         .reg = SYS_COUNT_TX_UNICAST,
0806     },
0807     [OCELOT_STAT_TX_MULTICAST] = {
0808         .name = "tx_multicast",
0809         .reg = SYS_COUNT_TX_MULTICAST,
0810     },
0811     [OCELOT_STAT_TX_BROADCAST] = {
0812         .name = "tx_broadcast",
0813         .reg = SYS_COUNT_TX_BROADCAST,
0814     },
0815     [OCELOT_STAT_TX_COLLISION] = {
0816         .name = "tx_collision",
0817         .reg = SYS_COUNT_TX_COLLISION,
0818     },
0819     [OCELOT_STAT_TX_DROPS] = {
0820         .name = "tx_drops",
0821         .reg = SYS_COUNT_TX_DROPS,
0822     },
0823     [OCELOT_STAT_TX_PAUSE] = {
0824         .name = "tx_pause",
0825         .reg = SYS_COUNT_TX_PAUSE,
0826     },
0827     [OCELOT_STAT_TX_64] = {
0828         .name = "tx_frames_below_65_octets",
0829         .reg = SYS_COUNT_TX_64,
0830     },
0831     [OCELOT_STAT_TX_65_127] = {
0832         .name = "tx_frames_65_to_127_octets",
0833         .reg = SYS_COUNT_TX_65_127,
0834     },
0835     [OCELOT_STAT_TX_128_255] = {
0836         .name = "tx_frames_128_255_octets",
0837         .reg = SYS_COUNT_TX_128_255,
0838     },
0839     [OCELOT_STAT_TX_256_511] = {
0840         .name = "tx_frames_256_511_octets",
0841         .reg = SYS_COUNT_TX_256_511,
0842     },
0843     [OCELOT_STAT_TX_512_1023] = {
0844         .name = "tx_frames_512_1023_octets",
0845         .reg = SYS_COUNT_TX_512_1023,
0846     },
0847     [OCELOT_STAT_TX_1024_1526] = {
0848         .name = "tx_frames_1024_1526_octets",
0849         .reg = SYS_COUNT_TX_1024_1526,
0850     },
0851     [OCELOT_STAT_TX_1527_MAX] = {
0852         .name = "tx_frames_over_1526_octets",
0853         .reg = SYS_COUNT_TX_1527_MAX,
0854     },
0855     [OCELOT_STAT_TX_YELLOW_PRIO_0] = {
0856         .name = "tx_yellow_prio_0",
0857         .reg = SYS_COUNT_TX_YELLOW_PRIO_0,
0858     },
0859     [OCELOT_STAT_TX_YELLOW_PRIO_1] = {
0860         .name = "tx_yellow_prio_1",
0861         .reg = SYS_COUNT_TX_YELLOW_PRIO_1,
0862     },
0863     [OCELOT_STAT_TX_YELLOW_PRIO_2] = {
0864         .name = "tx_yellow_prio_2",
0865         .reg = SYS_COUNT_TX_YELLOW_PRIO_2,
0866     },
0867     [OCELOT_STAT_TX_YELLOW_PRIO_3] = {
0868         .name = "tx_yellow_prio_3",
0869         .reg = SYS_COUNT_TX_YELLOW_PRIO_3,
0870     },
0871     [OCELOT_STAT_TX_YELLOW_PRIO_4] = {
0872         .name = "tx_yellow_prio_4",
0873         .reg = SYS_COUNT_TX_YELLOW_PRIO_4,
0874     },
0875     [OCELOT_STAT_TX_YELLOW_PRIO_5] = {
0876         .name = "tx_yellow_prio_5",
0877         .reg = SYS_COUNT_TX_YELLOW_PRIO_5,
0878     },
0879     [OCELOT_STAT_TX_YELLOW_PRIO_6] = {
0880         .name = "tx_yellow_prio_6",
0881         .reg = SYS_COUNT_TX_YELLOW_PRIO_6,
0882     },
0883     [OCELOT_STAT_TX_YELLOW_PRIO_7] = {
0884         .name = "tx_yellow_prio_7",
0885         .reg = SYS_COUNT_TX_YELLOW_PRIO_7,
0886     },
0887     [OCELOT_STAT_TX_GREEN_PRIO_0] = {
0888         .name = "tx_green_prio_0",
0889         .reg = SYS_COUNT_TX_GREEN_PRIO_0,
0890     },
0891     [OCELOT_STAT_TX_GREEN_PRIO_1] = {
0892         .name = "tx_green_prio_1",
0893         .reg = SYS_COUNT_TX_GREEN_PRIO_1,
0894     },
0895     [OCELOT_STAT_TX_GREEN_PRIO_2] = {
0896         .name = "tx_green_prio_2",
0897         .reg = SYS_COUNT_TX_GREEN_PRIO_2,
0898     },
0899     [OCELOT_STAT_TX_GREEN_PRIO_3] = {
0900         .name = "tx_green_prio_3",
0901         .reg = SYS_COUNT_TX_GREEN_PRIO_3,
0902     },
0903     [OCELOT_STAT_TX_GREEN_PRIO_4] = {
0904         .name = "tx_green_prio_4",
0905         .reg = SYS_COUNT_TX_GREEN_PRIO_4,
0906     },
0907     [OCELOT_STAT_TX_GREEN_PRIO_5] = {
0908         .name = "tx_green_prio_5",
0909         .reg = SYS_COUNT_TX_GREEN_PRIO_5,
0910     },
0911     [OCELOT_STAT_TX_GREEN_PRIO_6] = {
0912         .name = "tx_green_prio_6",
0913         .reg = SYS_COUNT_TX_GREEN_PRIO_6,
0914     },
0915     [OCELOT_STAT_TX_GREEN_PRIO_7] = {
0916         .name = "tx_green_prio_7",
0917         .reg = SYS_COUNT_TX_GREEN_PRIO_7,
0918     },
0919     [OCELOT_STAT_TX_AGED] = {
0920         .name = "tx_aged",
0921         .reg = SYS_COUNT_TX_AGING,
0922     },
0923     [OCELOT_STAT_DROP_LOCAL] = {
0924         .name = "drop_local",
0925         .reg = SYS_COUNT_DROP_LOCAL,
0926     },
0927     [OCELOT_STAT_DROP_TAIL] = {
0928         .name = "drop_tail",
0929         .reg = SYS_COUNT_DROP_TAIL,
0930     },
0931     [OCELOT_STAT_DROP_YELLOW_PRIO_0] = {
0932         .name = "drop_yellow_prio_0",
0933         .reg = SYS_COUNT_DROP_YELLOW_PRIO_0,
0934     },
0935     [OCELOT_STAT_DROP_YELLOW_PRIO_1] = {
0936         .name = "drop_yellow_prio_1",
0937         .reg = SYS_COUNT_DROP_YELLOW_PRIO_1,
0938     },
0939     [OCELOT_STAT_DROP_YELLOW_PRIO_2] = {
0940         .name = "drop_yellow_prio_2",
0941         .reg = SYS_COUNT_DROP_YELLOW_PRIO_2,
0942     },
0943     [OCELOT_STAT_DROP_YELLOW_PRIO_3] = {
0944         .name = "drop_yellow_prio_3",
0945         .reg = SYS_COUNT_DROP_YELLOW_PRIO_3,
0946     },
0947     [OCELOT_STAT_DROP_YELLOW_PRIO_4] = {
0948         .name = "drop_yellow_prio_4",
0949         .reg = SYS_COUNT_DROP_YELLOW_PRIO_4,
0950     },
0951     [OCELOT_STAT_DROP_YELLOW_PRIO_5] = {
0952         .name = "drop_yellow_prio_5",
0953         .reg = SYS_COUNT_DROP_YELLOW_PRIO_5,
0954     },
0955     [OCELOT_STAT_DROP_YELLOW_PRIO_6] = {
0956         .name = "drop_yellow_prio_6",
0957         .reg = SYS_COUNT_DROP_YELLOW_PRIO_6,
0958     },
0959     [OCELOT_STAT_DROP_YELLOW_PRIO_7] = {
0960         .name = "drop_yellow_prio_7",
0961         .reg = SYS_COUNT_DROP_YELLOW_PRIO_7,
0962     },
0963     [OCELOT_STAT_DROP_GREEN_PRIO_0] = {
0964         .name = "drop_green_prio_0",
0965         .reg = SYS_COUNT_DROP_GREEN_PRIO_0,
0966     },
0967     [OCELOT_STAT_DROP_GREEN_PRIO_1] = {
0968         .name = "drop_green_prio_1",
0969         .reg = SYS_COUNT_DROP_GREEN_PRIO_1,
0970     },
0971     [OCELOT_STAT_DROP_GREEN_PRIO_2] = {
0972         .name = "drop_green_prio_2",
0973         .reg = SYS_COUNT_DROP_GREEN_PRIO_2,
0974     },
0975     [OCELOT_STAT_DROP_GREEN_PRIO_3] = {
0976         .name = "drop_green_prio_3",
0977         .reg = SYS_COUNT_DROP_GREEN_PRIO_3,
0978     },
0979     [OCELOT_STAT_DROP_GREEN_PRIO_4] = {
0980         .name = "drop_green_prio_4",
0981         .reg = SYS_COUNT_DROP_GREEN_PRIO_4,
0982     },
0983     [OCELOT_STAT_DROP_GREEN_PRIO_5] = {
0984         .name = "drop_green_prio_5",
0985         .reg = SYS_COUNT_DROP_GREEN_PRIO_5,
0986     },
0987     [OCELOT_STAT_DROP_GREEN_PRIO_6] = {
0988         .name = "drop_green_prio_6",
0989         .reg = SYS_COUNT_DROP_GREEN_PRIO_6,
0990     },
0991     [OCELOT_STAT_DROP_GREEN_PRIO_7] = {
0992         .name = "drop_green_prio_7",
0993         .reg = SYS_COUNT_DROP_GREEN_PRIO_7,
0994     },
0995 };
0996 
0997 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
0998     [VCAP_ES0_EGR_PORT]         = {  0,  3},
0999     [VCAP_ES0_IGR_PORT]         = {  3,  3},
1000     [VCAP_ES0_RSV]              = {  6,  2},
1001     [VCAP_ES0_L2_MC]            = {  8,  1},
1002     [VCAP_ES0_L2_BC]            = {  9,  1},
1003     [VCAP_ES0_VID]              = { 10, 12},
1004     [VCAP_ES0_DP]               = { 22,  1},
1005     [VCAP_ES0_PCP]              = { 23,  3},
1006 };
1007 
1008 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
1009     [VCAP_ES0_ACT_PUSH_OUTER_TAG]       = {  0,  2},
1010     [VCAP_ES0_ACT_PUSH_INNER_TAG]       = {  2,  1},
1011     [VCAP_ES0_ACT_TAG_A_TPID_SEL]       = {  3,  2},
1012     [VCAP_ES0_ACT_TAG_A_VID_SEL]        = {  5,  1},
1013     [VCAP_ES0_ACT_TAG_A_PCP_SEL]        = {  6,  2},
1014     [VCAP_ES0_ACT_TAG_A_DEI_SEL]        = {  8,  2},
1015     [VCAP_ES0_ACT_TAG_B_TPID_SEL]       = { 10,  2},
1016     [VCAP_ES0_ACT_TAG_B_VID_SEL]        = { 12,  1},
1017     [VCAP_ES0_ACT_TAG_B_PCP_SEL]        = { 13,  2},
1018     [VCAP_ES0_ACT_TAG_B_DEI_SEL]        = { 15,  2},
1019     [VCAP_ES0_ACT_VID_A_VAL]        = { 17, 12},
1020     [VCAP_ES0_ACT_PCP_A_VAL]        = { 29,  3},
1021     [VCAP_ES0_ACT_DEI_A_VAL]        = { 32,  1},
1022     [VCAP_ES0_ACT_VID_B_VAL]        = { 33, 12},
1023     [VCAP_ES0_ACT_PCP_B_VAL]        = { 45,  3},
1024     [VCAP_ES0_ACT_DEI_B_VAL]        = { 48,  1},
1025     [VCAP_ES0_ACT_RSV]          = { 49, 23},
1026     [VCAP_ES0_ACT_HIT_STICKY]       = { 72,  1},
1027 };
1028 
1029 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
1030     [VCAP_IS1_HK_TYPE]          = {  0,   1},
1031     [VCAP_IS1_HK_LOOKUP]            = {  1,   2},
1032     [VCAP_IS1_HK_IGR_PORT_MASK]     = {  3,   7},
1033     [VCAP_IS1_HK_RSV]           = { 10,   9},
1034     [VCAP_IS1_HK_OAM_Y1731]         = { 19,   1},
1035     [VCAP_IS1_HK_L2_MC]         = { 20,   1},
1036     [VCAP_IS1_HK_L2_BC]         = { 21,   1},
1037     [VCAP_IS1_HK_IP_MC]         = { 22,   1},
1038     [VCAP_IS1_HK_VLAN_TAGGED]       = { 23,   1},
1039     [VCAP_IS1_HK_VLAN_DBL_TAGGED]       = { 24,   1},
1040     [VCAP_IS1_HK_TPID]          = { 25,   1},
1041     [VCAP_IS1_HK_VID]           = { 26,  12},
1042     [VCAP_IS1_HK_DEI]           = { 38,   1},
1043     [VCAP_IS1_HK_PCP]           = { 39,   3},
1044     /* Specific Fields for IS1 Half Key S1_NORMAL */
1045     [VCAP_IS1_HK_L2_SMAC]           = { 42,  48},
1046     [VCAP_IS1_HK_ETYPE_LEN]         = { 90,   1},
1047     [VCAP_IS1_HK_ETYPE]         = { 91,  16},
1048     [VCAP_IS1_HK_IP_SNAP]           = {107,   1},
1049     [VCAP_IS1_HK_IP4]           = {108,   1},
1050     /* Layer-3 Information */
1051     [VCAP_IS1_HK_L3_FRAGMENT]       = {109,   1},
1052     [VCAP_IS1_HK_L3_FRAG_OFS_GT0]       = {110,   1},
1053     [VCAP_IS1_HK_L3_OPTIONS]        = {111,   1},
1054     [VCAP_IS1_HK_L3_DSCP]           = {112,   6},
1055     [VCAP_IS1_HK_L3_IP4_SIP]        = {118,  32},
1056     /* Layer-4 Information */
1057     [VCAP_IS1_HK_TCP_UDP]           = {150,   1},
1058     [VCAP_IS1_HK_TCP]           = {151,   1},
1059     [VCAP_IS1_HK_L4_SPORT]          = {152,  16},
1060     [VCAP_IS1_HK_L4_RNG]            = {168,   8},
1061     /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
1062     [VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
1063     [VCAP_IS1_HK_IP4_INNER_VID]     = { 43,  12},
1064     [VCAP_IS1_HK_IP4_INNER_DEI]     = { 55,   1},
1065     [VCAP_IS1_HK_IP4_INNER_PCP]     = { 56,   3},
1066     [VCAP_IS1_HK_IP4_IP4]           = { 59,   1},
1067     [VCAP_IS1_HK_IP4_L3_FRAGMENT]       = { 60,   1},
1068     [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]   = { 61,   1},
1069     [VCAP_IS1_HK_IP4_L3_OPTIONS]        = { 62,   1},
1070     [VCAP_IS1_HK_IP4_L3_DSCP]       = { 63,   6},
1071     [VCAP_IS1_HK_IP4_L3_IP4_DIP]        = { 69,  32},
1072     [VCAP_IS1_HK_IP4_L3_IP4_SIP]        = {101,  32},
1073     [VCAP_IS1_HK_IP4_L3_PROTO]      = {133,   8},
1074     [VCAP_IS1_HK_IP4_TCP_UDP]       = {141,   1},
1075     [VCAP_IS1_HK_IP4_TCP]           = {142,   1},
1076     [VCAP_IS1_HK_IP4_L4_RNG]        = {143,   8},
1077     [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = {151,  32},
1078 };
1079 
1080 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
1081     [VCAP_IS1_ACT_DSCP_ENA]         = {  0,  1},
1082     [VCAP_IS1_ACT_DSCP_VAL]         = {  1,  6},
1083     [VCAP_IS1_ACT_QOS_ENA]          = {  7,  1},
1084     [VCAP_IS1_ACT_QOS_VAL]          = {  8,  3},
1085     [VCAP_IS1_ACT_DP_ENA]           = { 11,  1},
1086     [VCAP_IS1_ACT_DP_VAL]           = { 12,  1},
1087     [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]    = { 13,  8},
1088     [VCAP_IS1_ACT_PAG_VAL]          = { 21,  8},
1089     [VCAP_IS1_ACT_RSV]          = { 29,  9},
1090     /* The fields below are incorrectly shifted by 2 in the manual */
1091     [VCAP_IS1_ACT_VID_REPLACE_ENA]      = { 38,  1},
1092     [VCAP_IS1_ACT_VID_ADD_VAL]      = { 39, 12},
1093     [VCAP_IS1_ACT_FID_SEL]          = { 51,  2},
1094     [VCAP_IS1_ACT_FID_VAL]          = { 53, 13},
1095     [VCAP_IS1_ACT_PCP_DEI_ENA]      = { 66,  1},
1096     [VCAP_IS1_ACT_PCP_VAL]          = { 67,  3},
1097     [VCAP_IS1_ACT_DEI_VAL]          = { 70,  1},
1098     [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]     = { 71,  1},
1099     [VCAP_IS1_ACT_VLAN_POP_CNT]     = { 72,  2},
1100     [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]  = { 74,  4},
1101     [VCAP_IS1_ACT_HIT_STICKY]       = { 78,  1},
1102 };
1103 
1104 static struct vcap_field vsc9959_vcap_is2_keys[] = {
1105     /* Common: 41 bits */
1106     [VCAP_IS2_TYPE]             = {  0,   4},
1107     [VCAP_IS2_HK_FIRST]         = {  4,   1},
1108     [VCAP_IS2_HK_PAG]           = {  5,   8},
1109     [VCAP_IS2_HK_IGR_PORT_MASK]     = { 13,   7},
1110     [VCAP_IS2_HK_RSV2]          = { 20,   1},
1111     [VCAP_IS2_HK_HOST_MATCH]        = { 21,   1},
1112     [VCAP_IS2_HK_L2_MC]         = { 22,   1},
1113     [VCAP_IS2_HK_L2_BC]         = { 23,   1},
1114     [VCAP_IS2_HK_VLAN_TAGGED]       = { 24,   1},
1115     [VCAP_IS2_HK_VID]           = { 25,  12},
1116     [VCAP_IS2_HK_DEI]           = { 37,   1},
1117     [VCAP_IS2_HK_PCP]           = { 38,   3},
1118     /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
1119     [VCAP_IS2_HK_L2_DMAC]           = { 41,  48},
1120     [VCAP_IS2_HK_L2_SMAC]           = { 89,  48},
1121     /* MAC_ETYPE (TYPE=000) */
1122     [VCAP_IS2_HK_MAC_ETYPE_ETYPE]       = {137,  16},
1123     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153,  16},
1124     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169,   8},
1125     [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177,   3},
1126     /* MAC_LLC (TYPE=001) */
1127     [VCAP_IS2_HK_MAC_LLC_L2_LLC]        = {137,  40},
1128     /* MAC_SNAP (TYPE=010) */
1129     [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]      = {137,  40},
1130     /* MAC_ARP (TYPE=011) */
1131     [VCAP_IS2_HK_MAC_ARP_SMAC]      = { 41,  48},
1132     [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89,   1},
1133     [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 90,   1},
1134     [VCAP_IS2_HK_MAC_ARP_LEN_OK]        = { 91,   1},
1135     [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]  = { 92,   1},
1136     [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]  = { 93,   1},
1137     [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 94,   1},
1138     [VCAP_IS2_HK_MAC_ARP_OPCODE]        = { 95,   2},
1139     [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]    = { 97,  32},
1140     [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]    = {129,  32},
1141     [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]    = {161,   1},
1142     /* IP4_TCP_UDP / IP4_OTHER common */
1143     [VCAP_IS2_HK_IP4]           = { 41,   1},
1144     [VCAP_IS2_HK_L3_FRAGMENT]       = { 42,   1},
1145     [VCAP_IS2_HK_L3_FRAG_OFS_GT0]       = { 43,   1},
1146     [VCAP_IS2_HK_L3_OPTIONS]        = { 44,   1},
1147     [VCAP_IS2_HK_IP4_L3_TTL_GT0]        = { 45,   1},
1148     [VCAP_IS2_HK_L3_TOS]            = { 46,   8},
1149     [VCAP_IS2_HK_L3_IP4_DIP]        = { 54,  32},
1150     [VCAP_IS2_HK_L3_IP4_SIP]        = { 86,  32},
1151     [VCAP_IS2_HK_DIP_EQ_SIP]        = {118,   1},
1152     /* IP4_TCP_UDP (TYPE=100) */
1153     [VCAP_IS2_HK_TCP]           = {119,   1},
1154     [VCAP_IS2_HK_L4_DPORT]          = {120,  16},
1155     [VCAP_IS2_HK_L4_SPORT]          = {136,  16},
1156     [VCAP_IS2_HK_L4_RNG]            = {152,   8},
1157     [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]     = {160,   1},
1158     [VCAP_IS2_HK_L4_SEQUENCE_EQ0]       = {161,   1},
1159     [VCAP_IS2_HK_L4_FIN]            = {162,   1},
1160     [VCAP_IS2_HK_L4_SYN]            = {163,   1},
1161     [VCAP_IS2_HK_L4_RST]            = {164,   1},
1162     [VCAP_IS2_HK_L4_PSH]            = {165,   1},
1163     [VCAP_IS2_HK_L4_ACK]            = {166,   1},
1164     [VCAP_IS2_HK_L4_URG]            = {167,   1},
1165     [VCAP_IS2_HK_L4_1588_DOM]       = {168,   8},
1166     [VCAP_IS2_HK_L4_1588_VER]       = {176,   4},
1167     /* IP4_OTHER (TYPE=101) */
1168     [VCAP_IS2_HK_IP4_L3_PROTO]      = {119,   8},
1169     [VCAP_IS2_HK_L3_PAYLOAD]        = {127,  56},
1170     /* IP6_STD (TYPE=110) */
1171     [VCAP_IS2_HK_IP6_L3_TTL_GT0]        = { 41,   1},
1172     [VCAP_IS2_HK_L3_IP6_SIP]        = { 42, 128},
1173     [VCAP_IS2_HK_IP6_L3_PROTO]      = {170,   8},
1174     /* OAM (TYPE=111) */
1175     [VCAP_IS2_HK_OAM_MEL_FLAGS]     = {137,   7},
1176     [VCAP_IS2_HK_OAM_VER]           = {144,   5},
1177     [VCAP_IS2_HK_OAM_OPCODE]        = {149,   8},
1178     [VCAP_IS2_HK_OAM_FLAGS]         = {157,   8},
1179     [VCAP_IS2_HK_OAM_MEPID]         = {165,  16},
1180     [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]      = {181,   1},
1181     [VCAP_IS2_HK_OAM_IS_Y1731]      = {182,   1},
1182 };
1183 
1184 static struct vcap_field vsc9959_vcap_is2_actions[] = {
1185     [VCAP_IS2_ACT_HIT_ME_ONCE]      = {  0,  1},
1186     [VCAP_IS2_ACT_CPU_COPY_ENA]     = {  1,  1},
1187     [VCAP_IS2_ACT_CPU_QU_NUM]       = {  2,  3},
1188     [VCAP_IS2_ACT_MASK_MODE]        = {  5,  2},
1189     [VCAP_IS2_ACT_MIRROR_ENA]       = {  7,  1},
1190     [VCAP_IS2_ACT_LRN_DIS]          = {  8,  1},
1191     [VCAP_IS2_ACT_POLICE_ENA]       = {  9,  1},
1192     [VCAP_IS2_ACT_POLICE_IDX]       = { 10,  9},
1193     [VCAP_IS2_ACT_POLICE_VCAP_ONLY]     = { 19,  1},
1194     [VCAP_IS2_ACT_PORT_MASK]        = { 20,  6},
1195     [VCAP_IS2_ACT_REW_OP]           = { 26,  9},
1196     [VCAP_IS2_ACT_SMAC_REPLACE_ENA]     = { 35,  1},
1197     [VCAP_IS2_ACT_RSV]          = { 36,  2},
1198     [VCAP_IS2_ACT_ACL_ID]           = { 38,  6},
1199     [VCAP_IS2_ACT_HIT_CNT]          = { 44, 32},
1200 };
1201 
1202 static struct vcap_props vsc9959_vcap_props[] = {
1203     [VCAP_ES0] = {
1204         .action_type_width = 0,
1205         .action_table = {
1206             [ES0_ACTION_TYPE_NORMAL] = {
1207                 .width = 72, /* HIT_STICKY not included */
1208                 .count = 1,
1209             },
1210         },
1211         .target = S0,
1212         .keys = vsc9959_vcap_es0_keys,
1213         .actions = vsc9959_vcap_es0_actions,
1214     },
1215     [VCAP_IS1] = {
1216         .action_type_width = 0,
1217         .action_table = {
1218             [IS1_ACTION_TYPE_NORMAL] = {
1219                 .width = 78, /* HIT_STICKY not included */
1220                 .count = 4,
1221             },
1222         },
1223         .target = S1,
1224         .keys = vsc9959_vcap_is1_keys,
1225         .actions = vsc9959_vcap_is1_actions,
1226     },
1227     [VCAP_IS2] = {
1228         .action_type_width = 1,
1229         .action_table = {
1230             [IS2_ACTION_TYPE_NORMAL] = {
1231                 .width = 44,
1232                 .count = 2
1233             },
1234             [IS2_ACTION_TYPE_SMAC_SIP] = {
1235                 .width = 6,
1236                 .count = 4
1237             },
1238         },
1239         .target = S2,
1240         .keys = vsc9959_vcap_is2_keys,
1241         .actions = vsc9959_vcap_is2_actions,
1242     },
1243 };
1244 
1245 static const struct ptp_clock_info vsc9959_ptp_caps = {
1246     .owner      = THIS_MODULE,
1247     .name       = "felix ptp",
1248     .max_adj    = 0x7fffffff,
1249     .n_alarm    = 0,
1250     .n_ext_ts   = 0,
1251     .n_per_out  = OCELOT_PTP_PINS_NUM,
1252     .n_pins     = OCELOT_PTP_PINS_NUM,
1253     .pps        = 0,
1254     .gettime64  = ocelot_ptp_gettime64,
1255     .settime64  = ocelot_ptp_settime64,
1256     .adjtime    = ocelot_ptp_adjtime,
1257     .adjfine    = ocelot_ptp_adjfine,
1258     .verify     = ocelot_ptp_verify,
1259     .enable     = ocelot_ptp_enable,
1260 };
1261 
1262 #define VSC9959_INIT_TIMEOUT            50000
1263 #define VSC9959_GCB_RST_SLEEP           100
1264 #define VSC9959_SYS_RAMINIT_SLEEP       80
1265 
1266 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
1267 {
1268     int val;
1269 
1270     ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
1271 
1272     return val;
1273 }
1274 
1275 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
1276 {
1277     return ocelot_read(ocelot, SYS_RAM_INIT);
1278 }
1279 
1280 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
1281  * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
1282  */
1283 static int vsc9959_reset(struct ocelot *ocelot)
1284 {
1285     int val, err;
1286 
1287     /* soft-reset the switch core */
1288     ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
1289 
1290     err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
1291                  VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
1292     if (err) {
1293         dev_err(ocelot->dev, "timeout: switch core reset\n");
1294         return err;
1295     }
1296 
1297     /* initialize switch mem ~40us */
1298     ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
1299     err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
1300                  VSC9959_SYS_RAMINIT_SLEEP,
1301                  VSC9959_INIT_TIMEOUT);
1302     if (err) {
1303         dev_err(ocelot->dev, "timeout: switch sram init\n");
1304         return err;
1305     }
1306 
1307     /* enable switch core */
1308     ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
1309 
1310     return 0;
1311 }
1312 
1313 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
1314                      unsigned long *supported,
1315                      struct phylink_link_state *state)
1316 {
1317     __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1318 
1319     phylink_set_port_modes(mask);
1320     phylink_set(mask, Autoneg);
1321     phylink_set(mask, Pause);
1322     phylink_set(mask, Asym_Pause);
1323     phylink_set(mask, 10baseT_Half);
1324     phylink_set(mask, 10baseT_Full);
1325     phylink_set(mask, 100baseT_Half);
1326     phylink_set(mask, 100baseT_Full);
1327     phylink_set(mask, 1000baseT_Half);
1328     phylink_set(mask, 1000baseT_Full);
1329     phylink_set(mask, 1000baseX_Full);
1330 
1331     if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
1332         state->interface == PHY_INTERFACE_MODE_2500BASEX ||
1333         state->interface == PHY_INTERFACE_MODE_USXGMII) {
1334         phylink_set(mask, 2500baseT_Full);
1335         phylink_set(mask, 2500baseX_Full);
1336     }
1337 
1338     linkmode_and(supported, supported, mask);
1339     linkmode_and(state->advertising, state->advertising, mask);
1340 }
1341 
1342 /* Watermark encode
1343  * Bit 8:   Unit; 0:1, 1:16
1344  * Bit 7-0: Value to be multiplied with unit
1345  */
1346 static u16 vsc9959_wm_enc(u16 value)
1347 {
1348     WARN_ON(value >= 16 * BIT(8));
1349 
1350     if (value >= BIT(8))
1351         return BIT(8) | (value / 16);
1352 
1353     return value;
1354 }
1355 
1356 static u16 vsc9959_wm_dec(u16 wm)
1357 {
1358     WARN_ON(wm & ~GENMASK(8, 0));
1359 
1360     if (wm & BIT(8))
1361         return (wm & GENMASK(7, 0)) * 16;
1362 
1363     return wm;
1364 }
1365 
1366 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1367 {
1368     *inuse = (val & GENMASK(23, 12)) >> 12;
1369     *maxuse = val & GENMASK(11, 0);
1370 }
1371 
1372 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1373 {
1374     struct felix *felix = ocelot_to_felix(ocelot);
1375     struct enetc_mdio_priv *mdio_priv;
1376     struct device *dev = ocelot->dev;
1377     void __iomem *imdio_regs;
1378     struct resource res;
1379     struct enetc_hw *hw;
1380     struct mii_bus *bus;
1381     int port;
1382     int rc;
1383 
1384     felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1385                   sizeof(struct phylink_pcs *),
1386                   GFP_KERNEL);
1387     if (!felix->pcs) {
1388         dev_err(dev, "failed to allocate array for PCS PHYs\n");
1389         return -ENOMEM;
1390     }
1391 
1392     memcpy(&res, felix->info->imdio_res, sizeof(res));
1393     res.flags = IORESOURCE_MEM;
1394     res.start += felix->imdio_base;
1395     res.end += felix->imdio_base;
1396 
1397     imdio_regs = devm_ioremap_resource(dev, &res);
1398     if (IS_ERR(imdio_regs))
1399         return PTR_ERR(imdio_regs);
1400 
1401     hw = enetc_hw_alloc(dev, imdio_regs);
1402     if (IS_ERR(hw)) {
1403         dev_err(dev, "failed to allocate ENETC HW structure\n");
1404         return PTR_ERR(hw);
1405     }
1406 
1407     bus = mdiobus_alloc_size(sizeof(*mdio_priv));
1408     if (!bus)
1409         return -ENOMEM;
1410 
1411     bus->name = "VSC9959 internal MDIO bus";
1412     bus->read = enetc_mdio_read;
1413     bus->write = enetc_mdio_write;
1414     bus->parent = dev;
1415     mdio_priv = bus->priv;
1416     mdio_priv->hw = hw;
1417     /* This gets added to imdio_regs, which already maps addresses
1418      * starting with the proper offset.
1419      */
1420     mdio_priv->mdio_base = 0;
1421     snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1422 
1423     /* Needed in order to initialize the bus mutex lock */
1424     rc = mdiobus_register(bus);
1425     if (rc < 0) {
1426         dev_err(dev, "failed to register MDIO bus\n");
1427         mdiobus_free(bus);
1428         return rc;
1429     }
1430 
1431     felix->imdio = bus;
1432 
1433     for (port = 0; port < felix->info->num_ports; port++) {
1434         struct ocelot_port *ocelot_port = ocelot->ports[port];
1435         struct phylink_pcs *phylink_pcs;
1436         struct mdio_device *mdio_device;
1437 
1438         if (dsa_is_unused_port(felix->ds, port))
1439             continue;
1440 
1441         if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1442             continue;
1443 
1444         mdio_device = mdio_device_create(felix->imdio, port);
1445         if (IS_ERR(mdio_device))
1446             continue;
1447 
1448         phylink_pcs = lynx_pcs_create(mdio_device);
1449         if (!phylink_pcs) {
1450             mdio_device_free(mdio_device);
1451             continue;
1452         }
1453 
1454         felix->pcs[port] = phylink_pcs;
1455 
1456         dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1457     }
1458 
1459     return 0;
1460 }
1461 
1462 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1463 {
1464     struct felix *felix = ocelot_to_felix(ocelot);
1465     int port;
1466 
1467     for (port = 0; port < ocelot->num_phys_ports; port++) {
1468         struct phylink_pcs *phylink_pcs = felix->pcs[port];
1469         struct mdio_device *mdio_device;
1470 
1471         if (!phylink_pcs)
1472             continue;
1473 
1474         mdio_device = lynx_get_mdio_device(phylink_pcs);
1475         mdio_device_free(mdio_device);
1476         lynx_pcs_destroy(phylink_pcs);
1477     }
1478     mdiobus_unregister(felix->imdio);
1479     mdiobus_free(felix->imdio);
1480 }
1481 
1482 /* The switch considers any frame (regardless of size) as eligible for
1483  * transmission if the traffic class gate is open for at least 33 ns.
1484  * Overruns are prevented by cropping an interval at the end of the gate time
1485  * slot for which egress scheduling is blocked, but we need to still keep 33 ns
1486  * available for one packet to be transmitted, otherwise the port tc will hang.
1487  * This function returns the size of a gate interval that remains available for
1488  * setting the guard band, after reserving the space for one egress frame.
1489  */
1490 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns)
1491 {
1492     /* Gate always open */
1493     if (gate_len_ns == U64_MAX)
1494         return U64_MAX;
1495 
1496     return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC;
1497 }
1498 
1499 /* Extract shortest continuous gate open intervals in ns for each traffic class
1500  * of a cyclic tc-taprio schedule. If a gate is always open, the duration is
1501  * considered U64_MAX. If the gate is always closed, it is considered 0.
1502  */
1503 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio,
1504                      u64 min_gate_len[OCELOT_NUM_TC])
1505 {
1506     struct tc_taprio_sched_entry *entry;
1507     u64 gate_len[OCELOT_NUM_TC];
1508     u8 gates_ever_opened = 0;
1509     int tc, i, n;
1510 
1511     /* Initialize arrays */
1512     for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1513         min_gate_len[tc] = U64_MAX;
1514         gate_len[tc] = 0;
1515     }
1516 
1517     /* If we don't have taprio, consider all gates as permanently open */
1518     if (!taprio)
1519         return;
1520 
1521     n = taprio->num_entries;
1522 
1523     /* Walk through the gate list twice to determine the length
1524      * of consecutively open gates for a traffic class, including
1525      * open gates that wrap around. We are just interested in the
1526      * minimum window size, and this doesn't change what the
1527      * minimum is (if the gate never closes, min_gate_len will
1528      * remain U64_MAX).
1529      */
1530     for (i = 0; i < 2 * n; i++) {
1531         entry = &taprio->entries[i % n];
1532 
1533         for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1534             if (entry->gate_mask & BIT(tc)) {
1535                 gate_len[tc] += entry->interval;
1536                 gates_ever_opened |= BIT(tc);
1537             } else {
1538                 /* Gate closes now, record a potential new
1539                  * minimum and reinitialize length
1540                  */
1541                 if (min_gate_len[tc] > gate_len[tc] &&
1542                     gate_len[tc])
1543                     min_gate_len[tc] = gate_len[tc];
1544                 gate_len[tc] = 0;
1545             }
1546         }
1547     }
1548 
1549     /* min_gate_len[tc] actually tracks minimum *open* gate time, so for
1550      * permanently closed gates, min_gate_len[tc] will still be U64_MAX.
1551      * Therefore they are currently indistinguishable from permanently
1552      * open gates. Overwrite the gate len with 0 when we know they're
1553      * actually permanently closed, i.e. after the loop above.
1554      */
1555     for (tc = 0; tc < OCELOT_NUM_TC; tc++)
1556         if (!(gates_ever_opened & BIT(tc)))
1557             min_gate_len[tc] = 0;
1558 }
1559 
1560 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ,
1561  * so we need to spell out the register access to each traffic class in helper
1562  * functions, to simplify callers
1563  */
1564 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc,
1565                      u32 max_sdu)
1566 {
1567     switch (tc) {
1568     case 0:
1569         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0,
1570                  port);
1571         break;
1572     case 1:
1573         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1,
1574                  port);
1575         break;
1576     case 2:
1577         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2,
1578                  port);
1579         break;
1580     case 3:
1581         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3,
1582                  port);
1583         break;
1584     case 4:
1585         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4,
1586                  port);
1587         break;
1588     case 5:
1589         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5,
1590                  port);
1591         break;
1592     case 6:
1593         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6,
1594                  port);
1595         break;
1596     case 7:
1597         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7,
1598                  port);
1599         break;
1600     }
1601 }
1602 
1603 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc)
1604 {
1605     switch (tc) {
1606     case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port);
1607     case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port);
1608     case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port);
1609     case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port);
1610     case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port);
1611     case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port);
1612     case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port);
1613     case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port);
1614     default:
1615         return 0;
1616     }
1617 }
1618 
1619 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the
1620  * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU
1621  * values (the default value is 1518). Also, for traffic class windows smaller
1622  * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame
1623  * dropping, such that these won't hang the port, as they will never be sent.
1624  */
1625 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port)
1626 {
1627     struct ocelot_port *ocelot_port = ocelot->ports[port];
1628     u64 min_gate_len[OCELOT_NUM_TC];
1629     int speed, picos_per_byte;
1630     u64 needed_bit_time_ps;
1631     u32 val, maxlen;
1632     u8 tas_speed;
1633     int tc;
1634 
1635     lockdep_assert_held(&ocelot->tas_lock);
1636 
1637     val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1638     tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val);
1639 
1640     switch (tas_speed) {
1641     case OCELOT_SPEED_10:
1642         speed = SPEED_10;
1643         break;
1644     case OCELOT_SPEED_100:
1645         speed = SPEED_100;
1646         break;
1647     case OCELOT_SPEED_1000:
1648         speed = SPEED_1000;
1649         break;
1650     case OCELOT_SPEED_2500:
1651         speed = SPEED_2500;
1652         break;
1653     default:
1654         return;
1655     }
1656 
1657     picos_per_byte = (USEC_PER_SEC * 8) / speed;
1658 
1659     val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG);
1660     /* MAXLEN_CFG accounts automatically for VLAN. We need to include it
1661      * manually in the bit time calculation, plus the preamble and SFD.
1662      */
1663     maxlen = val + 2 * VLAN_HLEN;
1664     /* Consider the standard Ethernet overhead of 8 octets preamble+SFD,
1665      * 4 octets FCS, 12 octets IFG.
1666      */
1667     needed_bit_time_ps = (maxlen + 24) * picos_per_byte;
1668 
1669     dev_dbg(ocelot->dev,
1670         "port %d: max frame size %d needs %llu ps at speed %d\n",
1671         port, maxlen, needed_bit_time_ps, speed);
1672 
1673     vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len);
1674 
1675     mutex_lock(&ocelot->fwd_domain_lock);
1676 
1677     for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1678         u64 remaining_gate_len_ps;
1679         u32 max_sdu;
1680 
1681         remaining_gate_len_ps =
1682             vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]);
1683 
1684         if (remaining_gate_len_ps > needed_bit_time_ps) {
1685             /* Setting QMAXSDU_CFG to 0 disables oversized frame
1686              * dropping.
1687              */
1688             max_sdu = 0;
1689             dev_dbg(ocelot->dev,
1690                 "port %d tc %d min gate len %llu"
1691                 ", sending all frames\n",
1692                 port, tc, min_gate_len[tc]);
1693         } else {
1694             /* If traffic class doesn't support a full MTU sized
1695              * frame, make sure to enable oversize frame dropping
1696              * for frames larger than the smallest that would fit.
1697              *
1698              * However, the exact same register, QSYS_QMAXSDU_CFG_*,
1699              * controls not only oversized frame dropping, but also
1700              * per-tc static guard band lengths, so it reduces the
1701              * useful gate interval length. Therefore, be careful
1702              * to calculate a guard band (and therefore max_sdu)
1703              * that still leaves 33 ns available in the time slot.
1704              */
1705             max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte);
1706             /* A TC gate may be completely closed, which is a
1707              * special case where all packets are oversized.
1708              * Any limit smaller than 64 octets accomplishes this
1709              */
1710             if (!max_sdu)
1711                 max_sdu = 1;
1712             /* Take L1 overhead into account, but just don't allow
1713              * max_sdu to go negative or to 0. Here we use 20
1714              * because QSYS_MAXSDU_CFG_* already counts the 4 FCS
1715              * octets as part of packet size.
1716              */
1717             if (max_sdu > 20)
1718                 max_sdu -= 20;
1719             dev_info(ocelot->dev,
1720                  "port %d tc %d min gate length %llu"
1721                  " ns not enough for max frame size %d at %d"
1722                  " Mbps, dropping frames over %d"
1723                  " octets including FCS\n",
1724                  port, tc, min_gate_len[tc], maxlen, speed,
1725                  max_sdu);
1726         }
1727 
1728         vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu);
1729     }
1730 
1731     ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port);
1732 
1733     ocelot->ops->cut_through_fwd(ocelot);
1734 
1735     mutex_unlock(&ocelot->fwd_domain_lock);
1736 }
1737 
1738 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1739                     u32 speed)
1740 {
1741     struct ocelot_port *ocelot_port = ocelot->ports[port];
1742     u8 tas_speed;
1743 
1744     switch (speed) {
1745     case SPEED_10:
1746         tas_speed = OCELOT_SPEED_10;
1747         break;
1748     case SPEED_100:
1749         tas_speed = OCELOT_SPEED_100;
1750         break;
1751     case SPEED_1000:
1752         tas_speed = OCELOT_SPEED_1000;
1753         break;
1754     case SPEED_2500:
1755         tas_speed = OCELOT_SPEED_2500;
1756         break;
1757     default:
1758         tas_speed = OCELOT_SPEED_1000;
1759         break;
1760     }
1761 
1762     mutex_lock(&ocelot->tas_lock);
1763 
1764     ocelot_rmw_rix(ocelot,
1765                QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1766                QSYS_TAG_CONFIG_LINK_SPEED_M,
1767                QSYS_TAG_CONFIG, port);
1768 
1769     if (ocelot_port->taprio)
1770         vsc9959_tas_guard_bands_update(ocelot, port);
1771 
1772     mutex_unlock(&ocelot->tas_lock);
1773 }
1774 
1775 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1776                   u64 cycle_time,
1777                   struct timespec64 *new_base_ts)
1778 {
1779     struct timespec64 ts;
1780     ktime_t new_base_time;
1781     ktime_t current_time;
1782 
1783     ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1784     current_time = timespec64_to_ktime(ts);
1785     new_base_time = base_time;
1786 
1787     if (base_time < current_time) {
1788         u64 nr_of_cycles = current_time - base_time;
1789 
1790         do_div(nr_of_cycles, cycle_time);
1791         new_base_time += cycle_time * (nr_of_cycles + 1);
1792     }
1793 
1794     *new_base_ts = ktime_to_timespec64(new_base_time);
1795 }
1796 
1797 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1798 {
1799     return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1800 }
1801 
1802 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1803                 struct tc_taprio_sched_entry *entry)
1804 {
1805     ocelot_write(ocelot,
1806              QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1807              QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1808              QSYS_GCL_CFG_REG_1);
1809     ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1810 }
1811 
1812 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1813                     struct tc_taprio_qopt_offload *taprio)
1814 {
1815     struct ocelot_port *ocelot_port = ocelot->ports[port];
1816     struct timespec64 base_ts;
1817     int ret, i;
1818     u32 val;
1819 
1820     mutex_lock(&ocelot->tas_lock);
1821 
1822     if (!taprio->enable) {
1823         ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1824                    QSYS_TAG_CONFIG, port);
1825 
1826         taprio_offload_free(ocelot_port->taprio);
1827         ocelot_port->taprio = NULL;
1828 
1829         vsc9959_tas_guard_bands_update(ocelot, port);
1830 
1831         mutex_unlock(&ocelot->tas_lock);
1832         return 0;
1833     }
1834 
1835     if (taprio->cycle_time > NSEC_PER_SEC ||
1836         taprio->cycle_time_extension >= NSEC_PER_SEC) {
1837         ret = -EINVAL;
1838         goto err;
1839     }
1840 
1841     if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) {
1842         ret = -ERANGE;
1843         goto err;
1844     }
1845 
1846     /* Enable guard band. The switch will schedule frames without taking
1847      * their length into account. Thus we'll always need to enable the
1848      * guard band which reserves the time of a maximum sized frame at the
1849      * end of the time window.
1850      *
1851      * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1852      * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1853      * operate on the port number.
1854      */
1855     ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1856            QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1857            QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1858            QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1859            QSYS_TAS_PARAM_CFG_CTRL);
1860 
1861     /* Hardware errata -  Admin config could not be overwritten if
1862      * config is pending, need reset the TAS module
1863      */
1864     val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1865     if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1866         ret = -EBUSY;
1867         goto err;
1868     }
1869 
1870     ocelot_rmw_rix(ocelot,
1871                QSYS_TAG_CONFIG_ENABLE |
1872                QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1873                QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1874                QSYS_TAG_CONFIG_ENABLE |
1875                QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1876                QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1877                QSYS_TAG_CONFIG, port);
1878 
1879     vsc9959_new_base_time(ocelot, taprio->base_time,
1880                   taprio->cycle_time, &base_ts);
1881     ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1882     ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1883     val = upper_32_bits(base_ts.tv_sec);
1884     ocelot_write(ocelot,
1885              QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1886              QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1887              QSYS_PARAM_CFG_REG_3);
1888     ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1889     ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1890 
1891     for (i = 0; i < taprio->num_entries; i++)
1892         vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1893 
1894     ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1895            QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1896            QSYS_TAS_PARAM_CFG_CTRL);
1897 
1898     ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1899                  !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1900                  10, 100000);
1901     if (ret)
1902         goto err;
1903 
1904     ocelot_port->taprio = taprio_offload_get(taprio);
1905     vsc9959_tas_guard_bands_update(ocelot, port);
1906 
1907 err:
1908     mutex_unlock(&ocelot->tas_lock);
1909 
1910     return ret;
1911 }
1912 
1913 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot)
1914 {
1915     struct tc_taprio_qopt_offload *taprio;
1916     struct ocelot_port *ocelot_port;
1917     struct timespec64 base_ts;
1918     int port;
1919     u32 val;
1920 
1921     mutex_lock(&ocelot->tas_lock);
1922 
1923     for (port = 0; port < ocelot->num_phys_ports; port++) {
1924         ocelot_port = ocelot->ports[port];
1925         taprio = ocelot_port->taprio;
1926         if (!taprio)
1927             continue;
1928 
1929         ocelot_rmw(ocelot,
1930                QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port),
1931                QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M,
1932                QSYS_TAS_PARAM_CFG_CTRL);
1933 
1934         /* Disable time-aware shaper */
1935         ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1936                    QSYS_TAG_CONFIG, port);
1937 
1938         vsc9959_new_base_time(ocelot, taprio->base_time,
1939                       taprio->cycle_time, &base_ts);
1940 
1941         ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1942         ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec),
1943                  QSYS_PARAM_CFG_REG_2);
1944         val = upper_32_bits(base_ts.tv_sec);
1945         ocelot_rmw(ocelot,
1946                QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val),
1947                QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M,
1948                QSYS_PARAM_CFG_REG_3);
1949 
1950         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1951                QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1952                QSYS_TAS_PARAM_CFG_CTRL);
1953 
1954         /* Re-enable time-aware shaper */
1955         ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE,
1956                    QSYS_TAG_CONFIG_ENABLE,
1957                    QSYS_TAG_CONFIG, port);
1958     }
1959     mutex_unlock(&ocelot->tas_lock);
1960 }
1961 
1962 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1963                     struct tc_cbs_qopt_offload *cbs_qopt)
1964 {
1965     struct ocelot *ocelot = ds->priv;
1966     int port_ix = port * 8 + cbs_qopt->queue;
1967     u32 rate, burst;
1968 
1969     if (cbs_qopt->queue >= ds->num_tx_queues)
1970         return -EINVAL;
1971 
1972     if (!cbs_qopt->enable) {
1973         ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1974                  QSYS_CIR_CFG_CIR_BURST(0),
1975                  QSYS_CIR_CFG, port_ix);
1976 
1977         ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1978                    QSYS_SE_CFG, port_ix);
1979 
1980         return 0;
1981     }
1982 
1983     /* Rate unit is 100 kbps */
1984     rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1985     /* Avoid using zero rate */
1986     rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1987     /* Burst unit is 4kB */
1988     burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1989     /* Avoid using zero burst size */
1990     burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1991     ocelot_write_gix(ocelot,
1992              QSYS_CIR_CFG_CIR_RATE(rate) |
1993              QSYS_CIR_CFG_CIR_BURST(burst),
1994              QSYS_CIR_CFG,
1995              port_ix);
1996 
1997     ocelot_rmw_gix(ocelot,
1998                QSYS_SE_CFG_SE_FRM_MODE(0) |
1999                QSYS_SE_CFG_SE_AVB_ENA,
2000                QSYS_SE_CFG_SE_AVB_ENA |
2001                QSYS_SE_CFG_SE_FRM_MODE_M,
2002                QSYS_SE_CFG,
2003                port_ix);
2004 
2005     return 0;
2006 }
2007 
2008 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
2009                  enum tc_setup_type type,
2010                  void *type_data)
2011 {
2012     struct ocelot *ocelot = ds->priv;
2013 
2014     switch (type) {
2015     case TC_SETUP_QDISC_TAPRIO:
2016         return vsc9959_qos_port_tas_set(ocelot, port, type_data);
2017     case TC_SETUP_QDISC_CBS:
2018         return vsc9959_qos_port_cbs_set(ds, port, type_data);
2019     default:
2020         return -EOPNOTSUPP;
2021     }
2022 }
2023 
2024 #define VSC9959_PSFP_SFID_MAX           175
2025 #define VSC9959_PSFP_GATE_ID_MAX        183
2026 #define VSC9959_PSFP_POLICER_BASE       63
2027 #define VSC9959_PSFP_POLICER_MAX        383
2028 #define VSC9959_PSFP_GATE_LIST_NUM      4
2029 #define VSC9959_PSFP_GATE_CYCLETIME_MIN     5000
2030 
2031 struct felix_stream {
2032     struct list_head list;
2033     unsigned long id;
2034     bool dummy;
2035     int ports;
2036     int port;
2037     u8 dmac[ETH_ALEN];
2038     u16 vid;
2039     s8 prio;
2040     u8 sfid_valid;
2041     u8 ssid_valid;
2042     u32 sfid;
2043     u32 ssid;
2044 };
2045 
2046 struct felix_stream_filter {
2047     struct list_head list;
2048     refcount_t refcount;
2049     u32 index;
2050     u8 enable;
2051     int portmask;
2052     u8 sg_valid;
2053     u32 sgid;
2054     u8 fm_valid;
2055     u32 fmid;
2056     u8 prio_valid;
2057     u8 prio;
2058     u32 maxsdu;
2059 };
2060 
2061 struct felix_stream_filter_counters {
2062     u32 match;
2063     u32 not_pass_gate;
2064     u32 not_pass_sdu;
2065     u32 red;
2066 };
2067 
2068 struct felix_stream_gate {
2069     u32 index;
2070     u8 enable;
2071     u8 ipv_valid;
2072     u8 init_ipv;
2073     u64 basetime;
2074     u64 cycletime;
2075     u64 cycletime_ext;
2076     u32 num_entries;
2077     struct action_gate_entry entries[];
2078 };
2079 
2080 struct felix_stream_gate_entry {
2081     struct list_head list;
2082     refcount_t refcount;
2083     u32 index;
2084 };
2085 
2086 static int vsc9959_stream_identify(struct flow_cls_offload *f,
2087                    struct felix_stream *stream)
2088 {
2089     struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2090     struct flow_dissector *dissector = rule->match.dissector;
2091 
2092     if (dissector->used_keys &
2093         ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2094           BIT(FLOW_DISSECTOR_KEY_BASIC) |
2095           BIT(FLOW_DISSECTOR_KEY_VLAN) |
2096           BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
2097         return -EOPNOTSUPP;
2098 
2099     if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2100         struct flow_match_eth_addrs match;
2101 
2102         flow_rule_match_eth_addrs(rule, &match);
2103         ether_addr_copy(stream->dmac, match.key->dst);
2104         if (!is_zero_ether_addr(match.mask->src))
2105             return -EOPNOTSUPP;
2106     } else {
2107         return -EOPNOTSUPP;
2108     }
2109 
2110     if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2111         struct flow_match_vlan match;
2112 
2113         flow_rule_match_vlan(rule, &match);
2114         if (match.mask->vlan_priority)
2115             stream->prio = match.key->vlan_priority;
2116         else
2117             stream->prio = -1;
2118 
2119         if (!match.mask->vlan_id)
2120             return -EOPNOTSUPP;
2121         stream->vid = match.key->vlan_id;
2122     } else {
2123         return -EOPNOTSUPP;
2124     }
2125 
2126     stream->id = f->cookie;
2127 
2128     return 0;
2129 }
2130 
2131 static int vsc9959_mact_stream_set(struct ocelot *ocelot,
2132                    struct felix_stream *stream,
2133                    struct netlink_ext_ack *extack)
2134 {
2135     enum macaccess_entry_type type;
2136     int ret, sfid, ssid;
2137     u32 vid, dst_idx;
2138     u8 mac[ETH_ALEN];
2139 
2140     ether_addr_copy(mac, stream->dmac);
2141     vid = stream->vid;
2142 
2143     /* Stream identification desn't support to add a stream with non
2144      * existent MAC (The MAC entry has not been learned in MAC table).
2145      */
2146     ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
2147     if (ret) {
2148         if (extack)
2149             NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
2150         return -EOPNOTSUPP;
2151     }
2152 
2153     if ((stream->sfid_valid || stream->ssid_valid) &&
2154         type == ENTRYTYPE_NORMAL)
2155         type = ENTRYTYPE_LOCKED;
2156 
2157     sfid = stream->sfid_valid ? stream->sfid : -1;
2158     ssid = stream->ssid_valid ? stream->ssid : -1;
2159 
2160     ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
2161                        sfid, ssid);
2162 
2163     return ret;
2164 }
2165 
2166 static struct felix_stream *
2167 vsc9959_stream_table_lookup(struct list_head *stream_list,
2168                 struct felix_stream *stream)
2169 {
2170     struct felix_stream *tmp;
2171 
2172     list_for_each_entry(tmp, stream_list, list)
2173         if (ether_addr_equal(tmp->dmac, stream->dmac) &&
2174             tmp->vid == stream->vid)
2175             return tmp;
2176 
2177     return NULL;
2178 }
2179 
2180 static int vsc9959_stream_table_add(struct ocelot *ocelot,
2181                     struct list_head *stream_list,
2182                     struct felix_stream *stream,
2183                     struct netlink_ext_ack *extack)
2184 {
2185     struct felix_stream *stream_entry;
2186     int ret;
2187 
2188     stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
2189     if (!stream_entry)
2190         return -ENOMEM;
2191 
2192     if (!stream->dummy) {
2193         ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
2194         if (ret) {
2195             kfree(stream_entry);
2196             return ret;
2197         }
2198     }
2199 
2200     list_add_tail(&stream_entry->list, stream_list);
2201 
2202     return 0;
2203 }
2204 
2205 static struct felix_stream *
2206 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
2207 {
2208     struct felix_stream *tmp;
2209 
2210     list_for_each_entry(tmp, stream_list, list)
2211         if (tmp->id == id)
2212             return tmp;
2213 
2214     return NULL;
2215 }
2216 
2217 static void vsc9959_stream_table_del(struct ocelot *ocelot,
2218                      struct felix_stream *stream)
2219 {
2220     if (!stream->dummy)
2221         vsc9959_mact_stream_set(ocelot, stream, NULL);
2222 
2223     list_del(&stream->list);
2224     kfree(stream);
2225 }
2226 
2227 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
2228 {
2229     return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
2230 }
2231 
2232 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
2233                 struct felix_stream_filter *sfi)
2234 {
2235     u32 val;
2236 
2237     if (sfi->index > VSC9959_PSFP_SFID_MAX)
2238         return -EINVAL;
2239 
2240     if (!sfi->enable) {
2241         ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
2242                  ANA_TABLES_SFIDTIDX);
2243 
2244         val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
2245         ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
2246 
2247         return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
2248                       (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
2249                       10, 100000);
2250     }
2251 
2252     if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
2253         sfi->fmid > VSC9959_PSFP_POLICER_MAX)
2254         return -EINVAL;
2255 
2256     ocelot_write(ocelot,
2257              (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
2258              ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
2259              (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
2260              ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
2261              ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
2262              ANA_TABLES_SFIDTIDX);
2263 
2264     ocelot_write(ocelot,
2265              (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
2266              ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
2267              ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
2268              ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
2269              ANA_TABLES_SFIDACCESS);
2270 
2271     return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
2272                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
2273                   10, 100000);
2274 }
2275 
2276 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
2277 {
2278     u32 val;
2279 
2280     ocelot_rmw(ocelot,
2281            ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
2282            ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
2283            ANA_TABLES_SFIDTIDX);
2284 
2285     ocelot_write(ocelot,
2286              ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
2287              ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
2288              ANA_TABLES_SFID_MASK);
2289 
2290     ocelot_rmw(ocelot,
2291            ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
2292            ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
2293            ANA_TABLES_SFIDACCESS);
2294 
2295     return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
2296                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
2297                   10, 100000);
2298 }
2299 
2300 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
2301                      struct felix_stream_filter *sfi,
2302                      struct list_head *pos)
2303 {
2304     struct felix_stream_filter *sfi_entry;
2305     int ret;
2306 
2307     sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
2308     if (!sfi_entry)
2309         return -ENOMEM;
2310 
2311     refcount_set(&sfi_entry->refcount, 1);
2312 
2313     ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
2314     if (ret) {
2315         kfree(sfi_entry);
2316         return ret;
2317     }
2318 
2319     vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
2320 
2321     list_add(&sfi_entry->list, pos);
2322 
2323     return 0;
2324 }
2325 
2326 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
2327                       struct felix_stream_filter *sfi)
2328 {
2329     struct list_head *pos, *q, *last;
2330     struct felix_stream_filter *tmp;
2331     struct ocelot_psfp_list *psfp;
2332     u32 insert = 0;
2333 
2334     psfp = &ocelot->psfp;
2335     last = &psfp->sfi_list;
2336 
2337     list_for_each_safe(pos, q, &psfp->sfi_list) {
2338         tmp = list_entry(pos, struct felix_stream_filter, list);
2339         if (sfi->sg_valid == tmp->sg_valid &&
2340             sfi->fm_valid == tmp->fm_valid &&
2341             sfi->portmask == tmp->portmask &&
2342             tmp->sgid == sfi->sgid &&
2343             tmp->fmid == sfi->fmid) {
2344             sfi->index = tmp->index;
2345             refcount_inc(&tmp->refcount);
2346             return 0;
2347         }
2348         /* Make sure that the index is increasing in order. */
2349         if (tmp->index == insert) {
2350             last = pos;
2351             insert++;
2352         }
2353     }
2354     sfi->index = insert;
2355 
2356     return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2357 }
2358 
2359 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
2360                        struct felix_stream_filter *sfi,
2361                        struct felix_stream_filter *sfi2)
2362 {
2363     struct felix_stream_filter *tmp;
2364     struct list_head *pos, *q, *last;
2365     struct ocelot_psfp_list *psfp;
2366     u32 insert = 0;
2367     int ret;
2368 
2369     psfp = &ocelot->psfp;
2370     last = &psfp->sfi_list;
2371 
2372     list_for_each_safe(pos, q, &psfp->sfi_list) {
2373         tmp = list_entry(pos, struct felix_stream_filter, list);
2374         /* Make sure that the index is increasing in order. */
2375         if (tmp->index >= insert + 2)
2376             break;
2377 
2378         insert = tmp->index + 1;
2379         last = pos;
2380     }
2381     sfi->index = insert;
2382 
2383     ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2384     if (ret)
2385         return ret;
2386 
2387     sfi2->index = insert + 1;
2388 
2389     return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
2390 }
2391 
2392 static struct felix_stream_filter *
2393 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
2394 {
2395     struct felix_stream_filter *tmp;
2396 
2397     list_for_each_entry(tmp, sfi_list, list)
2398         if (tmp->index == index)
2399             return tmp;
2400 
2401     return NULL;
2402 }
2403 
2404 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
2405 {
2406     struct felix_stream_filter *tmp, *n;
2407     struct ocelot_psfp_list *psfp;
2408     u8 z;
2409 
2410     psfp = &ocelot->psfp;
2411 
2412     list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
2413         if (tmp->index == index) {
2414             z = refcount_dec_and_test(&tmp->refcount);
2415             if (z) {
2416                 tmp->enable = 0;
2417                 vsc9959_psfp_sfi_set(ocelot, tmp);
2418                 list_del(&tmp->list);
2419                 kfree(tmp);
2420             }
2421             break;
2422         }
2423 }
2424 
2425 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
2426                     struct felix_stream_gate *sgi)
2427 {
2428     sgi->index = entry->hw_index;
2429     sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
2430     sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
2431     sgi->basetime = entry->gate.basetime;
2432     sgi->cycletime = entry->gate.cycletime;
2433     sgi->num_entries = entry->gate.num_entries;
2434     sgi->enable = 1;
2435 
2436     memcpy(sgi->entries, entry->gate.entries,
2437            entry->gate.num_entries * sizeof(struct action_gate_entry));
2438 }
2439 
2440 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
2441 {
2442     return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
2443 }
2444 
2445 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
2446                 struct felix_stream_gate *sgi)
2447 {
2448     struct action_gate_entry *e;
2449     struct timespec64 base_ts;
2450     u32 interval_sum = 0;
2451     u32 val;
2452     int i;
2453 
2454     if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
2455         return -EINVAL;
2456 
2457     ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
2458              ANA_SG_ACCESS_CTRL);
2459 
2460     if (!sgi->enable) {
2461         ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
2462                ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2463                ANA_SG_CONFIG_REG_3_GATE_ENABLE,
2464                ANA_SG_CONFIG_REG_3);
2465 
2466         return 0;
2467     }
2468 
2469     if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
2470         sgi->cycletime > NSEC_PER_SEC)
2471         return -EINVAL;
2472 
2473     if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
2474         return -EINVAL;
2475 
2476     vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
2477     ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
2478     val = lower_32_bits(base_ts.tv_sec);
2479     ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
2480 
2481     val = upper_32_bits(base_ts.tv_sec);
2482     ocelot_write(ocelot,
2483              (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
2484              ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
2485              ANA_SG_CONFIG_REG_3_GATE_ENABLE |
2486              ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
2487              ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2488              ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
2489              ANA_SG_CONFIG_REG_3);
2490 
2491     ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
2492 
2493     e = sgi->entries;
2494     for (i = 0; i < sgi->num_entries; i++) {
2495         u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
2496 
2497         ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
2498                  (e[i].gate_state ?
2499                   ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
2500                  ANA_SG_GCL_GS_CONFIG, i);
2501 
2502         interval_sum += e[i].interval;
2503         ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
2504     }
2505 
2506     ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2507            ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2508            ANA_SG_ACCESS_CTRL);
2509 
2510     return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
2511                   (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
2512                   10, 100000);
2513 }
2514 
2515 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
2516                       struct felix_stream_gate *sgi)
2517 {
2518     struct felix_stream_gate_entry *tmp;
2519     struct ocelot_psfp_list *psfp;
2520     int ret;
2521 
2522     psfp = &ocelot->psfp;
2523 
2524     list_for_each_entry(tmp, &psfp->sgi_list, list)
2525         if (tmp->index == sgi->index) {
2526             refcount_inc(&tmp->refcount);
2527             return 0;
2528         }
2529 
2530     tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2531     if (!tmp)
2532         return -ENOMEM;
2533 
2534     ret = vsc9959_psfp_sgi_set(ocelot, sgi);
2535     if (ret) {
2536         kfree(tmp);
2537         return ret;
2538     }
2539 
2540     tmp->index = sgi->index;
2541     refcount_set(&tmp->refcount, 1);
2542     list_add_tail(&tmp->list, &psfp->sgi_list);
2543 
2544     return 0;
2545 }
2546 
2547 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
2548                        u32 index)
2549 {
2550     struct felix_stream_gate_entry *tmp, *n;
2551     struct felix_stream_gate sgi = {0};
2552     struct ocelot_psfp_list *psfp;
2553     u8 z;
2554 
2555     psfp = &ocelot->psfp;
2556 
2557     list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
2558         if (tmp->index == index) {
2559             z = refcount_dec_and_test(&tmp->refcount);
2560             if (z) {
2561                 sgi.index = index;
2562                 sgi.enable = 0;
2563                 vsc9959_psfp_sgi_set(ocelot, &sgi);
2564                 list_del(&tmp->list);
2565                 kfree(tmp);
2566             }
2567             break;
2568         }
2569 }
2570 
2571 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
2572                       struct felix_stream_filter_counters *counters)
2573 {
2574     spin_lock(&ocelot->stats_lock);
2575 
2576     ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
2577            SYS_STAT_CFG_STAT_VIEW_M,
2578            SYS_STAT_CFG);
2579 
2580     counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200);
2581     counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201);
2582     counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202);
2583     counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203);
2584 
2585     /* Clear the PSFP counter. */
2586     ocelot_write(ocelot,
2587              SYS_STAT_CFG_STAT_VIEW(index) |
2588              SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
2589              SYS_STAT_CFG);
2590 
2591     spin_unlock(&ocelot->stats_lock);
2592 }
2593 
2594 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
2595                    struct flow_cls_offload *f)
2596 {
2597     struct netlink_ext_ack *extack = f->common.extack;
2598     struct felix_stream_filter old_sfi, *sfi_entry;
2599     struct felix_stream_filter sfi = {0};
2600     const struct flow_action_entry *a;
2601     struct felix_stream *stream_entry;
2602     struct felix_stream stream = {0};
2603     struct felix_stream_gate *sgi;
2604     struct ocelot_psfp_list *psfp;
2605     struct ocelot_policer pol;
2606     int ret, i, size;
2607     u64 rate, burst;
2608     u32 index;
2609 
2610     psfp = &ocelot->psfp;
2611 
2612     ret = vsc9959_stream_identify(f, &stream);
2613     if (ret) {
2614         NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
2615         return ret;
2616     }
2617 
2618     flow_action_for_each(i, a, &f->rule->action) {
2619         switch (a->id) {
2620         case FLOW_ACTION_GATE:
2621             size = struct_size(sgi, entries, a->gate.num_entries);
2622             sgi = kzalloc(size, GFP_KERNEL);
2623             if (!sgi) {
2624                 ret = -ENOMEM;
2625                 goto err;
2626             }
2627             vsc9959_psfp_parse_gate(a, sgi);
2628             ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
2629             if (ret) {
2630                 kfree(sgi);
2631                 goto err;
2632             }
2633             sfi.sg_valid = 1;
2634             sfi.sgid = sgi->index;
2635             kfree(sgi);
2636             break;
2637         case FLOW_ACTION_POLICE:
2638             index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
2639             if (index > VSC9959_PSFP_POLICER_MAX) {
2640                 ret = -EINVAL;
2641                 goto err;
2642             }
2643 
2644             rate = a->police.rate_bytes_ps;
2645             burst = rate * PSCHED_NS2TICKS(a->police.burst);
2646             pol = (struct ocelot_policer) {
2647                 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
2648                 .rate = div_u64(rate, 1000) * 8,
2649             };
2650             ret = ocelot_vcap_policer_add(ocelot, index, &pol);
2651             if (ret)
2652                 goto err;
2653 
2654             sfi.fm_valid = 1;
2655             sfi.fmid = index;
2656             sfi.maxsdu = a->police.mtu;
2657             break;
2658         default:
2659             return -EOPNOTSUPP;
2660         }
2661     }
2662 
2663     stream.ports = BIT(port);
2664     stream.port = port;
2665 
2666     sfi.portmask = stream.ports;
2667     sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
2668     sfi.prio = (sfi.prio_valid ? stream.prio : 0);
2669     sfi.enable = 1;
2670 
2671     /* Check if stream is set. */
2672     stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
2673     if (stream_entry) {
2674         if (stream_entry->ports & BIT(port)) {
2675             NL_SET_ERR_MSG_MOD(extack,
2676                        "The stream is added on this port");
2677             ret = -EEXIST;
2678             goto err;
2679         }
2680 
2681         if (stream_entry->ports != BIT(stream_entry->port)) {
2682             NL_SET_ERR_MSG_MOD(extack,
2683                        "The stream is added on two ports");
2684             ret = -EEXIST;
2685             goto err;
2686         }
2687 
2688         stream_entry->ports |= BIT(port);
2689         stream.ports = stream_entry->ports;
2690 
2691         sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2692                                stream_entry->sfid);
2693         memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2694 
2695         vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2696 
2697         old_sfi.portmask = stream_entry->ports;
2698         sfi.portmask = stream.ports;
2699 
2700         if (stream_entry->port > port) {
2701             ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2702                               &old_sfi);
2703             stream_entry->dummy = true;
2704         } else {
2705             ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2706                               &sfi);
2707             stream.dummy = true;
2708         }
2709         if (ret)
2710             goto err;
2711 
2712         stream_entry->sfid = old_sfi.index;
2713     } else {
2714         ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2715         if (ret)
2716             goto err;
2717     }
2718 
2719     stream.sfid = sfi.index;
2720     stream.sfid_valid = 1;
2721     ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2722                        &stream, extack);
2723     if (ret) {
2724         vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2725         goto err;
2726     }
2727 
2728     return 0;
2729 
2730 err:
2731     if (sfi.sg_valid)
2732         vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2733 
2734     if (sfi.fm_valid)
2735         ocelot_vcap_policer_del(ocelot, sfi.fmid);
2736 
2737     return ret;
2738 }
2739 
2740 static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2741                    struct flow_cls_offload *f)
2742 {
2743     struct felix_stream *stream, tmp, *stream_entry;
2744     static struct felix_stream_filter *sfi;
2745     struct ocelot_psfp_list *psfp;
2746 
2747     psfp = &ocelot->psfp;
2748 
2749     stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2750     if (!stream)
2751         return -ENOMEM;
2752 
2753     sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2754     if (!sfi)
2755         return -ENOMEM;
2756 
2757     if (sfi->sg_valid)
2758         vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2759 
2760     if (sfi->fm_valid)
2761         ocelot_vcap_policer_del(ocelot, sfi->fmid);
2762 
2763     vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2764 
2765     memcpy(&tmp, stream, sizeof(tmp));
2766 
2767     stream->sfid_valid = 0;
2768     vsc9959_stream_table_del(ocelot, stream);
2769 
2770     stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2771     if (stream_entry) {
2772         stream_entry->ports = BIT(stream_entry->port);
2773         if (stream_entry->dummy) {
2774             stream_entry->dummy = false;
2775             vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2776         }
2777         vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2778                       stream_entry->ports);
2779     }
2780 
2781     return 0;
2782 }
2783 
2784 static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2785                   struct flow_cls_offload *f,
2786                   struct flow_stats *stats)
2787 {
2788     struct felix_stream_filter_counters counters;
2789     struct ocelot_psfp_list *psfp;
2790     struct felix_stream *stream;
2791 
2792     psfp = &ocelot->psfp;
2793     stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2794     if (!stream)
2795         return -ENOMEM;
2796 
2797     vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters);
2798 
2799     stats->pkts = counters.match;
2800     stats->drops = counters.not_pass_gate + counters.not_pass_sdu +
2801                counters.red;
2802 
2803     return 0;
2804 }
2805 
2806 static void vsc9959_psfp_init(struct ocelot *ocelot)
2807 {
2808     struct ocelot_psfp_list *psfp = &ocelot->psfp;
2809 
2810     INIT_LIST_HEAD(&psfp->stream_list);
2811     INIT_LIST_HEAD(&psfp->sfi_list);
2812     INIT_LIST_HEAD(&psfp->sgi_list);
2813 }
2814 
2815 /* When using cut-through forwarding and the egress port runs at a higher data
2816  * rate than the ingress port, the packet currently under transmission would
2817  * suffer an underrun since it would be transmitted faster than it is received.
2818  * The Felix switch implementation of cut-through forwarding does not check in
2819  * hardware whether this condition is satisfied or not, so we must restrict the
2820  * list of ports that have cut-through forwarding enabled on egress to only be
2821  * the ports operating at the lowest link speed within their respective
2822  * forwarding domain.
2823  */
2824 static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2825 {
2826     struct felix *felix = ocelot_to_felix(ocelot);
2827     struct dsa_switch *ds = felix->ds;
2828     int tc, port, other_port;
2829 
2830     lockdep_assert_held(&ocelot->fwd_domain_lock);
2831 
2832     for (port = 0; port < ocelot->num_phys_ports; port++) {
2833         struct ocelot_port *ocelot_port = ocelot->ports[port];
2834         int min_speed = ocelot_port->speed;
2835         unsigned long mask = 0;
2836         u32 tmp, val = 0;
2837 
2838         /* Disable cut-through on ports that are down */
2839         if (ocelot_port->speed <= 0)
2840             goto set;
2841 
2842         if (dsa_is_cpu_port(ds, port)) {
2843             /* Ocelot switches forward from the NPI port towards
2844              * any port, regardless of it being in the NPI port's
2845              * forwarding domain or not.
2846              */
2847             mask = dsa_user_ports(ds);
2848         } else {
2849             mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2850             mask &= ~BIT(port);
2851             if (ocelot->npi >= 0)
2852                 mask |= BIT(ocelot->npi);
2853             else
2854                 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
2855                                         port);
2856         }
2857 
2858         /* Calculate the minimum link speed, among the ports that are
2859          * up, of this source port's forwarding domain.
2860          */
2861         for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2862             struct ocelot_port *other_ocelot_port;
2863 
2864             other_ocelot_port = ocelot->ports[other_port];
2865             if (other_ocelot_port->speed <= 0)
2866                 continue;
2867 
2868             if (min_speed > other_ocelot_port->speed)
2869                 min_speed = other_ocelot_port->speed;
2870         }
2871 
2872         /* Enable cut-through forwarding for all traffic classes that
2873          * don't have oversized dropping enabled, since this check is
2874          * bypassed in cut-through mode.
2875          */
2876         if (ocelot_port->speed == min_speed) {
2877             val = GENMASK(7, 0);
2878 
2879             for (tc = 0; tc < OCELOT_NUM_TC; tc++)
2880                 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc))
2881                     val &= ~BIT(tc);
2882         }
2883 
2884 set:
2885         tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2886         if (tmp == val)
2887             continue;
2888 
2889         dev_dbg(ocelot->dev,
2890             "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n",
2891             port, mask, ocelot_port->speed, min_speed,
2892             val ? "enabling" : "disabling", val);
2893 
2894         ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2895     }
2896 }
2897 
2898 static const struct ocelot_ops vsc9959_ops = {
2899     .reset          = vsc9959_reset,
2900     .wm_enc         = vsc9959_wm_enc,
2901     .wm_dec         = vsc9959_wm_dec,
2902     .wm_stat        = vsc9959_wm_stat,
2903     .port_to_netdev     = felix_port_to_netdev,
2904     .netdev_to_port     = felix_netdev_to_port,
2905     .psfp_init      = vsc9959_psfp_init,
2906     .psfp_filter_add    = vsc9959_psfp_filter_add,
2907     .psfp_filter_del    = vsc9959_psfp_filter_del,
2908     .psfp_stats_get     = vsc9959_psfp_stats_get,
2909     .cut_through_fwd    = vsc9959_cut_through_fwd,
2910     .tas_clock_adjust   = vsc9959_tas_clock_adjust,
2911 };
2912 
2913 static const struct felix_info felix_info_vsc9959 = {
2914     .target_io_res      = vsc9959_target_io_res,
2915     .port_io_res        = vsc9959_port_io_res,
2916     .imdio_res      = &vsc9959_imdio_res,
2917     .regfields      = vsc9959_regfields,
2918     .map            = vsc9959_regmap,
2919     .ops            = &vsc9959_ops,
2920     .stats_layout       = vsc9959_stats_layout,
2921     .vcap           = vsc9959_vcap_props,
2922     .vcap_pol_base      = VSC9959_VCAP_POLICER_BASE,
2923     .vcap_pol_max       = VSC9959_VCAP_POLICER_MAX,
2924     .vcap_pol_base2     = 0,
2925     .vcap_pol_max2      = 0,
2926     .num_mact_rows      = 2048,
2927     .num_ports      = VSC9959_NUM_PORTS,
2928     .num_tx_queues      = OCELOT_NUM_TC,
2929     .quirk_no_xtr_irq   = true,
2930     .ptp_caps       = &vsc9959_ptp_caps,
2931     .mdio_bus_alloc     = vsc9959_mdio_bus_alloc,
2932     .mdio_bus_free      = vsc9959_mdio_bus_free,
2933     .phylink_validate   = vsc9959_phylink_validate,
2934     .port_modes     = vsc9959_port_modes,
2935     .port_setup_tc      = vsc9959_port_setup_tc,
2936     .port_sched_speed_set   = vsc9959_sched_speed_set,
2937     .tas_guard_bands_update = vsc9959_tas_guard_bands_update,
2938     .init_regmap        = ocelot_regmap_init,
2939 };
2940 
2941 static irqreturn_t felix_irq_handler(int irq, void *data)
2942 {
2943     struct ocelot *ocelot = (struct ocelot *)data;
2944 
2945     /* The INTB interrupt is used for both PTP TX timestamp interrupt
2946      * and preemption status change interrupt on each port.
2947      *
2948      * - Get txtstamp if have
2949      * - TODO: handle preemption. Without handling it, driver may get
2950      *   interrupt storm.
2951      */
2952 
2953     ocelot_get_txtstamp(ocelot);
2954 
2955     return IRQ_HANDLED;
2956 }
2957 
2958 static int felix_pci_probe(struct pci_dev *pdev,
2959                const struct pci_device_id *id)
2960 {
2961     struct dsa_switch *ds;
2962     struct ocelot *ocelot;
2963     struct felix *felix;
2964     int err;
2965 
2966     if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2967         dev_info(&pdev->dev, "device is disabled, skipping\n");
2968         return -ENODEV;
2969     }
2970 
2971     err = pci_enable_device(pdev);
2972     if (err) {
2973         dev_err(&pdev->dev, "device enable failed\n");
2974         goto err_pci_enable;
2975     }
2976 
2977     felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2978     if (!felix) {
2979         err = -ENOMEM;
2980         dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2981         goto err_alloc_felix;
2982     }
2983 
2984     pci_set_drvdata(pdev, felix);
2985     ocelot = &felix->ocelot;
2986     ocelot->dev = &pdev->dev;
2987     ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2988     felix->info = &felix_info_vsc9959;
2989     felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2990     felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
2991 
2992     pci_set_master(pdev);
2993 
2994     err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2995                     &felix_irq_handler, IRQF_ONESHOT,
2996                     "felix-intb", ocelot);
2997     if (err) {
2998         dev_err(&pdev->dev, "Failed to request irq\n");
2999         goto err_alloc_irq;
3000     }
3001 
3002     ocelot->ptp = 1;
3003 
3004     ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
3005     if (!ds) {
3006         err = -ENOMEM;
3007         dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
3008         goto err_alloc_ds;
3009     }
3010 
3011     ds->dev = &pdev->dev;
3012     ds->num_ports = felix->info->num_ports;
3013     ds->num_tx_queues = felix->info->num_tx_queues;
3014     ds->ops = &felix_switch_ops;
3015     ds->priv = ocelot;
3016     felix->ds = ds;
3017     felix->tag_proto = DSA_TAG_PROTO_OCELOT;
3018 
3019     err = dsa_register_switch(ds);
3020     if (err) {
3021         dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n");
3022         goto err_register_ds;
3023     }
3024 
3025     return 0;
3026 
3027 err_register_ds:
3028     kfree(ds);
3029 err_alloc_ds:
3030 err_alloc_irq:
3031     kfree(felix);
3032 err_alloc_felix:
3033     pci_disable_device(pdev);
3034 err_pci_enable:
3035     return err;
3036 }
3037 
3038 static void felix_pci_remove(struct pci_dev *pdev)
3039 {
3040     struct felix *felix = pci_get_drvdata(pdev);
3041 
3042     if (!felix)
3043         return;
3044 
3045     dsa_unregister_switch(felix->ds);
3046 
3047     kfree(felix->ds);
3048     kfree(felix);
3049 
3050     pci_disable_device(pdev);
3051 
3052     pci_set_drvdata(pdev, NULL);
3053 }
3054 
3055 static void felix_pci_shutdown(struct pci_dev *pdev)
3056 {
3057     struct felix *felix = pci_get_drvdata(pdev);
3058 
3059     if (!felix)
3060         return;
3061 
3062     dsa_switch_shutdown(felix->ds);
3063 
3064     pci_set_drvdata(pdev, NULL);
3065 }
3066 
3067 static struct pci_device_id felix_ids[] = {
3068     {
3069         /* NXP LS1028A */
3070         PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
3071     },
3072     { 0, }
3073 };
3074 MODULE_DEVICE_TABLE(pci, felix_ids);
3075 
3076 static struct pci_driver felix_vsc9959_pci_driver = {
3077     .name       = "mscc_felix",
3078     .id_table   = felix_ids,
3079     .probe      = felix_pci_probe,
3080     .remove     = felix_pci_remove,
3081     .shutdown   = felix_pci_shutdown,
3082 };
3083 module_pci_driver(felix_vsc9959_pci_driver);
3084 
3085 MODULE_DESCRIPTION("Felix Switch driver");
3086 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!