dsa/mv88e6xxx/smi.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx System Management Interface (SMI) support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
0008  */
0009
0010 #ifndef _MV88E6XXX_SMI_H
0011 #define _MV88E6XXX_SMI_H
0012
0013 #include "chip.h"
0014
0015 /* Offset 0x00: SMI Command Register */
0016 #define MV88E6XXX_SMI_CMD           0x00
0017 #define MV88E6XXX_SMI_CMD_BUSY          0x8000
0018 #define MV88E6XXX_SMI_CMD_MODE_MASK     0x1000
0019 #define MV88E6XXX_SMI_CMD_MODE_45       0x0000
0020 #define MV88E6XXX_SMI_CMD_MODE_22       0x1000
0021 #define MV88E6XXX_SMI_CMD_OP_MASK       0x0c00
0022 #define MV88E6XXX_SMI_CMD_OP_22_WRITE       0x0400
0023 #define MV88E6XXX_SMI_CMD_OP_22_READ        0x0800
0024 #define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR  0x0000
0025 #define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA  0x0400
0026 #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA   0x0800
0027 #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC   0x0c00
0028 #define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK     0x003e
0029 #define MV88E6XXX_SMI_CMD_REG_ADDR_MASK     0x001f
0030
0031 /* Offset 0x01: SMI Data Register */
0032 #define MV88E6XXX_SMI_DATA          0x01
0033
0034 int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
0035                struct mii_bus *bus, int sw_addr);
0036
0037 static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
0038                      int dev, int reg, u16 *data)
0039 {
0040     if (chip->smi_ops && chip->smi_ops->read)
0041         return chip->smi_ops->read(chip, dev, reg, data);
0042
0043     return -EOPNOTSUPP;
0044 }
0045
0046 static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
0047                       int dev, int reg, u16 data)
0048 {
0049     if (chip->smi_ops && chip->smi_ops->write)
0050         return chip->smi_ops->write(chip, dev, reg, data);
0051
0052     return -EOPNOTSUPP;
0053 }
0054
0055 #endif /* _MV88E6XXX_SMI_H */