dsa/mv88e6xxx/serdes.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx SERDES manipulation, via SMI bus
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
0008  */
0009
0010 #ifndef _MV88E6XXX_SERDES_H
0011 #define _MV88E6XXX_SERDES_H
0012
0013 #include "chip.h"
0014
0015 #define MV88E6352_ADDR_SERDES       0x0f
0016 #define MV88E6352_SERDES_PAGE_FIBER 0x01
0017 #define MV88E6352_SERDES_IRQ        0x0b
0018 #define MV88E6352_SERDES_INT_ENABLE 0x12
0019 #define MV88E6352_SERDES_INT_SPEED_CHANGE   BIT(14)
0020 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE  BIT(13)
0021 #define MV88E6352_SERDES_INT_PAGE_RX        BIT(12)
0022 #define MV88E6352_SERDES_INT_AN_COMPLETE    BIT(11)
0023 #define MV88E6352_SERDES_INT_LINK_CHANGE    BIT(10)
0024 #define MV88E6352_SERDES_INT_SYMBOL_ERROR   BIT(9)
0025 #define MV88E6352_SERDES_INT_FALSE_CARRIER  BIT(8)
0026 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER    BIT(7)
0027 #define MV88E6352_SERDES_INT_FIBRE_ENERGY   BIT(4)
0028 #define MV88E6352_SERDES_INT_STATUS 0x13
0029
0030 #define MV88E6352_SERDES_SPEC_CTRL2 0x1a
0031 #define MV88E6352_SERDES_OUT_AMP_MASK       0x0007
0032
0033 #define MV88E6341_PORT5_LANE        0x15
0034
0035 #define MV88E6390_PORT9_LANE0       0x09
0036 #define MV88E6390_PORT9_LANE1       0x12
0037 #define MV88E6390_PORT9_LANE2       0x13
0038 #define MV88E6390_PORT9_LANE3       0x14
0039 #define MV88E6390_PORT10_LANE0      0x0a
0040 #define MV88E6390_PORT10_LANE1      0x15
0041 #define MV88E6390_PORT10_LANE2      0x16
0042 #define MV88E6390_PORT10_LANE3      0x17
0043
0044 /* 10GBASE-R and 10GBASE-X4/X2 */
0045 #define MV88E6390_10G_CTRL1     (0x1000 + MDIO_CTRL1)
0046 #define MV88E6390_10G_STAT1     (0x1000 + MDIO_STAT1)
0047 #define MV88E6393X_10G_INT_ENABLE   0x9000
0048 #define MV88E6393X_10G_INT_LINK_CHANGE  BIT(2)
0049 #define MV88E6393X_10G_INT_STATUS   0x9001
0050
0051 /* 1000BASE-X and SGMII */
0052 #define MV88E6390_SGMII_BMCR        (0x2000 + MII_BMCR)
0053 #define MV88E6390_SGMII_BMSR        (0x2000 + MII_BMSR)
0054 #define MV88E6390_SGMII_ADVERTISE   (0x2000 + MII_ADVERTISE)
0055 #define MV88E6390_SGMII_LPA     (0x2000 + MII_LPA)
0056 #define MV88E6390_SGMII_INT_ENABLE  0xa001
0057 #define MV88E6390_SGMII_INT_SPEED_CHANGE    BIT(14)
0058 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE   BIT(13)
0059 #define MV88E6390_SGMII_INT_PAGE_RX     BIT(12)
0060 #define MV88E6390_SGMII_INT_AN_COMPLETE     BIT(11)
0061 #define MV88E6390_SGMII_INT_LINK_DOWN       BIT(10)
0062 #define MV88E6390_SGMII_INT_LINK_UP     BIT(9)
0063 #define MV88E6390_SGMII_INT_SYMBOL_ERROR    BIT(8)
0064 #define MV88E6390_SGMII_INT_FALSE_CARRIER   BIT(7)
0065 #define MV88E6390_SGMII_INT_STATUS  0xa002
0066 #define MV88E6390_SGMII_PHY_STATUS  0xa003
0067 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK   GENMASK(15, 14)
0068 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000   0x8000
0069 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100    0x4000
0070 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
0071 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL  BIT(13)
0072 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
0073 #define MV88E6390_SGMII_PHY_STATUS_LINK     BIT(10)
0074 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3)
0075 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
0076
0077 /* Packet generator pad packet checker */
0078 #define MV88E6390_PG_CONTROL        0xf010
0079 #define MV88E6390_PG_CONTROL_ENABLE_PC      BIT(0)
0080
0081 #define MV88E6393X_PORT0_LANE           0x00
0082 #define MV88E6393X_PORT9_LANE           0x09
0083 #define MV88E6393X_PORT10_LANE          0x0a
0084
0085 /* Port Operational Configuration */
0086 #define MV88E6393X_SERDES_POC           0xf002
0087 #define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000
0088 #define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001
0089 #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002
0090 #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003
0091 #define MV88E6393X_SERDES_POC_PCS_5GBASER   0x0004
0092 #define MV88E6393X_SERDES_POC_PCS_10GBASER  0x0005
0093 #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY   0x0006
0094 #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC   0x0007
0095 #define MV88E6393X_SERDES_POC_PCS_MASK      0x0007
0096 #define MV88E6393X_SERDES_POC_RESET     BIT(15)
0097 #define MV88E6393X_SERDES_POC_PDOWN     BIT(5)
0098 #define MV88E6393X_SERDES_POC_AN        BIT(3)
0099 #define MV88E6393X_SERDES_CTRL1         0xf003
0100 #define MV88E6393X_SERDES_CTRL1_TX_PDOWN    BIT(9)
0101 #define MV88E6393X_SERDES_CTRL1_RX_PDOWN    BIT(8)
0102
0103 #define MV88E6393X_ERRATA_4_8_REG       0xF074
0104 #define MV88E6393X_ERRATA_4_8_BIT       BIT(14)
0105
0106 int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0107 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0108 int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0109 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0110 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0111 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
0112 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
0113                 int lane, unsigned int mode,
0114                 phy_interface_t interface,
0115                 const unsigned long *advertise);
0116 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
0117                 int lane, unsigned int mode,
0118                 phy_interface_t interface,
0119                 const unsigned long *advertise);
0120 int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
0121                    int lane, struct phylink_link_state *state);
0122 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
0123                    int lane, struct phylink_link_state *state);
0124 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
0125                    int lane, struct phylink_link_state *state);
0126 int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
0127                     int lane, struct phylink_link_state *state);
0128 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
0129                     int lane);
0130 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
0131                     int lane);
0132 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
0133                  int lane, int speed, int duplex);
0134 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
0135                  int lane, int speed, int duplex);
0136 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
0137                       int port);
0138 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
0139                       int port);
0140 int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
0141                bool up);
0142 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
0143                bool on);
0144 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
0145                bool on);
0146 int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
0147                 bool on);
0148 int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip);
0149 int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
0150                 bool enable);
0151 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
0152                 bool enable);
0153 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
0154                 bool enable);
0155 int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
0156                  int lane, bool enable);
0157 irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
0158                     int lane);
0159 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
0160                     int lane);
0161 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
0162                     int lane);
0163 irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
0164                      int lane);
0165 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
0166 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
0167                  int port, uint8_t *data);
0168 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
0169                    uint64_t *data);
0170 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
0171 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
0172                  int port, uint8_t *data);
0173 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
0174                    uint64_t *data);
0175
0176 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
0177 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
0178 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
0179 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
0180
0181 int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
0182                       int val);
0183
0184 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
0185 static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
0186                         int port)
0187 {
0188     if (!chip->info->ops->serdes_get_lane)
0189         return -EOPNOTSUPP;
0190
0191     return chip->info->ops->serdes_get_lane(chip, port);
0192 }
0193
0194 static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
0195                         int port, int lane)
0196 {
0197     if (!chip->info->ops->serdes_power)
0198         return -EOPNOTSUPP;
0199
0200     return chip->info->ops->serdes_power(chip, port, lane, true);
0201 }
0202
0203 static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
0204                           int port, int lane)
0205 {
0206     if (!chip->info->ops->serdes_power)
0207         return -EOPNOTSUPP;
0208
0209     return chip->info->ops->serdes_power(chip, port, lane, false);
0210 }
0211
0212 static inline unsigned int
0213 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
0214 {
0215     if (!chip->info->ops->serdes_irq_mapping)
0216         return 0;
0217
0218     return chip->info->ops->serdes_irq_mapping(chip, port);
0219 }
0220
0221 static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
0222                           int port, int lane)
0223 {
0224     if (!chip->info->ops->serdes_irq_enable)
0225         return -EOPNOTSUPP;
0226
0227     return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
0228 }
0229
0230 static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
0231                            int port, int lane)
0232 {
0233     if (!chip->info->ops->serdes_irq_enable)
0234         return -EOPNOTSUPP;
0235
0236     return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
0237 }
0238
0239 static inline irqreturn_t
0240 mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane)
0241 {
0242     if (!chip->info->ops->serdes_irq_status)
0243         return IRQ_NONE;
0244
0245     return chip->info->ops->serdes_irq_status(chip, port, lane);
0246 }
0247
0248 #endif