dsa/mv88e6xxx/ptp.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx Switch PTP support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2017 National Instruments
0008  *      Erik Hons <erik.hons@ni.com>
0009  *      Brandon Streiff <brandon.streiff@ni.com>
0010  *      Dane Wagner <dane.wagner@ni.com>
0011  */
0012
0013 #ifndef _MV88E6XXX_PTP_H
0014 #define _MV88E6XXX_PTP_H
0015
0016 #include "chip.h"
0017
0018 /* Offset 0x00: TAI Global Config */
0019 #define MV88E6XXX_TAI_CFG           0x00
0020 #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE     0x8000
0021 #define MV88E6XXX_TAI_CFG_CAP_CTR_START     0x4000
0022 #define MV88E6XXX_TAI_CFG_EVREQ_FALLING     0x2000
0023 #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO    0x1000
0024 #define MV88E6XXX_TAI_CFG_IRL_ENABLE        0x0400
0025 #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN       0x0200
0026 #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN      0x0100
0027 #define MV88E6XXX_TAI_CFG_TRIG_LOCK     0x0080
0028 #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE      0x0008
0029 #define MV88E6XXX_TAI_CFG_MULTI_PTP     0x0004
0030 #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002
0031 #define MV88E6XXX_TAI_CFG_TRIG_ENABLE       0x0001
0032
0033 /* Offset 0x01: Timestamp Clock Period (ps) */
0034 #define MV88E6XXX_TAI_CLOCK_PERIOD      0x01
0035
0036 /* Offset 0x02/0x03: Trigger Generation Amount */
0037 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO    0x02
0038 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI    0x03
0039
0040 /* Offset 0x04: Clock Compensation */
0041 #define MV88E6XXX_TAI_TRIG_CLOCK_COMP       0x04
0042
0043 /* Offset 0x05: Trigger Configuration */
0044 #define MV88E6XXX_TAI_TRIG_CFG          0x05
0045
0046 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
0047 #define MV88E6XXX_TAI_IRL_AMOUNT        0x06
0048
0049 /* Offset 0x07: Ingress Rate Limiter Compensation */
0050 #define MV88E6XXX_TAI_IRL_COMP          0x07
0051
0052 /* Offset 0x08: Ingress Rate Limiter Compensation */
0053 #define MV88E6XXX_TAI_IRL_COMP_PS       0x08
0054
0055 /* Offset 0x09: Event Status */
0056 #define MV88E6XXX_TAI_EVENT_STATUS      0x09
0057 #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000
0058 #define MV88E6XXX_TAI_EVENT_STATUS_ERROR    0x0200
0059 #define MV88E6XXX_TAI_EVENT_STATUS_VALID    0x0100
0060 #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff
0061
0062 /* Offset 0x0A/0x0B: Event Time */
0063 #define MV88E6XXX_TAI_EVENT_TIME_LO     0x0a
0064 #define MV88E6XXX_TAI_EVENT_TYPE_HI     0x0b
0065
0066 /* Offset 0x0E/0x0F: PTP Global Time */
0067 #define MV88E6XXX_TAI_TIME_LO           0x0e
0068 #define MV88E6XXX_TAI_TIME_HI           0x0f
0069
0070 /* Offset 0x10/0x11: Trig Generation Time */
0071 #define MV88E6XXX_TAI_TRIG_TIME_LO      0x10
0072 #define MV88E6XXX_TAI_TRIG_TIME_HI      0x11
0073
0074 /* Offset 0x12: Lock Status */
0075 #define MV88E6XXX_TAI_LOCK_STATUS       0x12
0076
0077 /* Offset 0x00: Ether Type */
0078 #define MV88E6XXX_PTP_GC_ETYPE          0x00
0079
0080 /* 6165 Global Control Registers */
0081 /* Offset 0x00: Ether Type */
0082 #define MV88E6XXX_PTP_GC_ETYPE          0x00
0083
0084 /* Offset 0x01: Message ID */
0085 #define MV88E6XXX_PTP_GC_MESSAGE_ID     0x01
0086
0087 /* Offset 0x02: Time Stamp Arrive Time */
0088 #define MV88E6XXX_PTP_GC_TS_ARR_PTR     0x02
0089
0090 /* Offset 0x03: Port Arrival Interrupt Enable */
0091 #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN    0x03
0092
0093 /* Offset 0x04: Port Departure Interrupt Enable */
0094 #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN    0x04
0095
0096 /* Offset 0x05: Configuration */
0097 #define MV88E6XXX_PTP_GC_CONFIG         0x05
0098 #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE   BIT(1)
0099 #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS      BIT(0)
0100
0101 /* Offset 0x8: Interrupt Status */
0102 #define MV88E6XXX_PTP_GC_INT_STATUS     0x08
0103
0104 /* Offset 0x9/0xa: Global Time */
0105 #define MV88E6XXX_PTP_GC_TIME_LO        0x09
0106 #define MV88E6XXX_PTP_GC_TIME_HI        0x0A
0107
0108 /* 6165 Per Port Registers */
0109 /* Offset 0: Arrival Time 0 Status */
0110 #define MV88E6165_PORT_PTP_ARR0_STS 0x00
0111
0112 /* Offset 0x01/0x02: PTP Arrival 0 Time */
0113 #define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01
0114 #define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02
0115
0116 /* Offset 0x03: PTP Arrival 0 Sequence ID */
0117 #define MV88E6165_PORT_PTP_ARR0_SEQID   0x03
0118
0119 /* Offset 0x04: PTP Arrival 1 Status */
0120 #define MV88E6165_PORT_PTP_ARR1_STS 0x04
0121
0122 /* Offset 0x05/0x6E: PTP Arrival 1 Time */
0123 #define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05
0124 #define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06
0125
0126 /* Offset 0x07: PTP Arrival 1 Sequence ID */
0127 #define MV88E6165_PORT_PTP_ARR1_SEQID   0x07
0128
0129 /* Offset 0x08: PTP Departure Status */
0130 #define MV88E6165_PORT_PTP_DEP_STS  0x08
0131
0132 /* Offset 0x09/0x0a: PTP Deperture Time */
0133 #define MV88E6165_PORT_PTP_DEP_TIME_LO  0x09
0134 #define MV88E6165_PORT_PTP_DEP_TIME_HI  0x0a
0135
0136 /* Offset 0x0b: PTP Departure Sequence ID */
0137 #define MV88E6165_PORT_PTP_DEP_SEQID    0x0b
0138
0139 /* Offset 0x0d: Port Status */
0140 #define MV88E6164_PORT_STATUS       0x0d
0141
0142 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
0143
0144 long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);
0145 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);
0146 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
0147
0148 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip,   \
0149                       ptp_clock_info)
0150
0151 extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops;
0152 extern const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops;
0153 extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops;
0154
0155 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
0156
0157 static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)
0158 {
0159     return -1;
0160 }
0161
0162 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
0163 {
0164     return 0;
0165 }
0166
0167 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
0168 {
0169 }
0170
0171 static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {};
0172 static const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {};
0173 static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {};
0174
0175 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
0176
0177 #endif /* _MV88E6XXX_PTP_H */