dsa/mv88e6xxx/ptp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Marvell 88E6xxx Switch PTP support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2017 National Instruments
0008  *      Erik Hons <erik.hons@ni.com>
0009  *      Brandon Streiff <brandon.streiff@ni.com>
0010  *      Dane Wagner <dane.wagner@ni.com>
0011  */
0012
0013 #include "chip.h"
0014 #include "global2.h"
0015 #include "hwtstamp.h"
0016 #include "ptp.h"
0017
0018 #define MV88E6XXX_MAX_ADJ_PPB   1000000
0019
0020 /* Family MV88E6250:
0021  * Raw timestamps are in units of 10-ns clock periods.
0022  *
0023  * clkadj = scaled_ppm * 10*2^28 / (10^6 * 2^16)
0024  * simplifies to
0025  * clkadj = scaled_ppm * 2^7 / 5^5
0026  */
0027 #define MV88E6250_CC_SHIFT  28
0028 #define MV88E6250_CC_MULT   (10 << MV88E6250_CC_SHIFT)
0029 #define MV88E6250_CC_MULT_NUM   (1 << 7)
0030 #define MV88E6250_CC_MULT_DEM   3125ULL
0031
0032 /* Other families:
0033  * Raw timestamps are in units of 8-ns clock periods.
0034  *
0035  * clkadj = scaled_ppm * 8*2^28 / (10^6 * 2^16)
0036  * simplifies to
0037  * clkadj = scaled_ppm * 2^9 / 5^6
0038  */
0039 #define MV88E6XXX_CC_SHIFT  28
0040 #define MV88E6XXX_CC_MULT   (8 << MV88E6XXX_CC_SHIFT)
0041 #define MV88E6XXX_CC_MULT_NUM   (1 << 9)
0042 #define MV88E6XXX_CC_MULT_DEM   15625ULL
0043
0044 #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)
0045
0046 #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
0047 #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
0048                          overflow_work)
0049 #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
0050                           tai_event_work)
0051
0052 static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr,
0053                   u16 *data, int len)
0054 {
0055     if (!chip->info->ops->avb_ops->tai_read)
0056         return -EOPNOTSUPP;
0057
0058     return chip->info->ops->avb_ops->tai_read(chip, addr, data, len);
0059 }
0060
0061 static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data)
0062 {
0063     if (!chip->info->ops->avb_ops->tai_write)
0064         return -EOPNOTSUPP;
0065
0066     return chip->info->ops->avb_ops->tai_write(chip, addr, data);
0067 }
0068
0069 /* TODO: places where this are called should be using pinctrl */
0070 static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin,
0071                    int func, int input)
0072 {
0073     int err;
0074
0075     if (!chip->info->ops->gpio_ops)
0076         return -EOPNOTSUPP;
0077
0078     err = chip->info->ops->gpio_ops->set_dir(chip, pin, input);
0079     if (err)
0080         return err;
0081
0082     return chip->info->ops->gpio_ops->set_pctl(chip, pin, func);
0083 }
0084
0085 static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc)
0086 {
0087     struct mv88e6xxx_chip *chip = cc_to_chip(cc);
0088     u16 phc_time[2];
0089     int err;
0090
0091     err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time,
0092                  ARRAY_SIZE(phc_time));
0093     if (err)
0094         return 0;
0095     else
0096         return ((u32)phc_time[1] << 16) | phc_time[0];
0097 }
0098
0099 static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc)
0100 {
0101     struct mv88e6xxx_chip *chip = cc_to_chip(cc);
0102     u16 phc_time[2];
0103     int err;
0104
0105     err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time,
0106                  ARRAY_SIZE(phc_time));
0107     if (err)
0108         return 0;
0109     else
0110         return ((u32)phc_time[1] << 16) | phc_time[0];
0111 }
0112
0113 /* mv88e6352_config_eventcap - configure TAI event capture
0114  * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
0115  * @rising: zero for falling-edge trigger, else rising-edge trigger
0116  *
0117  * This will also reset the capture sequence counter.
0118  */
0119 static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event,
0120                      int rising)
0121 {
0122     u16 global_config;
0123     u16 cap_config;
0124     int err;
0125
0126     chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE |
0127                  MV88E6XXX_TAI_CFG_CAP_CTR_START;
0128     if (!rising)
0129         chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING;
0130
0131     global_config = (chip->evcap_config | chip->trig_config);
0132     err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config);
0133     if (err)
0134         return err;
0135
0136     if (event == PTP_CLOCK_PPS) {
0137         cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG;
0138     } else if (event == PTP_CLOCK_EXTTS) {
0139         /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
0140         cap_config = 0;
0141     } else {
0142         return -EINVAL;
0143     }
0144
0145     /* Write the capture config; this also clears the capture counter */
0146     err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS,
0147                   cap_config);
0148
0149     return err;
0150 }
0151
0152 static void mv88e6352_tai_event_work(struct work_struct *ugly)
0153 {
0154     struct delayed_work *dw = to_delayed_work(ugly);
0155     struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw);
0156     struct ptp_clock_event ev;
0157     u16 status[4];
0158     u32 raw_ts;
0159     int err;
0160
0161     mv88e6xxx_reg_lock(chip);
0162     err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS,
0163                  status, ARRAY_SIZE(status));
0164     mv88e6xxx_reg_unlock(chip);
0165
0166     if (err) {
0167         dev_err(chip->dev, "failed to read TAI status register\n");
0168         return;
0169     }
0170     if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) {
0171         dev_warn(chip->dev, "missed event capture\n");
0172         return;
0173     }
0174     if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID))
0175         goto out;
0176
0177     raw_ts = ((u32)status[2] << 16) | status[1];
0178
0179     /* Clear the valid bit so the next timestamp can come in */
0180     status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID;
0181     mv88e6xxx_reg_lock(chip);
0182     err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]);
0183     mv88e6xxx_reg_unlock(chip);
0184
0185     /* This is an external timestamp */
0186     ev.type = PTP_CLOCK_EXTTS;
0187
0188     /* We only have one timestamping channel. */
0189     ev.index = 0;
0190     mv88e6xxx_reg_lock(chip);
0191     ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts);
0192     mv88e6xxx_reg_unlock(chip);
0193
0194     ptp_clock_event(chip->ptp_clock, &ev);
0195 out:
0196     schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL);
0197 }
0198
0199 static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
0200 {
0201     struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
0202     const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
0203     int neg_adj = 0;
0204     u32 diff, mult;
0205     u64 adj;
0206
0207     if (scaled_ppm < 0) {
0208         neg_adj = 1;
0209         scaled_ppm = -scaled_ppm;
0210     }
0211
0212     mult = ptp_ops->cc_mult;
0213     adj = ptp_ops->cc_mult_num;
0214     adj *= scaled_ppm;
0215     diff = div_u64(adj, ptp_ops->cc_mult_dem);
0216
0217     mv88e6xxx_reg_lock(chip);
0218
0219     timecounter_read(&chip->tstamp_tc);
0220     chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff;
0221
0222     mv88e6xxx_reg_unlock(chip);
0223
0224     return 0;
0225 }
0226
0227 static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
0228 {
0229     struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
0230
0231     mv88e6xxx_reg_lock(chip);
0232     timecounter_adjtime(&chip->tstamp_tc, delta);
0233     mv88e6xxx_reg_unlock(chip);
0234
0235     return 0;
0236 }
0237
0238 static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp,
0239                  struct timespec64 *ts)
0240 {
0241     struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
0242     u64 ns;
0243
0244     mv88e6xxx_reg_lock(chip);
0245     ns = timecounter_read(&chip->tstamp_tc);
0246     mv88e6xxx_reg_unlock(chip);
0247
0248     *ts = ns_to_timespec64(ns);
0249
0250     return 0;
0251 }
0252
0253 static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp,
0254                  const struct timespec64 *ts)
0255 {
0256     struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
0257     u64 ns;
0258
0259     ns = timespec64_to_ns(ts);
0260
0261     mv88e6xxx_reg_lock(chip);
0262     timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns);
0263     mv88e6xxx_reg_unlock(chip);
0264
0265     return 0;
0266 }
0267
0268 static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip,
0269                       struct ptp_clock_request *rq, int on)
0270 {
0271     int rising = (rq->extts.flags & PTP_RISING_EDGE);
0272     int func;
0273     int pin;
0274     int err;
0275
0276     /* Reject requests with unsupported flags */
0277     if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0278                 PTP_RISING_EDGE |
0279                 PTP_FALLING_EDGE |
0280                 PTP_STRICT_FLAGS))
0281         return -EOPNOTSUPP;
0282
0283     /* Reject requests to enable time stamping on both edges. */
0284     if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
0285         (rq->extts.flags & PTP_ENABLE_FEATURE) &&
0286         (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
0287         return -EOPNOTSUPP;
0288
0289     pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
0290
0291     if (pin < 0)
0292         return -EBUSY;
0293
0294     mv88e6xxx_reg_lock(chip);
0295
0296     if (on) {
0297         func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ;
0298
0299         err = mv88e6352_set_gpio_func(chip, pin, func, true);
0300         if (err)
0301             goto out;
0302
0303         schedule_delayed_work(&chip->tai_event_work,
0304                       TAI_EVENT_WORK_INTERVAL);
0305
0306         err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising);
0307     } else {
0308         func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO;
0309
0310         err = mv88e6352_set_gpio_func(chip, pin, func, true);
0311
0312         cancel_delayed_work_sync(&chip->tai_event_work);
0313     }
0314
0315 out:
0316     mv88e6xxx_reg_unlock(chip);
0317
0318     return err;
0319 }
0320
0321 static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp,
0322                 struct ptp_clock_request *rq, int on)
0323 {
0324     struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
0325
0326     switch (rq->type) {
0327     case PTP_CLK_REQ_EXTTS:
0328         return mv88e6352_ptp_enable_extts(chip, rq, on);
0329     default:
0330         return -EOPNOTSUPP;
0331     }
0332 }
0333
0334 static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
0335                 enum ptp_pin_function func, unsigned int chan)
0336 {
0337     switch (func) {
0338     case PTP_PF_NONE:
0339     case PTP_PF_EXTTS:
0340         break;
0341     case PTP_PF_PEROUT:
0342     case PTP_PF_PHYSYNC:
0343         return -EOPNOTSUPP;
0344     }
0345     return 0;
0346 }
0347
0348 const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {
0349     .clock_read = mv88e6165_ptp_clock_read,
0350     .global_enable = mv88e6165_global_enable,
0351     .global_disable = mv88e6165_global_disable,
0352     .arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS,
0353     .arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS,
0354     .dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS,
0355     .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
0356         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
0357         (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
0358         (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
0359         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
0360         (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
0361         (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
0362     .cc_shift = MV88E6XXX_CC_SHIFT,
0363     .cc_mult = MV88E6XXX_CC_MULT,
0364     .cc_mult_num = MV88E6XXX_CC_MULT_NUM,
0365     .cc_mult_dem = MV88E6XXX_CC_MULT_DEM,
0366 };
0367
0368 const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {
0369     .clock_read = mv88e6352_ptp_clock_read,
0370     .ptp_enable = mv88e6352_ptp_enable,
0371     .ptp_verify = mv88e6352_ptp_verify,
0372     .event_work = mv88e6352_tai_event_work,
0373     .port_enable = mv88e6352_hwtstamp_port_enable,
0374     .port_disable = mv88e6352_hwtstamp_port_disable,
0375     .n_ext_ts = 1,
0376     .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
0377     .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
0378     .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
0379     .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
0380         (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
0381         (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
0382         (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
0383         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
0384         (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
0385         (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
0386         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
0387         (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
0388         (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
0389     .cc_shift = MV88E6250_CC_SHIFT,
0390     .cc_mult = MV88E6250_CC_MULT,
0391     .cc_mult_num = MV88E6250_CC_MULT_NUM,
0392     .cc_mult_dem = MV88E6250_CC_MULT_DEM,
0393 };
0394
0395 const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {
0396     .clock_read = mv88e6352_ptp_clock_read,
0397     .ptp_enable = mv88e6352_ptp_enable,
0398     .ptp_verify = mv88e6352_ptp_verify,
0399     .event_work = mv88e6352_tai_event_work,
0400     .port_enable = mv88e6352_hwtstamp_port_enable,
0401     .port_disable = mv88e6352_hwtstamp_port_disable,
0402     .n_ext_ts = 1,
0403     .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
0404     .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
0405     .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
0406     .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
0407         (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
0408         (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
0409         (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
0410         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
0411         (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
0412         (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
0413         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
0414         (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
0415         (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
0416     .cc_shift = MV88E6XXX_CC_SHIFT,
0417     .cc_mult = MV88E6XXX_CC_MULT,
0418     .cc_mult_num = MV88E6XXX_CC_MULT_NUM,
0419     .cc_mult_dem = MV88E6XXX_CC_MULT_DEM,
0420 };
0421
0422 static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc)
0423 {
0424     struct mv88e6xxx_chip *chip = cc_to_chip(cc);
0425
0426     if (chip->info->ops->ptp_ops->clock_read)
0427         return chip->info->ops->ptp_ops->clock_read(cc);
0428
0429     return 0;
0430 }
0431
0432 /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
0433  * seconds; this task forces periodic reads so that we don't miss any.
0434  */
0435 #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
0436 static void mv88e6xxx_ptp_overflow_check(struct work_struct *work)
0437 {
0438     struct delayed_work *dw = to_delayed_work(work);
0439     struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw);
0440     struct timespec64 ts;
0441
0442     mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts);
0443
0444     schedule_delayed_work(&chip->overflow_work,
0445                   MV88E6XXX_TAI_OVERFLOW_PERIOD);
0446 }
0447
0448 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
0449 {
0450     const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
0451     int i;
0452
0453     /* Set up the cycle counter */
0454     memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc));
0455     chip->tstamp_cc.read    = mv88e6xxx_ptp_clock_read;
0456     chip->tstamp_cc.mask    = CYCLECOUNTER_MASK(32);
0457     chip->tstamp_cc.mult    = ptp_ops->cc_mult;
0458     chip->tstamp_cc.shift   = ptp_ops->cc_shift;
0459
0460     timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc,
0461              ktime_to_ns(ktime_get_real()));
0462
0463     INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check);
0464     if (ptp_ops->event_work)
0465         INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work);
0466
0467     chip->ptp_clock_info.owner = THIS_MODULE;
0468     snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name),
0469          "%s", dev_name(chip->dev));
0470
0471     chip->ptp_clock_info.n_ext_ts   = ptp_ops->n_ext_ts;
0472     chip->ptp_clock_info.n_per_out  = 0;
0473     chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip);
0474     chip->ptp_clock_info.pps    = 0;
0475
0476     for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) {
0477         struct ptp_pin_desc *ppd = &chip->pin_config[i];
0478
0479         snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i);
0480         ppd->index = i;
0481         ppd->func = PTP_PF_NONE;
0482     }
0483     chip->ptp_clock_info.pin_config = chip->pin_config;
0484
0485     chip->ptp_clock_info.max_adj    = MV88E6XXX_MAX_ADJ_PPB;
0486     chip->ptp_clock_info.adjfine    = mv88e6xxx_ptp_adjfine;
0487     chip->ptp_clock_info.adjtime    = mv88e6xxx_ptp_adjtime;
0488     chip->ptp_clock_info.gettime64  = mv88e6xxx_ptp_gettime;
0489     chip->ptp_clock_info.settime64  = mv88e6xxx_ptp_settime;
0490     chip->ptp_clock_info.enable = ptp_ops->ptp_enable;
0491     chip->ptp_clock_info.verify = ptp_ops->ptp_verify;
0492     chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work;
0493
0494     chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev);
0495     if (IS_ERR(chip->ptp_clock))
0496         return PTR_ERR(chip->ptp_clock);
0497
0498     schedule_delayed_work(&chip->overflow_work,
0499                   MV88E6XXX_TAI_OVERFLOW_PERIOD);
0500
0501     return 0;
0502 }
0503
0504 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
0505 {
0506     if (chip->ptp_clock) {
0507         cancel_delayed_work_sync(&chip->overflow_work);
0508         if (chip->info->ops->ptp_ops->event_work)
0509             cancel_delayed_work_sync(&chip->tai_event_work);
0510
0511         ptp_clock_unregister(chip->ptp_clock);
0512         chip->ptp_clock = NULL;
0513     }
0514 }