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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx Switch Port Registers support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
0008  *  Vivien Didelot <vivien.didelot@savoirfairelinux.com>
0009  */
0010 
0011 #ifndef _MV88E6XXX_PORT_H
0012 #define _MV88E6XXX_PORT_H
0013 
0014 #include "chip.h"
0015 
0016 /* Offset 0x00: Port Status Register */
0017 #define MV88E6XXX_PORT_STS          0x00
0018 #define MV88E6XXX_PORT_STS_PAUSE_EN     0x8000
0019 #define MV88E6XXX_PORT_STS_MY_PAUSE     0x4000
0020 #define MV88E6XXX_PORT_STS_HD_FLOW      0x2000
0021 #define MV88E6XXX_PORT_STS_PHY_DETECT       0x1000
0022 #define MV88E6250_PORT_STS_LINK             0x1000
0023 #define MV88E6250_PORT_STS_PORTMODE_MASK        0x0f00
0024 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF     0x0800
0025 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF    0x0900
0026 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL     0x0a00
0027 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL    0x0b00
0028 #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF     0x0c00
0029 #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF    0x0d00
0030 #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL     0x0e00
0031 #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL    0x0f00
0032 #define MV88E6XXX_PORT_STS_LINK         0x0800
0033 #define MV88E6XXX_PORT_STS_DUPLEX       0x0400
0034 #define MV88E6XXX_PORT_STS_SPEED_MASK       0x0300
0035 #define MV88E6XXX_PORT_STS_SPEED_10     0x0000
0036 #define MV88E6XXX_PORT_STS_SPEED_100        0x0100
0037 #define MV88E6XXX_PORT_STS_SPEED_1000       0x0200
0038 #define MV88E6XXX_PORT_STS_SPEED_10000      0x0300
0039 #define MV88E6352_PORT_STS_EEE          0x0040
0040 #define MV88E6165_PORT_STS_AM_DIS       0x0040
0041 #define MV88E6185_PORT_STS_MGMII        0x0040
0042 #define MV88E6XXX_PORT_STS_TX_PAUSED        0x0020
0043 #define MV88E6XXX_PORT_STS_FLOW_CTL     0x0010
0044 #define MV88E6XXX_PORT_STS_CMODE_MASK       0x000f
0045 #define MV88E6XXX_PORT_STS_CMODE_MII_PHY    0x0001
0046 #define MV88E6XXX_PORT_STS_CMODE_MII        0x0002
0047 #define MV88E6XXX_PORT_STS_CMODE_GMII       0x0003
0048 #define MV88E6XXX_PORT_STS_CMODE_RMII_PHY   0x0004
0049 #define MV88E6XXX_PORT_STS_CMODE_RMII       0x0005
0050 #define MV88E6XXX_PORT_STS_CMODE_RGMII      0x0007
0051 #define MV88E6XXX_PORT_STS_CMODE_100BASEX   0x0008
0052 #define MV88E6XXX_PORT_STS_CMODE_1000BASEX  0x0009
0053 #define MV88E6XXX_PORT_STS_CMODE_SGMII      0x000a
0054 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX  0x000b
0055 #define MV88E6XXX_PORT_STS_CMODE_XAUI       0x000c
0056 #define MV88E6XXX_PORT_STS_CMODE_RXAUI      0x000d
0057 #define MV88E6393X_PORT_STS_CMODE_5GBASER   0x000c
0058 #define MV88E6393X_PORT_STS_CMODE_10GBASER  0x000d
0059 #define MV88E6393X_PORT_STS_CMODE_USXGMII   0x000e
0060 #define MV88E6185_PORT_STS_CDUPLEX      0x0008
0061 #define MV88E6185_PORT_STS_CMODE_MASK       0x0007
0062 #define MV88E6185_PORT_STS_CMODE_GMII_FD    0x0000
0063 #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS  0x0001
0064 #define MV88E6185_PORT_STS_CMODE_MII_100    0x0002
0065 #define MV88E6185_PORT_STS_CMODE_MII_10     0x0003
0066 #define MV88E6185_PORT_STS_CMODE_SERDES     0x0004
0067 #define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005
0068 #define MV88E6185_PORT_STS_CMODE_PHY        0x0006
0069 #define MV88E6185_PORT_STS_CMODE_DISABLED   0x0007
0070 
0071 /* Offset 0x01: MAC (or PCS or Physical) Control Register */
0072 #define MV88E6XXX_PORT_MAC_CTL              0x01
0073 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK    0x8000
0074 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK    0x4000
0075 #define MV88E6185_PORT_MAC_CTL_SYNC_OK          0x4000
0076 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED      0x2000
0077 #define MV88E6390_PORT_MAC_CTL_ALTSPEED         0x1000
0078 #define MV88E6352_PORT_MAC_CTL_200BASE          0x1000
0079 #define MV88E6XXX_PORT_MAC_CTL_EEE          0x0200
0080 #define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE        0x0100
0081 #define MV88E6185_PORT_MAC_CTL_AN_EN            0x0400
0082 #define MV88E6185_PORT_MAC_CTL_AN_RESTART       0x0200
0083 #define MV88E6185_PORT_MAC_CTL_AN_DONE          0x0100
0084 #define MV88E6XXX_PORT_MAC_CTL_FC           0x0080
0085 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC         0x0040
0086 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP          0x0020
0087 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK       0x0010
0088 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL      0x0008
0089 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX     0x0004
0090 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK       0x0003
0091 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10         0x0000
0092 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100        0x0001
0093 #define MV88E6065_PORT_MAC_CTL_SPEED_200        0x0002
0094 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000       0x0002
0095 #define MV88E6390_PORT_MAC_CTL_SPEED_10000      0x0003
0096 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED       0x0003
0097 
0098 /* Offset 0x02: Jamming Control Register */
0099 #define MV88E6097_PORT_JAM_CTL          0x02
0100 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK   0xff00
0101 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK    0x00ff
0102 
0103 /* Offset 0x02: Flow Control Register */
0104 #define MV88E6390_PORT_FLOW_CTL         0x02
0105 #define MV88E6390_PORT_FLOW_CTL_UPDATE      0x8000
0106 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK    0x7f00
0107 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN    0x0000
0108 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT   0x0100
0109 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK   0x00ff
0110 
0111 /* Offset 0x03: Switch Identifier Register */
0112 #define MV88E6XXX_PORT_SWITCH_ID        0x03
0113 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK  0xfff0
0114 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085  0x04a0
0115 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095  0x0950
0116 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097  0x0990
0117 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00
0118 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10
0119 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131  0x1060
0120 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320  0x1150
0121 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123  0x1210
0122 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161  0x1610
0123 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165  0x1650
0124 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171  0x1710
0125 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172  0x1720
0126 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175  0x1750
0127 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176  0x1760
0128 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190  0x1900
0129 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191  0x1910
0130 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920
0131 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930
0132 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185  0x1a70
0133 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220  0x2200
0134 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240  0x2400
0135 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250  0x2500
0136 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290  0x2900
0137 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321  0x3100
0138 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141  0x3400
0139 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341  0x3410
0140 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352  0x3520
0141 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350  0x3710
0142 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351  0x3750
0143 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390  0x3900
0144 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930
0145 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK   0x000f
0146 
0147 /* Offset 0x04: Port Control Register */
0148 #define MV88E6XXX_PORT_CTL0                 0x04
0149 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG            0x8000
0150 #define MV88E6XXX_PORT_CTL0_SA_FILT_MASK            0xc000
0151 #define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED            0x0000
0152 #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK        0x4000
0153 #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK      0x8000
0154 #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU     0xc000
0155 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK            0x3000
0156 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED      0x0000
0157 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED        0x1000
0158 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED          0x2000
0159 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA      0x3000
0160 #define MV88E6XXX_PORT_CTL0_HEADER              0x0800
0161 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP          0x0400
0162 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG              0x0200
0163 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK         0x0300
0164 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL           0x0000
0165 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA          0x0100
0166 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER         0x0200
0167 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA       0x0300
0168 #define MV88E6XXX_PORT_CTL0_DSA_TAG             0x0100
0169 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL             0x0080
0170 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH             0x0040
0171 #define MV88E6185_PORT_CTL0_USE_IP              0x0020
0172 #define MV88E6185_PORT_CTL0_USE_TAG             0x0010
0173 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN         0x0004
0174 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC            0x0004
0175 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC            0x0008
0176 #define MV88E6XXX_PORT_CTL0_STATE_MASK              0x0003
0177 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED          0x0000
0178 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING          0x0001
0179 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING          0x0002
0180 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING            0x0003
0181 
0182 /* Offset 0x05: Port Control 1 */
0183 #define MV88E6XXX_PORT_CTL1         0x05
0184 #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT    0x8000
0185 #define MV88E6XXX_PORT_CTL1_TRUNK_PORT      0x4000
0186 #define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK   0x0f00
0187 #define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT  8
0188 #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK   0x00ff
0189 
0190 /* Offset 0x06: Port Based VLAN Map */
0191 #define MV88E6XXX_PORT_BASE_VLAN        0x06
0192 #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK   0xf000
0193 
0194 /* Offset 0x07: Default Port VLAN ID & Priority */
0195 #define MV88E6XXX_PORT_DEFAULT_VLAN     0x07
0196 #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK    0x0fff
0197 
0198 /* Offset 0x08: Port Control 2 Register */
0199 #define MV88E6XXX_PORT_CTL2             0x08
0200 #define MV88E6XXX_PORT_CTL2_IGNORE_FCS          0x8000
0201 #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE        0x4000
0202 #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE        0x2000
0203 #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE        0x1000
0204 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK     0x3000
0205 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522     0x0000
0206 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048     0x1000
0207 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240        0x2000
0208 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK     0x0c00
0209 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED     0x0000
0210 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK     0x0400
0211 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK        0x0800
0212 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE       0x0c00
0213 #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED      0x0200
0214 #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED        0x0100
0215 #define MV88E6XXX_PORT_CTL2_MAP_DA          0x0080
0216 #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD     0x0040
0217 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR      0x0020
0218 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR     0x0010
0219 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK       0x000f
0220 
0221 /* Offset 0x09: Egress Rate Control */
0222 #define MV88E6XXX_PORT_EGRESS_RATE_CTL1     0x09
0223 
0224 /* Offset 0x0A: Egress Rate Control 2 */
0225 #define MV88E6XXX_PORT_EGRESS_RATE_CTL2     0x0a
0226 
0227 /* Offset 0x0B: Port Association Vector */
0228 #define MV88E6XXX_PORT_ASSOC_VECTOR         0x0b
0229 #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1       0x8000
0230 #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT     0x4000
0231 #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT     0x2000
0232 #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG    0x1000
0233 #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED  0x0800
0234 
0235 /* Offset 0x0C: Port ATU Control */
0236 #define MV88E6XXX_PORT_ATU_CTL      0x0c
0237 
0238 /* Offset 0x0D: Priority Override Register */
0239 #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
0240 
0241 /* Offset 0x0E: Policy Control Register */
0242 #define MV88E6XXX_PORT_POLICY_CTL       0x0e
0243 #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK   0xc000
0244 #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK   0x3000
0245 #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK  0x0c00
0246 #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK    0x0300
0247 #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK    0x00c0
0248 #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030
0249 #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK    0x000c
0250 #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK  0x0003
0251 #define MV88E6XXX_PORT_POLICY_CTL_NORMAL    0x0000
0252 #define MV88E6XXX_PORT_POLICY_CTL_MIRROR    0x0001
0253 #define MV88E6XXX_PORT_POLICY_CTL_TRAP      0x0002
0254 #define MV88E6XXX_PORT_POLICY_CTL_DISCARD   0x0003
0255 
0256 /* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */
0257 #define MV88E6393X_PORT_POLICY_MGMT_CTL             0x0e
0258 #define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE          0x8000
0259 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK        0x3f00
0260 #define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK       0x00ff
0261 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000
0262 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100
0263 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400
0264 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500
0265 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST    0x3000
0266 #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST        0x3800
0267 #define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI    0x00e0
0268 
0269 /* Offset 0x0F: Port Special Ether Type */
0270 #define MV88E6XXX_PORT_ETH_TYPE     0x0f
0271 #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
0272 
0273 /* Offset 0x10: InDiscards Low Counter */
0274 #define MV88E6XXX_PORT_IN_DISCARD_LO    0x10
0275 
0276 /* Offset 0x10: Extended Port Control Command */
0277 #define MV88E6393X_PORT_EPC_CMD     0x10
0278 #define MV88E6393X_PORT_EPC_CMD_BUSY    0x8000
0279 #define MV88E6393X_PORT_EPC_CMD_WRITE   0x0300
0280 #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE    0x02
0281 
0282 /* Offset 0x11: Extended Port Control Data */
0283 #define MV88E6393X_PORT_EPC_DATA    0x11
0284 
0285 /* Offset 0x11: InDiscards High Counter */
0286 #define MV88E6XXX_PORT_IN_DISCARD_HI    0x11
0287 
0288 /* Offset 0x12: InFiltered Counter */
0289 #define MV88E6XXX_PORT_IN_FILTERED  0x12
0290 
0291 /* Offset 0x13: OutFiltered Counter */
0292 #define MV88E6XXX_PORT_OUT_FILTERED 0x13
0293 
0294 /* Offset 0x18: IEEE Priority Mapping Table */
0295 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE          0x18
0296 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE       0x8000
0297 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK         0x7000
0298 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP      0x0000
0299 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
0300 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP    0x2000
0301 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP   0x3000
0302 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP    0x5000
0303 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP   0x6000
0304 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP  0x7000
0305 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK     0x0e00
0306 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK        0x01ff
0307 
0308 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
0309 #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
0310 
0311 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
0312 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
0313 
0314 /* Offset 0x1a: Magic undocumented errata register */
0315 #define MV88E6XXX_PORT_RESERVED_1A      0x1a
0316 #define MV88E6XXX_PORT_RESERVED_1A_BUSY     0x8000
0317 #define MV88E6XXX_PORT_RESERVED_1A_WRITE    0x4000
0318 #define MV88E6XXX_PORT_RESERVED_1A_READ     0x0000
0319 #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT   5
0320 #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT  10
0321 #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT    0x04
0322 #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT    0x05
0323 #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE  0x8000
0324 #define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000
0325 
0326 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
0327             u16 *val);
0328 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
0329              u16 val);
0330 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
0331                 int bit, int val);
0332 
0333 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
0334                  int pause);
0335 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
0336                    phy_interface_t mode);
0337 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
0338                    phy_interface_t mode);
0339 
0340 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
0341 
0342 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
0343 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
0344 
0345 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0346                     int speed, int duplex);
0347 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0348                     int speed, int duplex);
0349 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0350                     int speed, int duplex);
0351 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0352                     int speed, int duplex);
0353 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0354                     int speed, int duplex);
0355 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0356                      int speed, int duplex);
0357 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
0358                      int speed, int duplex);
0359 
0360 phy_interface_t mv88e6341_port_max_speed_mode(int port);
0361 phy_interface_t mv88e6390_port_max_speed_mode(int port);
0362 phy_interface_t mv88e6390x_port_max_speed_mode(int port);
0363 phy_interface_t mv88e6393x_port_max_speed_mode(int port);
0364 
0365 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
0366 
0367 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
0368 
0369 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
0370 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
0371 
0372 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
0373 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
0374 
0375 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
0376                 bool locked);
0377 
0378 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
0379                   u16 mode);
0380 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
0381 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
0382 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
0383                    enum mv88e6xxx_egress_mode mode);
0384 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
0385                   enum mv88e6xxx_frame_mode mode);
0386 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
0387                   enum mv88e6xxx_frame_mode mode);
0388 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
0389                        int port, bool unicast);
0390 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
0391                        int port, bool multicast);
0392 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
0393                    bool unicast);
0394 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
0395                    bool multicast);
0396 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
0397                   enum mv88e6xxx_policy_mapping mapping,
0398                   enum mv88e6xxx_policy_action action);
0399 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
0400                    enum mv88e6xxx_policy_mapping mapping,
0401                    enum mv88e6xxx_policy_action action);
0402 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
0403                   u16 etype);
0404 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
0405                    enum mv88e6xxx_egress_direction direction,
0406                    int port);
0407 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
0408                       int upstream_port);
0409 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
0410 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
0411                    u16 etype);
0412 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
0413                     bool message_port);
0414 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
0415                  bool trunk, u8 id);
0416 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
0417                   size_t size);
0418 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
0419 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
0420 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
0421                     u16 pav);
0422 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
0423                    u8 out);
0424 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
0425                    u8 out);
0426 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
0427                  phy_interface_t mode);
0428 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
0429                  phy_interface_t mode);
0430 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
0431                   phy_interface_t mode);
0432 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
0433                   phy_interface_t mode);
0434 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
0435 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
0436 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
0437                  bool drop_untagged);
0438 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map);
0439 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
0440                      int upstream_port);
0441 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
0442                   enum mv88e6xxx_egress_direction direction,
0443                   bool mirror);
0444 
0445 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
0446 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
0447 
0448 int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,
0449                 int port, int reg, u16 val);
0450 int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);
0451 int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,
0452                    int reg, u16 *val);
0453 
0454 #endif /* _MV88E6XXX_PORT_H */
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