dsa/mv88e6xxx/phy.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx PHY access
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
0008  */
0009
0010 #ifndef _MV88E6XXX_PHY_H
0011 #define _MV88E6XXX_PHY_H
0012
0013 #define MV88E6XXX_PHY_PAGE      0x16
0014 #define MV88E6XXX_PHY_PAGE_COPPER   0x00
0015
0016 /* PHY Registers accesses implementations */
0017 int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
0018                int addr, int reg, u16 *val);
0019 int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
0020             int addr, int reg, u16 val);
0021 int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
0022                int addr, int reg, u16 *val);
0023 int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
0024                 int addr, int reg, u16 val);
0025
0026 /* Generic PHY operations */
0027 int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
0028                int reg, u16 *val);
0029 int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
0030             int reg, u16 val);
0031 int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
0032                 u8 page, int reg, u16 *val);
0033 int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
0034                  u8 page, int reg, u16 val);
0035 void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip);
0036 void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip);
0037 int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip);
0038
0039 #endif /*_MV88E6XXX_PHY_H */