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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx Switch Global 2 Registers support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
0008  *  Vivien Didelot <vivien.didelot@savoirfairelinux.com>
0009  */
0010 
0011 #ifndef _MV88E6XXX_GLOBAL2_H
0012 #define _MV88E6XXX_GLOBAL2_H
0013 
0014 #include "chip.h"
0015 
0016 /* Offset 0x00: Interrupt Source Register */
0017 #define MV88E6XXX_G2_INT_SRC            0x00
0018 #define MV88E6XXX_G2_INT_SRC_WDOG       0x8000
0019 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT      0x4000
0020 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH    0x2000
0021 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT     0x1000
0022 #define MV88E6352_G2_INT_SRC_SERDES     0x0800
0023 #define MV88E6352_G2_INT_SRC_PHY        0x001f
0024 #define MV88E6390_G2_INT_SRC_PHY        0x07fe
0025 
0026 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG    15
0027 
0028 /* Offset 0x01: Interrupt Mask Register */
0029 #define MV88E6XXX_G2_INT_MASK           0x01
0030 #define MV88E6XXX_G2_INT_MASK_WDOG      0x8000
0031 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT     0x4000
0032 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH   0x2000
0033 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT    0x1000
0034 #define MV88E6352_G2_INT_MASK_SERDES        0x0800
0035 #define MV88E6352_G2_INT_MASK_PHY       0x001f
0036 #define MV88E6390_G2_INT_MASK_PHY       0x07fe
0037 
0038 /* Offset 0x02: MGMT Enable Register 2x */
0039 #define MV88E6XXX_G2_MGMT_EN_2X     0x02
0040 
0041 /* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */
0042 #define MV88E6393X_G2_MACLINK_INT_SRC       0x02
0043 
0044 /* Offset 0x03: MGMT Enable Register 0x */
0045 #define MV88E6XXX_G2_MGMT_EN_0X     0x03
0046 
0047 /* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */
0048 #define MV88E6393X_G2_MACLINK_INT_MASK      0x03
0049 
0050 /* Offset 0x04: Flow Control Delay Register */
0051 #define MV88E6XXX_G2_FLOW_CTL   0x04
0052 
0053 /* Offset 0x05: Switch Management Register */
0054 #define MV88E6XXX_G2_SWITCH_MGMT            0x05
0055 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA    0x8000
0056 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS      0x4000
0057 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG       0x2000
0058 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
0059 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU       0x0008
0060 
0061 #define MV88E6393X_G2_EGRESS_MONITOR_DEST       0x05
0062 
0063 /* Offset 0x06: Device Mapping Table Register */
0064 #define MV88E6XXX_G2_DEVICE_MAPPING     0x06
0065 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE  0x8000
0066 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK    0x1f00
0067 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK   0x000f
0068 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK   0x001f
0069 
0070 /* Offset 0x07: Trunk Mask Table Register */
0071 #define MV88E6XXX_G2_TRUNK_MASK         0x07
0072 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE      0x8000
0073 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK    0x7000
0074 #define MV88E6XXX_G2_TRUNK_MASK_HASH        0x0800
0075 
0076 /* Offset 0x08: Trunk Mapping Table Register */
0077 #define MV88E6XXX_G2_TRUNK_MAPPING      0x08
0078 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE   0x8000
0079 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK  0x7800
0080 
0081 /* Offset 0x09: Ingress Rate Command Register */
0082 #define MV88E6XXX_G2_IRL_CMD            0x09
0083 #define MV88E6XXX_G2_IRL_CMD_BUSY       0x8000
0084 #define MV88E6352_G2_IRL_CMD_OP_MASK        0x7000
0085 #define MV88E6352_G2_IRL_CMD_OP_NOOP        0x0000
0086 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL    0x1000
0087 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES    0x2000
0088 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG   0x3000
0089 #define MV88E6352_G2_IRL_CMD_OP_READ_REG    0x4000
0090 #define MV88E6390_G2_IRL_CMD_OP_MASK        0x6000
0091 #define MV88E6390_G2_IRL_CMD_OP_READ_REG    0x0000
0092 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL    0x2000
0093 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES    0x4000
0094 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG   0x6000
0095 #define MV88E6352_G2_IRL_CMD_PORT_MASK      0x0f00
0096 #define MV88E6390_G2_IRL_CMD_PORT_MASK      0x1f00
0097 #define MV88E6XXX_G2_IRL_CMD_RES_MASK       0x00e0
0098 #define MV88E6XXX_G2_IRL_CMD_REG_MASK       0x000f
0099 
0100 /* Offset 0x0A: Ingress Rate Data Register */
0101 #define MV88E6XXX_G2_IRL_DATA       0x0a
0102 #define MV88E6XXX_G2_IRL_DATA_MASK  0xffff
0103 
0104 /* Offset 0x0B: Cross-chip Port VLAN Register */
0105 #define MV88E6XXX_G2_PVT_ADDR           0x0b
0106 #define MV88E6XXX_G2_PVT_ADDR_BUSY      0x8000
0107 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK       0x7000
0108 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES  0x1000
0109 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN    0x3000
0110 #define MV88E6XXX_G2_PVT_ADDR_OP_READ       0x4000
0111 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK      0x01ff
0112 #define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK     0x1f
0113 
0114 /* Offset 0x0C: Cross-chip Port VLAN Data Register */
0115 #define MV88E6XXX_G2_PVT_DATA       0x0c
0116 #define MV88E6XXX_G2_PVT_DATA_MASK  0x7f
0117 
0118 /* Offset 0x0D: Switch MAC/WoL/WoF Register */
0119 #define MV88E6XXX_G2_SWITCH_MAC         0x0d
0120 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE      0x8000
0121 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK    0x1f00
0122 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK   0x00ff
0123 
0124 /* Offset 0x0E: ATU Stats Register */
0125 #define MV88E6XXX_G2_ATU_STATS              0x0e
0126 #define MV88E6XXX_G2_ATU_STATS_BIN_0            (0x0 << 14)
0127 #define MV88E6XXX_G2_ATU_STATS_BIN_1            (0x1 << 14)
0128 #define MV88E6XXX_G2_ATU_STATS_BIN_2            (0x2 << 14)
0129 #define MV88E6XXX_G2_ATU_STATS_BIN_3            (0x3 << 14)
0130 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL         (0x0 << 12)
0131 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC     (0x1 << 12)
0132 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL     (0x2 << 12)
0133 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12)
0134 #define MV88E6XXX_G2_ATU_STATS_MASK         0x0fff
0135 
0136 /* Offset 0x0F: Priority Override Table */
0137 #define MV88E6XXX_G2_PRIO_OVERRIDE      0x0f
0138 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE   0x8000
0139 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET  0x1000
0140 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
0141 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN    0x0080
0142 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
0143 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN  0x0008
0144 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK    0x0007
0145 
0146 /* Offset 0x14: EEPROM Command */
0147 #define MV88E6XXX_G2_EEPROM_CMD         0x14
0148 #define MV88E6XXX_G2_EEPROM_CMD_BUSY        0x8000
0149 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK     0x7000
0150 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE    0x3000
0151 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ     0x4000
0152 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD     0x6000
0153 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING     0x0800
0154 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN    0x0400
0155 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK   0x00ff
0156 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK   0x00ff
0157 
0158 /* Offset 0x15: EEPROM Data */
0159 #define MV88E6352_G2_EEPROM_DATA    0x15
0160 #define MV88E6352_G2_EEPROM_DATA_MASK   0xffff
0161 
0162 /* Offset 0x15: EEPROM Addr */
0163 #define MV88E6390_G2_EEPROM_ADDR    0x15
0164 #define MV88E6390_G2_EEPROM_ADDR_MASK   0xffff
0165 
0166 /* Offset 0x16: AVB Command Register */
0167 #define MV88E6352_G2_AVB_CMD            0x16
0168 #define MV88E6352_G2_AVB_CMD_BUSY       0x8000
0169 #define MV88E6352_G2_AVB_CMD_OP_READ        0x4000
0170 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR   0x6000
0171 #define MV88E6352_G2_AVB_CMD_OP_WRITE       0x3000
0172 #define MV88E6390_G2_AVB_CMD_OP_READ        0x0000
0173 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR   0x4000
0174 #define MV88E6390_G2_AVB_CMD_OP_WRITE       0x6000
0175 #define MV88E6352_G2_AVB_CMD_PORT_MASK      0x0f00
0176 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe
0177 #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
0178 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
0179 #define MV88E6390_G2_AVB_CMD_PORT_MASK      0x1f00
0180 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e
0181 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f
0182 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP      0
0183 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB      1
0184 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV      2
0185 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB      3
0186 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK     0x00e0
0187 #define MV88E6352_G2_AVB_CMD_ADDR_MASK      0x001f
0188 
0189 /* Offset 0x17: AVB Data Register */
0190 #define MV88E6352_G2_AVB_DATA       0x17
0191 
0192 /* Offset 0x18: SMI PHY Command Register */
0193 #define MV88E6XXX_G2_SMI_PHY_CMD            0x18
0194 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY           0x8000
0195 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK      0x6000
0196 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL      0x0000
0197 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL      0x2000
0198 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP     0x4000
0199 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK      0x1000
0200 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45        0x0000
0201 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22        0x1000
0202 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK        0x0c00
0203 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA   0x0400
0204 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA    0x0800
0205 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR   0x0000
0206 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA   0x0400
0207 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC    0x0800
0208 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA    0x0c00
0209 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK      0x03e0
0210 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK      0x001f
0211 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK     0x03ff
0212 
0213 /* Offset 0x19: SMI PHY Data Register */
0214 #define MV88E6XXX_G2_SMI_PHY_DATA   0x19
0215 
0216 /* Offset 0x1A: Scratch and Misc. Register */
0217 #define MV88E6XXX_G2_SCRATCH_MISC_MISC      0x1a
0218 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE    0x8000
0219 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK  0x7f00
0220 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
0221 
0222 /* Offset 0x1B: Watch Dog Control Register */
0223 #define MV88E6250_G2_WDOG_CTL           0x1b
0224 #define MV88E6250_G2_WDOG_CTL_QC_HISTORY    0x0100
0225 #define MV88E6250_G2_WDOG_CTL_QC_EVENT      0x0080
0226 #define MV88E6250_G2_WDOG_CTL_QC_ENABLE     0x0040
0227 #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY    0x0020
0228 #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT  0x0010
0229 #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
0230 #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ     0x0004
0231 #define MV88E6250_G2_WDOG_CTL_HISTORY       0x0002
0232 #define MV88E6250_G2_WDOG_CTL_SWRESET       0x0001
0233 
0234 /* Offset 0x1B: Watch Dog Control Register */
0235 #define MV88E6352_G2_WDOG_CTL           0x1b
0236 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT  0x0080
0237 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT   0x0040
0238 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE     0x0020
0239 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY    0x0010
0240 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
0241 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ     0x0004
0242 #define MV88E6352_G2_WDOG_CTL_HISTORY       0x0002
0243 #define MV88E6352_G2_WDOG_CTL_SWRESET       0x0001
0244 
0245 /* Offset 0x1B: Watch Dog Control Register */
0246 #define MV88E6390_G2_WDOG_CTL               0x1b
0247 #define MV88E6390_G2_WDOG_CTL_UPDATE            0x8000
0248 #define MV88E6390_G2_WDOG_CTL_PTR_MASK          0x7f00
0249 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE        0x0000
0250 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS       0x1000
0251 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE        0x1100
0252 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT         0x1200
0253 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY       0x1300
0254 #define MV88E6390_G2_WDOG_CTL_DATA_MASK         0x00ff
0255 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH       0x0008
0256 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER      0x0004
0257 #define MV88E6390_G2_WDOG_CTL_EGRESS            0x0002
0258 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ         0x0001
0259 
0260 /* Offset 0x1C: QoS Weights Register */
0261 #define MV88E6XXX_G2_QOS_WEIGHTS        0x1c
0262 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE     0x8000
0263 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK   0x3f00
0264 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK   0x7f00
0265 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK  0x00ff
0266 
0267 /* Offset 0x1D: Misc Register */
0268 #define MV88E6XXX_G2_MISC       0x1d
0269 #define MV88E6XXX_G2_MISC_5_BIT_PORT    0x4000
0270 #define MV88E6352_G2_NOEGR_POLICY   0x2000
0271 #define MV88E6390_G2_LAG_ID_4       0x2000
0272 
0273 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
0274 /* Offset 0x02: Misc Configuration */
0275 #define MV88E6352_G2_SCRATCH_MISC_CFG       0x02
0276 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
0277 /* Offset 0x60-0x61: GPIO Configuration */
0278 #define MV88E6352_G2_SCRATCH_GPIO_CFG0      0x60
0279 #define MV88E6352_G2_SCRATCH_GPIO_CFG1      0x61
0280 /* Offset 0x62-0x63: GPIO Direction */
0281 #define MV88E6352_G2_SCRATCH_GPIO_DIR0      0x62
0282 #define MV88E6352_G2_SCRATCH_GPIO_DIR1      0x63
0283 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT   0
0284 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN    1
0285 /* Offset 0x64-0x65: GPIO Data */
0286 #define MV88E6352_G2_SCRATCH_GPIO_DATA0     0x64
0287 #define MV88E6352_G2_SCRATCH_GPIO_DATA1     0x65
0288 /* Offset 0x68-0x6F: GPIO Pin Control */
0289 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0     0x68
0290 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1     0x69
0291 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2     0x6A
0292 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3     0x6B
0293 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4     0x6C
0294 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5     0x6D
0295 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6     0x6E
0296 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7     0x6F
0297 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0   0x70
0298 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1   0x71
0299 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU    BIT(2)
0300 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2   0x72
0301 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK  0x3
0302 #define MV88E6352_G2_SCRATCH_CONFIG_DATA3   0x73
0303 #define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL     BIT(1)
0304 
0305 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0
0306 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1
0307 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ    2
0308 
0309 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
0310 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
0311 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
0312               int bit, int val);
0313 
0314 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
0315 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
0316 
0317 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
0318                   struct mii_bus *bus,
0319                   int addr, int reg, u16 *val);
0320 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
0321                    struct mii_bus *bus,
0322                    int addr, int reg, u16 val);
0323 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
0324 
0325 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
0326                  struct ethtool_eeprom *eeprom, u8 *data);
0327 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
0328                  struct ethtool_eeprom *eeprom, u8 *data);
0329 
0330 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
0331                   struct ethtool_eeprom *eeprom, u8 *data);
0332 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
0333                   struct ethtool_eeprom *eeprom, u8 *data);
0334 
0335 int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
0336               int src_port, u16 *data);
0337 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
0338                int src_port, u16 data);
0339 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
0340 
0341 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
0342 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
0343 
0344 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
0345                 struct mii_bus *bus);
0346 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
0347                 struct mii_bus *bus);
0348 
0349 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
0350 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
0351 
0352 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
0353 
0354 int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
0355                   bool hash, u16 mask);
0356 int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
0357                      u16 map);
0358 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
0359 
0360 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
0361                       int port);
0362 
0363 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
0364 extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
0365 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
0366 
0367 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
0368 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
0369 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
0370 
0371 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
0372 
0373 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
0374                       bool external);
0375 int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
0376 int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
0377 int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
0378 
0379 #endif /* _MV88E6XXX_GLOBAL2_H */
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