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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx Switch Global (1) Registers support
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  *
0007  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
0008  *  Vivien Didelot <vivien.didelot@savoirfairelinux.com>
0009  */
0010 
0011 #ifndef _MV88E6XXX_GLOBAL1_H
0012 #define _MV88E6XXX_GLOBAL1_H
0013 
0014 #include "chip.h"
0015 
0016 /* Offset 0x00: Switch Global Status Register */
0017 #define MV88E6XXX_G1_STS                0x00
0018 #define MV88E6352_G1_STS_PPU_STATE          0x8000
0019 #define MV88E6185_G1_STS_PPU_STATE_MASK         0xc000
0020 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST     0x0000
0021 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING     0x4000
0022 #define MV88E6185_G1_STS_PPU_STATE_DISABLED     0x8000
0023 #define MV88E6185_G1_STS_PPU_STATE_POLLING      0xc000
0024 #define MV88E6XXX_G1_STS_INIT_READY         0x0800
0025 #define MV88E6393X_G1_STS_IRQ_DEVICE_2          9
0026 #define MV88E6XXX_G1_STS_IRQ_AVB            8
0027 #define MV88E6XXX_G1_STS_IRQ_DEVICE         7
0028 #define MV88E6XXX_G1_STS_IRQ_STATS          6
0029 #define MV88E6XXX_G1_STS_IRQ_VTU_PROB           5
0030 #define MV88E6XXX_G1_STS_IRQ_VTU_DONE           4
0031 #define MV88E6XXX_G1_STS_IRQ_ATU_PROB           3
0032 #define MV88E6XXX_G1_STS_IRQ_ATU_DONE           2
0033 #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE          1
0034 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE        0
0035 
0036 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
0037  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
0038  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
0039  */
0040 #define MV88E6XXX_G1_MAC_01     0x01
0041 #define MV88E6XXX_G1_MAC_23     0x02
0042 #define MV88E6XXX_G1_MAC_45     0x03
0043 
0044 /* Offset 0x01: ATU FID Register */
0045 #define MV88E6352_G1_ATU_FID        0x01
0046 
0047 /* Offset 0x02: VTU FID Register */
0048 #define MV88E6352_G1_VTU_FID        0x02
0049 #define MV88E6352_G1_VTU_FID_VID_POLICY 0x1000
0050 #define MV88E6352_G1_VTU_FID_MASK   0x0fff
0051 
0052 /* Offset 0x03: VTU SID Register */
0053 #define MV88E6352_G1_VTU_SID        0x03
0054 #define MV88E6352_G1_VTU_SID_MASK   0x3f
0055 
0056 /* Offset 0x04: Switch Global Control Register */
0057 #define MV88E6XXX_G1_CTL1           0x04
0058 #define MV88E6XXX_G1_CTL1_SW_RESET      0x8000
0059 #define MV88E6XXX_G1_CTL1_PPU_ENABLE        0x4000
0060 #define MV88E6352_G1_CTL1_DISCARD_EXCESS    0x2000
0061 #define MV88E6185_G1_CTL1_SCHED_PRIO        0x0800
0062 #define MV88E6185_G1_CTL1_MAX_FRAME_1632    0x0400
0063 #define MV88E6185_G1_CTL1_RELOAD_EEPROM     0x0200
0064 #define MV88E6393X_G1_CTL1_DEVICE2_EN       0x0200
0065 #define MV88E6XXX_G1_CTL1_DEVICE_EN     0x0080
0066 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN     0x0040
0067 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN    0x0020
0068 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN       0x0010
0069 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN    0x0008
0070 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN       0x0004
0071 #define MV88E6XXX_G1_CTL1_TCAM_EN       0x0002
0072 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN    0x0001
0073 
0074 /* Offset 0x05: VTU Operation Register */
0075 #define MV88E6XXX_G1_VTU_OP         0x05
0076 #define MV88E6XXX_G1_VTU_OP_BUSY        0x8000
0077 #define MV88E6XXX_G1_VTU_OP_MASK        0x7000
0078 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL       0x1000
0079 #define MV88E6XXX_G1_VTU_OP_NOOP        0x2000
0080 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE  0x3000
0081 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT    0x4000
0082 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE  0x5000
0083 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT    0x6000
0084 #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION   0x7000
0085 #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION    BIT(6)
0086 #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION  BIT(5)
0087 #define MV88E6XXX_G1_VTU_OP_SPID_MASK       0xf
0088 
0089 /* Offset 0x06: VTU VID Register */
0090 #define MV88E6XXX_G1_VTU_VID        0x06
0091 #define MV88E6XXX_G1_VTU_VID_MASK   0x0fff
0092 #define MV88E6390_G1_VTU_VID_PAGE   0x2000
0093 #define MV88E6XXX_G1_VTU_VID_VALID  0x1000
0094 
0095 /* Offset 0x07: VTU/STU Data Register 1
0096  * Offset 0x08: VTU/STU Data Register 2
0097  * Offset 0x09: VTU/STU Data Register 3
0098  */
0099 #define MV88E6XXX_G1_VTU_DATA1              0x07
0100 #define MV88E6XXX_G1_VTU_DATA2              0x08
0101 #define MV88E6XXX_G1_VTU_DATA3              0x09
0102 #define MV88E6XXX_G1_VTU_STU_DATA_MASK          0x0003
0103 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
0104 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED   0x0001
0105 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED     0x0002
0106 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
0107 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED   0x0000
0108 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING   0x0001
0109 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING   0x0002
0110 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
0111 
0112 /* Offset 0x0A: ATU Control Register */
0113 #define MV88E6XXX_G1_ATU_CTL        0x0a
0114 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL  0x0008
0115 #define MV88E6161_G1_ATU_CTL_HASH_MASK  0x0003
0116 
0117 /* Offset 0x0B: ATU Operation Register */
0118 #define MV88E6XXX_G1_ATU_OP             0x0b
0119 #define MV88E6XXX_G1_ATU_OP_BUSY            0x8000
0120 #define MV88E6XXX_G1_ATU_OP_MASK            0x7000
0121 #define MV88E6XXX_G1_ATU_OP_NOOP            0x0000
0122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL      0x1000
0123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC   0x2000
0124 #define MV88E6XXX_G1_ATU_OP_LOAD_DB         0x3000
0125 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB         0x4000
0126 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB       0x5000
0127 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB    0x6000
0128 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION       0x7000
0129 #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION       BIT(7)
0130 #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION        BIT(6)
0131 #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION      BIT(5)
0132 #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION      BIT(4)
0133 
0134 /* Offset 0x0C: ATU Data Register */
0135 #define MV88E6XXX_G1_ATU_DATA                   0x0c
0136 #define MV88E6XXX_G1_ATU_DATA_TRUNK             0x8000
0137 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK         0x00f0
0138 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK          0x3ff0
0139 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK            0x000f
0140 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED           0x0000
0141 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST     0x0001
0142 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2            0x0002
0143 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3            0x0003
0144 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4            0x0004
0145 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5            0x0005
0146 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6            0x0006
0147 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST     0x0007
0148 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY        0x0008
0149 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO     0x0009
0150 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL       0x000a
0151 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO    0x000b
0152 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT       0x000c
0153 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO    0x000d
0154 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC           0x000e
0155 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO        0x000f
0156 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED           0x0000
0157 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY        0x0004
0158 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL       0x0005
0159 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT       0x0006
0160 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC           0x0007
0161 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO     0x000c
0162 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO    0x000d
0163 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO    0x000e
0164 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO        0x000f
0165 
0166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
0167  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
0168  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
0169  */
0170 #define MV88E6XXX_G1_ATU_MAC01      0x0d
0171 #define MV88E6XXX_G1_ATU_MAC23      0x0e
0172 #define MV88E6XXX_G1_ATU_MAC45      0x0f
0173 
0174 /* Offset 0x10: IP-PRI Mapping Register 0
0175  * Offset 0x11: IP-PRI Mapping Register 1
0176  * Offset 0x12: IP-PRI Mapping Register 2
0177  * Offset 0x13: IP-PRI Mapping Register 3
0178  * Offset 0x14: IP-PRI Mapping Register 4
0179  * Offset 0x15: IP-PRI Mapping Register 5
0180  * Offset 0x16: IP-PRI Mapping Register 6
0181  * Offset 0x17: IP-PRI Mapping Register 7
0182  */
0183 #define MV88E6XXX_G1_IP_PRI_0   0x10
0184 #define MV88E6XXX_G1_IP_PRI_1   0x11
0185 #define MV88E6XXX_G1_IP_PRI_2   0x12
0186 #define MV88E6XXX_G1_IP_PRI_3   0x13
0187 #define MV88E6XXX_G1_IP_PRI_4   0x14
0188 #define MV88E6XXX_G1_IP_PRI_5   0x15
0189 #define MV88E6XXX_G1_IP_PRI_6   0x16
0190 #define MV88E6XXX_G1_IP_PRI_7   0x17
0191 
0192 /* Offset 0x18: IEEE-PRI Register */
0193 #define MV88E6XXX_G1_IEEE_PRI   0x18
0194 
0195 /* Offset 0x19: Core Tag Type */
0196 #define MV88E6185_G1_CORE_TAG_TYPE  0x19
0197 
0198 /* Offset 0x1A: Monitor Control */
0199 #define MV88E6185_G1_MONITOR_CTL            0x1a
0200 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK  0xf000
0201 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK   0x0f00
0202 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK          0x00f0
0203 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK          0x00f0
0204 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK   0x000f
0205 
0206 /* Offset 0x1A: Monitor & MGMT Control Register */
0207 #define MV88E6390_G1_MONITOR_MGMT_CTL               0x1a
0208 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE            0x8000
0209 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK          0x3f00
0210 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO    0x0000
0211 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI    0x0100
0212 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO    0x0200
0213 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI    0x0300
0214 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST      0x2000
0215 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST       0x2100
0216 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST      0x3000
0217 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI  0x00e0
0218 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK         0x00ff
0219 
0220 /* Offset 0x1C: Global Control 2 */
0221 #define MV88E6XXX_G1_CTL2           0x1c
0222 #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
0223 #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
0224 #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI    0xf000
0225 #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK  0xc000
0226 #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG  0x0000
0227 #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT  0x4000
0228 #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG   0x8000
0229 #define MV88E6352_G1_CTL2_RMU_MODE_MASK     0x3000
0230 #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
0231 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4   0x1000
0232 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5   0x2000
0233 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6   0x3000
0234 #define MV88E6085_G1_CTL2_DA_CHECK      0x4000
0235 #define MV88E6085_G1_CTL2_P10RM         0x2000
0236 #define MV88E6085_G1_CTL2_RM_ENABLE     0x1000
0237 #define MV88E6352_G1_CTL2_DA_CHECK      0x0800
0238 #define MV88E6390_G1_CTL2_RMU_MODE_MASK     0x0700
0239 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0   0x0000
0240 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1   0x0100
0241 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9   0x0200
0242 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10  0x0300
0243 #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA  0x0600
0244 #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
0245 #define MV88E6390_G1_CTL2_HIST_MODE_MASK    0x00c0
0246 #define MV88E6390_G1_CTL2_HIST_MODE_RX      0x0040
0247 #define MV88E6390_G1_CTL2_HIST_MODE_TX      0x0080
0248 #define MV88E6352_G1_CTL2_CTR_MODE_MASK     0x0060
0249 #define MV88E6390_G1_CTL2_CTR_MODE      0x0020
0250 #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK    0x001f
0251 
0252 /* Offset 0x1D: Stats Operation Register */
0253 #define MV88E6XXX_G1_STATS_OP           0x1d
0254 #define MV88E6XXX_G1_STATS_OP_BUSY      0x8000
0255 #define MV88E6XXX_G1_STATS_OP_NOP       0x0000
0256 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL     0x1000
0257 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT    0x2000
0258 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
0259 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT  0x5000
0260 #define MV88E6XXX_G1_STATS_OP_HIST_RX       0x0400
0261 #define MV88E6XXX_G1_STATS_OP_HIST_TX       0x0800
0262 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX    0x0c00
0263 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9  0x0200
0264 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
0265 
0266 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
0267  * Offset 0x1F: Stats Counter Register Bytes 1 & 0
0268  */
0269 #define MV88E6XXX_G1_STATS_COUNTER_32   0x1e
0270 #define MV88E6XXX_G1_STATS_COUNTER_01   0x1f
0271 
0272 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
0273 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
0274 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
0275               bit, int val);
0276 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
0277                u16 mask, u16 val);
0278 
0279 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
0280 
0281 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
0282 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
0283 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
0284 void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip);
0285 
0286 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
0287 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
0288 
0289 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
0290 
0291 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
0292 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
0293 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
0294 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
0295 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
0296 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
0297 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
0298 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
0299                  enum mv88e6xxx_egress_direction direction,
0300                  int port);
0301 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
0302                  enum mv88e6xxx_egress_direction direction,
0303                  int port);
0304 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
0305 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
0306 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
0307 
0308 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
0309 
0310 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
0311 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
0312 
0313 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
0314 
0315 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
0316 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
0317 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
0318 
0319 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
0320 
0321 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
0322 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
0323                   unsigned int msecs);
0324 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
0325                  struct mv88e6xxx_atu_entry *entry);
0326 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
0327                    struct mv88e6xxx_atu_entry *entry);
0328 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
0329 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
0330                 bool all);
0331 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
0332 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
0333 int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
0334 int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
0335 
0336 int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
0337                  struct mv88e6xxx_vtu_entry *entry);
0338 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
0339                  struct mv88e6xxx_vtu_entry *entry);
0340 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
0341                    struct mv88e6xxx_vtu_entry *entry);
0342 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
0343                  struct mv88e6xxx_vtu_entry *entry);
0344 int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
0345                    struct mv88e6xxx_vtu_entry *entry);
0346 int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
0347                  struct mv88e6xxx_vtu_entry *entry);
0348 int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
0349                    struct mv88e6xxx_vtu_entry *entry);
0350 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
0351 int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip,
0352                  struct mv88e6xxx_stu_entry *entry);
0353 int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip,
0354                  struct mv88e6xxx_stu_entry *entry);
0355 int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
0356                    struct mv88e6xxx_stu_entry *entry);
0357 int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip,
0358                  struct mv88e6xxx_stu_entry *entry);
0359 int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
0360                    struct mv88e6xxx_stu_entry *entry);
0361 int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
0362 void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
0363 int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
0364 
0365 #endif /* _MV88E6XXX_GLOBAL1_H */
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