dsa/mv88e6xxx/chip.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Marvell 88E6xxx Ethernet switch single-chip definition
0004  *
0005  * Copyright (c) 2008 Marvell Semiconductor
0006  */
0007
0008 #ifndef _MV88E6XXX_CHIP_H
0009 #define _MV88E6XXX_CHIP_H
0010
0011 #include <linux/idr.h>
0012 #include <linux/if_vlan.h>
0013 #include <linux/irq.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/kthread.h>
0016 #include <linux/phy.h>
0017 #include <linux/ptp_clock_kernel.h>
0018 #include <linux/timecounter.h>
0019 #include <net/dsa.h>
0020
0021 #define EDSA_HLEN       8
0022 #define MV88E6XXX_N_FID     4096
0023 #define MV88E6XXX_N_SID     64
0024
0025 #define MV88E6XXX_FID_STANDALONE    0
0026 #define MV88E6XXX_FID_BRIDGED       1
0027
0028 /* PVT limits for 4-bit port and 5-bit switch */
0029 #define MV88E6XXX_MAX_PVT_SWITCHES  32
0030 #define MV88E6XXX_MAX_PVT_PORTS     16
0031 #define MV88E6XXX_MAX_PVT_ENTRIES   \
0032     (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
0033
0034 #define MV88E6XXX_MAX_GPIO  16
0035
0036 enum mv88e6xxx_egress_mode {
0037     MV88E6XXX_EGRESS_MODE_UNMODIFIED,
0038     MV88E6XXX_EGRESS_MODE_UNTAGGED,
0039     MV88E6XXX_EGRESS_MODE_TAGGED,
0040     MV88E6XXX_EGRESS_MODE_ETHERTYPE,
0041 };
0042
0043 enum mv88e6xxx_egress_direction {
0044         MV88E6XXX_EGRESS_DIR_INGRESS,
0045         MV88E6XXX_EGRESS_DIR_EGRESS,
0046 };
0047
0048 enum mv88e6xxx_frame_mode {
0049     MV88E6XXX_FRAME_MODE_NORMAL,
0050     MV88E6XXX_FRAME_MODE_DSA,
0051     MV88E6XXX_FRAME_MODE_PROVIDER,
0052     MV88E6XXX_FRAME_MODE_ETHERTYPE,
0053 };
0054
0055 /* List of supported models */
0056 enum mv88e6xxx_model {
0057     MV88E6085,
0058     MV88E6095,
0059     MV88E6097,
0060     MV88E6123,
0061     MV88E6131,
0062     MV88E6141,
0063     MV88E6161,
0064     MV88E6165,
0065     MV88E6171,
0066     MV88E6172,
0067     MV88E6175,
0068     MV88E6176,
0069     MV88E6185,
0070     MV88E6190,
0071     MV88E6190X,
0072     MV88E6191,
0073     MV88E6191X,
0074     MV88E6193X,
0075     MV88E6220,
0076     MV88E6240,
0077     MV88E6250,
0078     MV88E6290,
0079     MV88E6320,
0080     MV88E6321,
0081     MV88E6341,
0082     MV88E6350,
0083     MV88E6351,
0084     MV88E6352,
0085     MV88E6390,
0086     MV88E6390X,
0087     MV88E6393X,
0088 };
0089
0090 enum mv88e6xxx_family {
0091     MV88E6XXX_FAMILY_NONE,
0092     MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
0093     MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
0094     MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
0095     MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
0096     MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
0097     MV88E6XXX_FAMILY_6250,  /* 6220 6250 */
0098     MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
0099     MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
0100     MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
0101     MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
0102     MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
0103     MV88E6XXX_FAMILY_6393,  /* 6191X 6193X 6393X */
0104 };
0105
0106 /**
0107  * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
0108  * @MV88E6XXX_EDSA_UNSUPPORTED:  Device has no support for EDSA tags
0109  * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
0110  *                               egressing FORWARD frames with an EDSA
0111  *                               tag is reserved for future use, but
0112  *                               empirical data shows that this mode
0113  *                               is supported.
0114  * @MV88E6XXX_EDSA_SUPPORTED:    EDSA tags are fully supported.
0115  */
0116 enum mv88e6xxx_edsa_support {
0117     MV88E6XXX_EDSA_UNSUPPORTED = 0,
0118     MV88E6XXX_EDSA_UNDOCUMENTED,
0119     MV88E6XXX_EDSA_SUPPORTED,
0120 };
0121
0122 struct mv88e6xxx_ops;
0123
0124 struct mv88e6xxx_info {
0125     enum mv88e6xxx_family family;
0126     u16 prod_num;
0127     const char *name;
0128     unsigned int num_databases;
0129     unsigned int num_macs;
0130     unsigned int num_ports;
0131     unsigned int num_internal_phys;
0132     unsigned int num_gpio;
0133     unsigned int max_vid;
0134     unsigned int max_sid;
0135     unsigned int port_base_addr;
0136     unsigned int phy_base_addr;
0137     unsigned int global1_addr;
0138     unsigned int global2_addr;
0139     unsigned int age_time_coeff;
0140     unsigned int g1_irqs;
0141     unsigned int g2_irqs;
0142     bool pvt;
0143
0144     /* Mark certain ports as invalid. This is required for example for the
0145      * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
0146      * ports 2-4 are not routet to pins.
0147      */
0148     unsigned int invalid_port_mask;
0149     /* Multi-chip Addressing Mode.
0150      * Some chips respond to only 2 registers of its own SMI device address
0151      * when it is non-zero, and use indirect access to internal registers.
0152      */
0153     bool multi_chip;
0154     /* Dual-chip Addressing Mode
0155      * Some chips respond to only half of the 32 SMI addresses,
0156      * allowing two to coexist on the same SMI interface.
0157      */
0158     bool dual_chip;
0159
0160     enum mv88e6xxx_edsa_support edsa_support;
0161
0162     /* Mask for FromPort and ToPort value of PortVec used in ATU Move
0163      * operation. 0 means that the ATU Move operation is not supported.
0164      */
0165     u8 atu_move_port_mask;
0166     const struct mv88e6xxx_ops *ops;
0167
0168     /* Supports PTP */
0169     bool ptp_support;
0170 };
0171
0172 struct mv88e6xxx_atu_entry {
0173     u8  state;
0174     bool    trunk;
0175     u16 portvec;
0176     u8  mac[ETH_ALEN];
0177 };
0178
0179 struct mv88e6xxx_vtu_entry {
0180     u16 vid;
0181     u16 fid;
0182     u8  sid;
0183     bool    valid;
0184     bool    policy;
0185     u8  member[DSA_MAX_PORTS];
0186     u8  state[DSA_MAX_PORTS];   /* Older silicon has no STU */
0187 };
0188
0189 struct mv88e6xxx_stu_entry {
0190     u8  sid;
0191     bool    valid;
0192     u8  state[DSA_MAX_PORTS];
0193 };
0194
0195 struct mv88e6xxx_bus_ops;
0196 struct mv88e6xxx_irq_ops;
0197 struct mv88e6xxx_gpio_ops;
0198 struct mv88e6xxx_avb_ops;
0199 struct mv88e6xxx_ptp_ops;
0200
0201 struct mv88e6xxx_irq {
0202     u16 masked;
0203     struct irq_chip chip;
0204     struct irq_domain *domain;
0205     int nirqs;
0206 };
0207
0208 /* state flags for mv88e6xxx_port_hwtstamp::state */
0209 enum {
0210     MV88E6XXX_HWTSTAMP_ENABLED,
0211     MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
0212 };
0213
0214 struct mv88e6xxx_port_hwtstamp {
0215     /* Port index */
0216     int port_id;
0217
0218     /* Timestamping state */
0219     unsigned long state;
0220
0221     /* Resources for receive timestamping */
0222     struct sk_buff_head rx_queue;
0223     struct sk_buff_head rx_queue2;
0224
0225     /* Resources for transmit timestamping */
0226     unsigned long tx_tstamp_start;
0227     struct sk_buff *tx_skb;
0228     u16 tx_seq_id;
0229
0230     /* Current timestamp configuration */
0231     struct hwtstamp_config tstamp_config;
0232 };
0233
0234 enum mv88e6xxx_policy_mapping {
0235     MV88E6XXX_POLICY_MAPPING_DA,
0236     MV88E6XXX_POLICY_MAPPING_SA,
0237     MV88E6XXX_POLICY_MAPPING_VTU,
0238     MV88E6XXX_POLICY_MAPPING_ETYPE,
0239     MV88E6XXX_POLICY_MAPPING_PPPOE,
0240     MV88E6XXX_POLICY_MAPPING_VBAS,
0241     MV88E6XXX_POLICY_MAPPING_OPT82,
0242     MV88E6XXX_POLICY_MAPPING_UDP,
0243 };
0244
0245 enum mv88e6xxx_policy_action {
0246     MV88E6XXX_POLICY_ACTION_NORMAL,
0247     MV88E6XXX_POLICY_ACTION_MIRROR,
0248     MV88E6XXX_POLICY_ACTION_TRAP,
0249     MV88E6XXX_POLICY_ACTION_DISCARD,
0250 };
0251
0252 struct mv88e6xxx_policy {
0253     enum mv88e6xxx_policy_mapping mapping;
0254     enum mv88e6xxx_policy_action action;
0255     struct ethtool_rx_flow_spec fs;
0256     u8 addr[ETH_ALEN];
0257     int port;
0258     u16 vid;
0259 };
0260
0261 struct mv88e6xxx_vlan {
0262     u16 vid;
0263     bool    valid;
0264 };
0265
0266 struct mv88e6xxx_port {
0267     struct mv88e6xxx_chip *chip;
0268     int port;
0269     struct mv88e6xxx_vlan bridge_pvid;
0270     u64 serdes_stats[2];
0271     u64 atu_member_violation;
0272     u64 atu_miss_violation;
0273     u64 atu_full_violation;
0274     u64 vtu_member_violation;
0275     u64 vtu_miss_violation;
0276     phy_interface_t interface;
0277     u8 cmode;
0278     bool mirror_ingress;
0279     bool mirror_egress;
0280     unsigned int serdes_irq;
0281     char serdes_irq_name[64];
0282     struct devlink_region *region;
0283 };
0284
0285 enum mv88e6xxx_region_id {
0286     MV88E6XXX_REGION_GLOBAL1 = 0,
0287     MV88E6XXX_REGION_GLOBAL2,
0288     MV88E6XXX_REGION_ATU,
0289     MV88E6XXX_REGION_VTU,
0290     MV88E6XXX_REGION_STU,
0291     MV88E6XXX_REGION_PVT,
0292
0293     _MV88E6XXX_REGION_MAX,
0294 };
0295
0296 struct mv88e6xxx_region_priv {
0297     enum mv88e6xxx_region_id id;
0298 };
0299
0300 struct mv88e6xxx_mst {
0301     struct list_head node;
0302
0303     refcount_t refcnt;
0304     struct net_device *br;
0305     u16 msti;
0306
0307     struct mv88e6xxx_stu_entry stu;
0308 };
0309
0310 struct mv88e6xxx_chip {
0311     const struct mv88e6xxx_info *info;
0312
0313     /* Currently configured tagging protocol */
0314     enum dsa_tag_protocol tag_protocol;
0315
0316     /* The dsa_switch this private structure is related to */
0317     struct dsa_switch *ds;
0318
0319     /* The device this structure is associated to */
0320     struct device *dev;
0321
0322     /* This mutex protects the access to the switch registers */
0323     struct mutex reg_lock;
0324
0325     /* The MII bus and the address on the bus that is used to
0326      * communication with the switch
0327      */
0328     const struct mv88e6xxx_bus_ops *smi_ops;
0329     struct mii_bus *bus;
0330     int sw_addr;
0331
0332     /* Handles automatic disabling and re-enabling of the PHY
0333      * polling unit.
0334      */
0335     const struct mv88e6xxx_bus_ops *phy_ops;
0336     struct mutex        ppu_mutex;
0337     int         ppu_disabled;
0338     struct work_struct  ppu_work;
0339     struct timer_list   ppu_timer;
0340
0341     /* This mutex serialises access to the statistics unit.
0342      * Hold this mutex over snapshot + dump sequences.
0343      */
0344     struct mutex    stats_mutex;
0345
0346     /* A switch may have a GPIO line tied to its reset pin. Parse
0347      * this from the device tree, and use it before performing
0348      * switch soft reset.
0349      */
0350     struct gpio_desc *reset;
0351
0352     /* set to size of eeprom if supported by the switch */
0353     u32 eeprom_len;
0354
0355     /* List of mdio busses */
0356     struct list_head mdios;
0357
0358     /* Policy Control List IDs and rules */
0359     struct idr policies;
0360
0361     /* There can be two interrupt controllers, which are chained
0362      * off a GPIO as interrupt source
0363      */
0364     struct mv88e6xxx_irq g1_irq;
0365     struct mv88e6xxx_irq g2_irq;
0366     int irq;
0367     char irq_name[64];
0368     int device_irq;
0369     char device_irq_name[64];
0370     int watchdog_irq;
0371     char watchdog_irq_name[64];
0372
0373     int atu_prob_irq;
0374     char atu_prob_irq_name[64];
0375     int vtu_prob_irq;
0376     char vtu_prob_irq_name[64];
0377     struct kthread_worker *kworker;
0378     struct kthread_delayed_work irq_poll_work;
0379
0380     /* GPIO resources */
0381     u8 gpio_data[2];
0382
0383     /* This cyclecounter abstracts the switch PTP time.
0384      * reg_lock must be held for any operation that read()s.
0385      */
0386     struct cyclecounter tstamp_cc;
0387     struct timecounter  tstamp_tc;
0388     struct delayed_work overflow_work;
0389
0390     struct ptp_clock    *ptp_clock;
0391     struct ptp_clock_info   ptp_clock_info;
0392     struct delayed_work tai_event_work;
0393     struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
0394     u16 trig_config;
0395     u16 evcap_config;
0396     u16 enable_count;
0397
0398     /* Current ingress and egress monitor ports */
0399     int egress_dest_port;
0400     int ingress_dest_port;
0401
0402     /* Per-port timestamping resources. */
0403     struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
0404
0405     /* Array of port structures. */
0406     struct mv88e6xxx_port ports[DSA_MAX_PORTS];
0407
0408     /* devlink regions */
0409     struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
0410
0411     /* Bridge MST to SID mappings */
0412     struct list_head msts;
0413 };
0414
0415 struct mv88e6xxx_bus_ops {
0416     int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
0417     int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
0418     int (*init)(struct mv88e6xxx_chip *chip);
0419 };
0420
0421 struct mv88e6xxx_mdio_bus {
0422     struct mii_bus *bus;
0423     struct mv88e6xxx_chip *chip;
0424     struct list_head list;
0425     bool external;
0426 };
0427
0428 struct mv88e6xxx_ops {
0429     /* Switch Setup Errata, called early in the switch setup to
0430      * allow any errata actions to be performed
0431      */
0432     int (*setup_errata)(struct mv88e6xxx_chip *chip);
0433
0434     int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
0435     int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
0436
0437     /* Ingress Rate Limit unit (IRL) operations */
0438     int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
0439
0440     int (*get_eeprom)(struct mv88e6xxx_chip *chip,
0441               struct ethtool_eeprom *eeprom, u8 *data);
0442     int (*set_eeprom)(struct mv88e6xxx_chip *chip,
0443               struct ethtool_eeprom *eeprom, u8 *data);
0444
0445     int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
0446
0447     int (*phy_read)(struct mv88e6xxx_chip *chip,
0448             struct mii_bus *bus,
0449             int addr, int reg, u16 *val);
0450     int (*phy_write)(struct mv88e6xxx_chip *chip,
0451              struct mii_bus *bus,
0452              int addr, int reg, u16 val);
0453
0454     /* Priority Override Table operations */
0455     int (*pot_clear)(struct mv88e6xxx_chip *chip);
0456
0457     /* PHY Polling Unit (PPU) operations */
0458     int (*ppu_enable)(struct mv88e6xxx_chip *chip);
0459     int (*ppu_disable)(struct mv88e6xxx_chip *chip);
0460
0461     /* Switch Software Reset */
0462     int (*reset)(struct mv88e6xxx_chip *chip);
0463
0464     /* RGMII Receive/Transmit Timing Control
0465      * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
0466      */
0467     int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
0468                     phy_interface_t mode);
0469
0470 #define LINK_FORCED_DOWN    0
0471 #define LINK_FORCED_UP      1
0472 #define LINK_UNFORCED       -2
0473
0474     /* Port's MAC link state
0475      * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
0476      * or LINK_UNFORCED for normal link detection.
0477      */
0478     int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
0479
0480     /* Synchronise the port link state with that of the SERDES
0481      */
0482     int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
0483
0484 #define PAUSE_ON        1
0485 #define PAUSE_OFF       0
0486
0487     /* Enable/disable sending Pause */
0488     int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
0489                   int pause);
0490
0491 #define SPEED_UNFORCED      -2
0492 #define DUPLEX_UNFORCED     -2
0493
0494     /* Port's MAC speed (in Mbps) and MAC duplex mode
0495      *
0496      * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
0497      * Use SPEED_UNFORCED for normal detection.
0498      *
0499      * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
0500      * or DUPLEX_UNFORCED for normal duplex detection.
0501      */
0502     int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
0503                      int speed, int duplex);
0504
0505     /* What interface mode should be used for maximum speed? */
0506     phy_interface_t (*port_max_speed_mode)(int port);
0507
0508     int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
0509
0510     int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
0511                    enum mv88e6xxx_policy_mapping mapping,
0512                    enum mv88e6xxx_policy_action action);
0513
0514     int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
0515                    enum mv88e6xxx_frame_mode mode);
0516     int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
0517                     bool unicast);
0518     int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
0519                     bool multicast);
0520     int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
0521                    u16 etype);
0522     int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
0523                    size_t size);
0524
0525     int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
0526     int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
0527                 u8 out);
0528     int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
0529     int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
0530     int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
0531
0532     /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
0533      * Some chips allow this to be configured on specific ports.
0534      */
0535     int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
0536                   phy_interface_t mode);
0537     int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
0538
0539     /* Some devices have a per port register indicating what is
0540      * the upstream port this port should forward to.
0541      */
0542     int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
0543                       int upstream_port);
0544
0545     /* Snapshot the statistics for a port. The statistics can then
0546      * be read back a leisure but still with a consistent view.
0547      */
0548     int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
0549
0550     /* Set the histogram mode for statistics, when the control registers
0551      * are separated out of the STATS_OP register.
0552      */
0553     int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
0554
0555     /* Return the number of strings describing statistics */
0556     int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
0557     int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
0558     int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
0559                    uint64_t *data);
0560     int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
0561     int (*set_egress_port)(struct mv88e6xxx_chip *chip,
0562                    enum mv88e6xxx_egress_direction direction,
0563                    int port);
0564
0565 #define MV88E6XXX_CASCADE_PORT_NONE     0xe
0566 #define MV88E6XXX_CASCADE_PORT_MULTIPLE     0xf
0567
0568     int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
0569
0570     const struct mv88e6xxx_irq_ops *watchdog_ops;
0571
0572     int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
0573
0574     /* Power on/off a SERDES interface */
0575     int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
0576                 bool up);
0577
0578     /* SERDES lane mapping */
0579     int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
0580
0581     int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
0582                     int lane, struct phylink_link_state *state);
0583     int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
0584                  int lane, unsigned int mode,
0585                  phy_interface_t interface,
0586                  const unsigned long *advertise);
0587     int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
0588                      int lane);
0589     int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
0590                   int lane, int speed, int duplex);
0591
0592     /* SERDES interrupt handling */
0593     unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
0594                        int port);
0595     int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
0596                  bool enable);
0597     irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
0598                      int lane);
0599
0600     /* Statistics from the SERDES interface */
0601     int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
0602     int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
0603                   uint8_t *data);
0604     int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
0605                 uint64_t *data);
0606
0607     /* SERDES registers for ethtool */
0608     int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
0609     void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
0610                 void *_p);
0611
0612     /* SERDES SGMII/Fiber Output Amplitude */
0613     int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
0614                        int val);
0615
0616     /* Address Translation Unit operations */
0617     int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
0618     int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
0619
0620     /* VLAN Translation Unit operations */
0621     int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
0622                struct mv88e6xxx_vtu_entry *entry);
0623     int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
0624                  struct mv88e6xxx_vtu_entry *entry);
0625
0626     /* Spanning Tree Unit operations */
0627     int (*stu_getnext)(struct mv88e6xxx_chip *chip,
0628                struct mv88e6xxx_stu_entry *entry);
0629     int (*stu_loadpurge)(struct mv88e6xxx_chip *chip,
0630                  struct mv88e6xxx_stu_entry *entry);
0631
0632     /* GPIO operations */
0633     const struct mv88e6xxx_gpio_ops *gpio_ops;
0634
0635     /* Interface to the AVB/PTP registers */
0636     const struct mv88e6xxx_avb_ops *avb_ops;
0637
0638     /* Remote Management Unit operations */
0639     int (*rmu_disable)(struct mv88e6xxx_chip *chip);
0640
0641     /* Precision Time Protocol operations */
0642     const struct mv88e6xxx_ptp_ops *ptp_ops;
0643
0644     /* Phylink */
0645     void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
0646                  struct phylink_config *config);
0647
0648     /* Max Frame Size */
0649     int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
0650 };
0651
0652 struct mv88e6xxx_irq_ops {
0653     /* Action to be performed when the interrupt happens */
0654     int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
0655     /* Setup the hardware to generate the interrupt */
0656     int (*irq_setup)(struct mv88e6xxx_chip *chip);
0657     /* Reset the hardware to stop generating the interrupt */
0658     void (*irq_free)(struct mv88e6xxx_chip *chip);
0659 };
0660
0661 struct mv88e6xxx_gpio_ops {
0662     /* Get/set data on GPIO pin */
0663     int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
0664     int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
0665             int value);
0666
0667     /* get/set GPIO direction */
0668     int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
0669     int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
0670                bool input);
0671
0672     /* get/set GPIO pin control */
0673     int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
0674             int *func);
0675     int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
0676             int func);
0677 };
0678
0679 struct mv88e6xxx_avb_ops {
0680     /* Access port-scoped Precision Time Protocol registers */
0681     int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
0682                  u16 *data, int len);
0683     int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
0684                   u16 data);
0685
0686     /* Access global Precision Time Protocol registers */
0687     int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
0688             int len);
0689     int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
0690
0691     /* Access global Time Application Interface registers */
0692     int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
0693             int len);
0694     int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
0695 };
0696
0697 struct mv88e6xxx_ptp_ops {
0698     u64 (*clock_read)(const struct cyclecounter *cc);
0699     int (*ptp_enable)(struct ptp_clock_info *ptp,
0700               struct ptp_clock_request *rq, int on);
0701     int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
0702               enum ptp_pin_function func, unsigned int chan);
0703     void (*event_work)(struct work_struct *ugly);
0704     int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
0705     int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
0706     int (*global_enable)(struct mv88e6xxx_chip *chip);
0707     int (*global_disable)(struct mv88e6xxx_chip *chip);
0708     int n_ext_ts;
0709     int arr0_sts_reg;
0710     int arr1_sts_reg;
0711     int dep_sts_reg;
0712     u32 rx_filters;
0713     u32 cc_shift;
0714     u32 cc_mult;
0715     u32 cc_mult_num;
0716     u32 cc_mult_dem;
0717 };
0718
0719 #define STATS_TYPE_PORT     BIT(0)
0720 #define STATS_TYPE_BANK0    BIT(1)
0721 #define STATS_TYPE_BANK1    BIT(2)
0722
0723 struct mv88e6xxx_hw_stat {
0724     char string[ETH_GSTRING_LEN];
0725     size_t size;
0726     int reg;
0727     int type;
0728 };
0729
0730 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)
0731 {
0732     return chip->info->max_sid > 0 &&
0733         chip->info->ops->stu_loadpurge &&
0734         chip->info->ops->stu_getnext;
0735 }
0736
0737 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
0738 {
0739     return chip->info->pvt;
0740 }
0741
0742 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
0743 {
0744     return !!chip->info->global2_addr;
0745 }
0746
0747 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
0748 {
0749     return chip->info->num_databases;
0750 }
0751
0752 static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
0753 {
0754     return chip->info->num_macs;
0755 }
0756
0757 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
0758 {
0759     return chip->info->num_ports;
0760 }
0761
0762 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
0763 {
0764     return chip->info->max_vid;
0765 }
0766
0767 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip)
0768 {
0769     return chip->info->max_sid;
0770 }
0771
0772 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
0773 {
0774     return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
0775 }
0776
0777 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
0778 {
0779     return chip->info->num_gpio;
0780 }
0781
0782 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
0783 {
0784     return (chip->info->invalid_port_mask & BIT(port)) != 0;
0785 }
0786
0787 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
0788 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
0789 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
0790             u16 mask, u16 val);
0791 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
0792                int bit, int val);
0793 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
0794
0795 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
0796 {
0797     mutex_lock(&chip->reg_lock);
0798 }
0799
0800 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
0801 {
0802     mutex_unlock(&chip->reg_lock);
0803 }
0804
0805 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
0806
0807 #endif /* _MV88E6XXX_CHIP_H */