net/dsa/mv88e6060.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
0004  * Copyright (c) 2015 Neil Armstrong
0005  *
0006  * Based on mv88e6xxx.h
0007  * Copyright (c) 2008 Marvell Semiconductor
0008  */
0009
0010 #ifndef __MV88E6060_H
0011 #define __MV88E6060_H
0012
0013 #define MV88E6060_PORTS 6
0014
0015 #define REG_PORT(p)     (0x8 + (p))
0016 #define PORT_STATUS     0x00
0017 #define PORT_STATUS_PAUSE_EN    BIT(15)
0018 #define PORT_STATUS_MY_PAUSE    BIT(14)
0019 #define PORT_STATUS_FC      (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
0020 #define PORT_STATUS_RESOLVED    BIT(13)
0021 #define PORT_STATUS_LINK    BIT(12)
0022 #define PORT_STATUS_PORTMODE    BIT(11)
0023 #define PORT_STATUS_PHYMODE BIT(10)
0024 #define PORT_STATUS_DUPLEX  BIT(9)
0025 #define PORT_STATUS_SPEED   BIT(8)
0026 #define PORT_SWITCH_ID      0x03
0027 #define PORT_SWITCH_ID_6060 0x0600
0028 #define PORT_SWITCH_ID_6060_MASK    0xfff0
0029 #define PORT_SWITCH_ID_6060_R1  0x0601
0030 #define PORT_SWITCH_ID_6060_R2  0x0602
0031 #define PORT_CONTROL        0x04
0032 #define PORT_CONTROL_FORCE_FLOW_CTRL    BIT(15)
0033 #define PORT_CONTROL_TRAILER    BIT(14)
0034 #define PORT_CONTROL_HEADER BIT(11)
0035 #define PORT_CONTROL_INGRESS_MODE   BIT(8)
0036 #define PORT_CONTROL_VLAN_TUNNEL    BIT(7)
0037 #define PORT_CONTROL_STATE_MASK 0x03
0038 #define PORT_CONTROL_STATE_DISABLED 0x00
0039 #define PORT_CONTROL_STATE_BLOCKING 0x01
0040 #define PORT_CONTROL_STATE_LEARNING 0x02
0041 #define PORT_CONTROL_STATE_FORWARDING   0x03
0042 #define PORT_VLAN_MAP       0x06
0043 #define PORT_VLAN_MAP_DBNUM_SHIFT   12
0044 #define PORT_VLAN_MAP_TABLE_MASK    0x1f
0045 #define PORT_ASSOC_VECTOR   0x0b
0046 #define PORT_ASSOC_VECTOR_MONITOR   BIT(15)
0047 #define PORT_ASSOC_VECTOR_PAV_MASK  0x1f
0048 #define PORT_RX_CNTR        0x10
0049 #define PORT_TX_CNTR        0x11
0050
0051 #define REG_GLOBAL      0x0f
0052 #define GLOBAL_STATUS       0x00
0053 #define GLOBAL_STATUS_SW_MODE_MASK  (0x3 << 12)
0054 #define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12)
0055 #define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12)
0056 #define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12)
0057 #define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12)
0058 #define GLOBAL_STATUS_INIT_READY    BIT(11)
0059 #define GLOBAL_STATUS_ATU_FULL      BIT(3)
0060 #define GLOBAL_STATUS_ATU_DONE      BIT(2)
0061 #define GLOBAL_STATUS_PHY_INT   BIT(1)
0062 #define GLOBAL_STATUS_EEINT BIT(0)
0063 #define GLOBAL_MAC_01       0x01
0064 #define GLOBAL_MAC_01_DIFF_ADDR BIT(8)
0065 #define GLOBAL_MAC_23       0x02
0066 #define GLOBAL_MAC_45       0x03
0067 #define GLOBAL_CONTROL      0x04
0068 #define GLOBAL_CONTROL_DISCARD_EXCESS   BIT(13)
0069 #define GLOBAL_CONTROL_MAX_FRAME_1536   BIT(10)
0070 #define GLOBAL_CONTROL_RELOAD_EEPROM    BIT(9)
0071 #define GLOBAL_CONTROL_CTRMODE      BIT(8)
0072 #define GLOBAL_CONTROL_ATU_FULL_EN  BIT(3)
0073 #define GLOBAL_CONTROL_ATU_DONE_EN  BIT(2)
0074 #define GLOBAL_CONTROL_PHYINT_EN    BIT(1)
0075 #define GLOBAL_CONTROL_EEPROM_DONE_EN   BIT(0)
0076 #define GLOBAL_ATU_CONTROL  0x0a
0077 #define GLOBAL_ATU_CONTROL_SWRESET  BIT(15)
0078 #define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14)
0079 #define GLOBAL_ATU_CONTROL_ATUSIZE_256  (0x0 << 12)
0080 #define GLOBAL_ATU_CONTROL_ATUSIZE_512  (0x1 << 12)
0081 #define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12)
0082 #define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT    4
0083 #define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4)
0084 #define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4)
0085 #define GLOBAL_ATU_OP       0x0b
0086 #define GLOBAL_ATU_OP_BUSY  BIT(15)
0087 #define GLOBAL_ATU_OP_NOP       (0 << 12)
0088 #define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
0089 #define GLOBAL_ATU_OP_FLUSH_UNLOCKED    ((2 << 12) | GLOBAL_ATU_OP_BUSY)
0090 #define GLOBAL_ATU_OP_LOAD_DB       ((3 << 12) | GLOBAL_ATU_OP_BUSY)
0091 #define GLOBAL_ATU_OP_GET_NEXT_DB   ((4 << 12) | GLOBAL_ATU_OP_BUSY)
0092 #define GLOBAL_ATU_OP_FLUSH_DB      ((5 << 12) | GLOBAL_ATU_OP_BUSY)
0093 #define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
0094 #define GLOBAL_ATU_DATA     0x0c
0095 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK    0x3f0
0096 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT   4
0097 #define GLOBAL_ATU_DATA_STATE_MASK      0x0f
0098 #define GLOBAL_ATU_DATA_STATE_UNUSED        0x00
0099 #define GLOBAL_ATU_DATA_STATE_UC_STATIC     0x0e
0100 #define GLOBAL_ATU_DATA_STATE_UC_LOCKED     0x0f
0101 #define GLOBAL_ATU_DATA_STATE_MC_STATIC     0x07
0102 #define GLOBAL_ATU_DATA_STATE_MC_LOCKED     0x0e
0103 #define GLOBAL_ATU_MAC_01   0x0d
0104 #define GLOBAL_ATU_MAC_23   0x0e
0105 #define GLOBAL_ATU_MAC_45   0x0f
0106
0107 struct mv88e6060_priv {
0108     /* MDIO bus and address on bus to use. When in single chip
0109      * mode, address is 0, and the switch uses multiple addresses
0110      * on the bus.  When in multi-chip mode, the switch uses a
0111      * single address which contains two registers used for
0112      * indirect access to more registers.
0113      */
0114     struct mii_bus *bus;
0115     int sw_addr;
0116     struct dsa_switch *ds;
0117 };
0118
0119 #endif