net/dsa/mt7530.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Mediatek MT7530 DSA Switch driver
0004  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
0005  */
0006 #include <linux/etherdevice.h>
0007 #include <linux/if_bridge.h>
0008 #include <linux/iopoll.h>
0009 #include <linux/mdio.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/netdevice.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/of_mdio.h>
0015 #include <linux/of_net.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/phylink.h>
0018 #include <linux/regmap.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/reset.h>
0021 #include <linux/gpio/consumer.h>
0022 #include <linux/gpio/driver.h>
0023 #include <net/dsa.h>
0024
0025 #include "mt7530.h"
0026
0027 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
0028 {
0029     return container_of(pcs, struct mt753x_pcs, pcs);
0030 }
0031
0032 /* String, offset, and register size in bytes if different from 4 bytes */
0033 static const struct mt7530_mib_desc mt7530_mib[] = {
0034     MIB_DESC(1, 0x00, "TxDrop"),
0035     MIB_DESC(1, 0x04, "TxCrcErr"),
0036     MIB_DESC(1, 0x08, "TxUnicast"),
0037     MIB_DESC(1, 0x0c, "TxMulticast"),
0038     MIB_DESC(1, 0x10, "TxBroadcast"),
0039     MIB_DESC(1, 0x14, "TxCollision"),
0040     MIB_DESC(1, 0x18, "TxSingleCollision"),
0041     MIB_DESC(1, 0x1c, "TxMultipleCollision"),
0042     MIB_DESC(1, 0x20, "TxDeferred"),
0043     MIB_DESC(1, 0x24, "TxLateCollision"),
0044     MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
0045     MIB_DESC(1, 0x2c, "TxPause"),
0046     MIB_DESC(1, 0x30, "TxPktSz64"),
0047     MIB_DESC(1, 0x34, "TxPktSz65To127"),
0048     MIB_DESC(1, 0x38, "TxPktSz128To255"),
0049     MIB_DESC(1, 0x3c, "TxPktSz256To511"),
0050     MIB_DESC(1, 0x40, "TxPktSz512To1023"),
0051     MIB_DESC(1, 0x44, "Tx1024ToMax"),
0052     MIB_DESC(2, 0x48, "TxBytes"),
0053     MIB_DESC(1, 0x60, "RxDrop"),
0054     MIB_DESC(1, 0x64, "RxFiltering"),
0055     MIB_DESC(1, 0x68, "RxUnicast"),
0056     MIB_DESC(1, 0x6c, "RxMulticast"),
0057     MIB_DESC(1, 0x70, "RxBroadcast"),
0058     MIB_DESC(1, 0x74, "RxAlignErr"),
0059     MIB_DESC(1, 0x78, "RxCrcErr"),
0060     MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
0061     MIB_DESC(1, 0x80, "RxFragErr"),
0062     MIB_DESC(1, 0x84, "RxOverSzErr"),
0063     MIB_DESC(1, 0x88, "RxJabberErr"),
0064     MIB_DESC(1, 0x8c, "RxPause"),
0065     MIB_DESC(1, 0x90, "RxPktSz64"),
0066     MIB_DESC(1, 0x94, "RxPktSz65To127"),
0067     MIB_DESC(1, 0x98, "RxPktSz128To255"),
0068     MIB_DESC(1, 0x9c, "RxPktSz256To511"),
0069     MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
0070     MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
0071     MIB_DESC(2, 0xa8, "RxBytes"),
0072     MIB_DESC(1, 0xb0, "RxCtrlDrop"),
0073     MIB_DESC(1, 0xb4, "RxIngressDrop"),
0074     MIB_DESC(1, 0xb8, "RxArlDrop"),
0075 };
0076
0077 /* Since phy_device has not yet been created and
0078  * phy_{read,write}_mmd_indirect is not available, we provide our own
0079  * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
0080  * to complete this function.
0081  */
0082 static int
0083 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
0084 {
0085     struct mii_bus *bus = priv->bus;
0086     int value, ret;
0087
0088     /* Write the desired MMD Devad */
0089     ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
0090     if (ret < 0)
0091         goto err;
0092
0093     /* Write the desired MMD register address */
0094     ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
0095     if (ret < 0)
0096         goto err;
0097
0098     /* Select the Function : DATA with no post increment */
0099     ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
0100     if (ret < 0)
0101         goto err;
0102
0103     /* Read the content of the MMD's selected register */
0104     value = bus->read(bus, 0, MII_MMD_DATA);
0105
0106     return value;
0107 err:
0108     dev_err(&bus->dev,  "failed to read mmd register\n");
0109
0110     return ret;
0111 }
0112
0113 static int
0114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
0115             int devad, u32 data)
0116 {
0117     struct mii_bus *bus = priv->bus;
0118     int ret;
0119
0120     /* Write the desired MMD Devad */
0121     ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
0122     if (ret < 0)
0123         goto err;
0124
0125     /* Write the desired MMD register address */
0126     ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
0127     if (ret < 0)
0128         goto err;
0129
0130     /* Select the Function : DATA with no post increment */
0131     ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
0132     if (ret < 0)
0133         goto err;
0134
0135     /* Write the data into MMD's selected register */
0136     ret = bus->write(bus, 0, MII_MMD_DATA, data);
0137 err:
0138     if (ret < 0)
0139         dev_err(&bus->dev,
0140             "failed to write mmd register\n");
0141     return ret;
0142 }
0143
0144 static void
0145 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
0146 {
0147     struct mii_bus *bus = priv->bus;
0148
0149     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0150
0151     core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
0152
0153     mutex_unlock(&bus->mdio_lock);
0154 }
0155
0156 static void
0157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
0158 {
0159     struct mii_bus *bus = priv->bus;
0160     u32 val;
0161
0162     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0163
0164     val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
0165     val &= ~mask;
0166     val |= set;
0167     core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
0168
0169     mutex_unlock(&bus->mdio_lock);
0170 }
0171
0172 static void
0173 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
0174 {
0175     core_rmw(priv, reg, 0, val);
0176 }
0177
0178 static void
0179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
0180 {
0181     core_rmw(priv, reg, val, 0);
0182 }
0183
0184 static int
0185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
0186 {
0187     struct mii_bus *bus = priv->bus;
0188     u16 page, r, lo, hi;
0189     int ret;
0190
0191     page = (reg >> 6) & 0x3ff;
0192     r  = (reg >> 2) & 0xf;
0193     lo = val & 0xffff;
0194     hi = val >> 16;
0195
0196     /* MT7530 uses 31 as the pseudo port */
0197     ret = bus->write(bus, 0x1f, 0x1f, page);
0198     if (ret < 0)
0199         goto err;
0200
0201     ret = bus->write(bus, 0x1f, r,  lo);
0202     if (ret < 0)
0203         goto err;
0204
0205     ret = bus->write(bus, 0x1f, 0x10, hi);
0206 err:
0207     if (ret < 0)
0208         dev_err(&bus->dev,
0209             "failed to write mt7530 register\n");
0210     return ret;
0211 }
0212
0213 static u32
0214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
0215 {
0216     struct mii_bus *bus = priv->bus;
0217     u16 page, r, lo, hi;
0218     int ret;
0219
0220     page = (reg >> 6) & 0x3ff;
0221     r = (reg >> 2) & 0xf;
0222
0223     /* MT7530 uses 31 as the pseudo port */
0224     ret = bus->write(bus, 0x1f, 0x1f, page);
0225     if (ret < 0) {
0226         dev_err(&bus->dev,
0227             "failed to read mt7530 register\n");
0228         return ret;
0229     }
0230
0231     lo = bus->read(bus, 0x1f, r);
0232     hi = bus->read(bus, 0x1f, 0x10);
0233
0234     return (hi << 16) | (lo & 0xffff);
0235 }
0236
0237 static void
0238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
0239 {
0240     struct mii_bus *bus = priv->bus;
0241
0242     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0243
0244     mt7530_mii_write(priv, reg, val);
0245
0246     mutex_unlock(&bus->mdio_lock);
0247 }
0248
0249 static u32
0250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
0251 {
0252     return mt7530_mii_read(p->priv, p->reg);
0253 }
0254
0255 static u32
0256 _mt7530_read(struct mt7530_dummy_poll *p)
0257 {
0258     struct mii_bus      *bus = p->priv->bus;
0259     u32 val;
0260
0261     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0262
0263     val = mt7530_mii_read(p->priv, p->reg);
0264
0265     mutex_unlock(&bus->mdio_lock);
0266
0267     return val;
0268 }
0269
0270 static u32
0271 mt7530_read(struct mt7530_priv *priv, u32 reg)
0272 {
0273     struct mt7530_dummy_poll p;
0274
0275     INIT_MT7530_DUMMY_POLL(&p, priv, reg);
0276     return _mt7530_read(&p);
0277 }
0278
0279 static void
0280 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
0281        u32 mask, u32 set)
0282 {
0283     struct mii_bus *bus = priv->bus;
0284     u32 val;
0285
0286     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0287
0288     val = mt7530_mii_read(priv, reg);
0289     val &= ~mask;
0290     val |= set;
0291     mt7530_mii_write(priv, reg, val);
0292
0293     mutex_unlock(&bus->mdio_lock);
0294 }
0295
0296 static void
0297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
0298 {
0299     mt7530_rmw(priv, reg, 0, val);
0300 }
0301
0302 static void
0303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
0304 {
0305     mt7530_rmw(priv, reg, val, 0);
0306 }
0307
0308 static int
0309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
0310 {
0311     u32 val;
0312     int ret;
0313     struct mt7530_dummy_poll p;
0314
0315     /* Set the command operating upon the MAC address entries */
0316     val = ATC_BUSY | ATC_MAT(0) | cmd;
0317     mt7530_write(priv, MT7530_ATC, val);
0318
0319     INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
0320     ret = readx_poll_timeout(_mt7530_read, &p, val,
0321                  !(val & ATC_BUSY), 20, 20000);
0322     if (ret < 0) {
0323         dev_err(priv->dev, "reset timeout\n");
0324         return ret;
0325     }
0326
0327     /* Additional sanity for read command if the specified
0328      * entry is invalid
0329      */
0330     val = mt7530_read(priv, MT7530_ATC);
0331     if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
0332         return -EINVAL;
0333
0334     if (rsp)
0335         *rsp = val;
0336
0337     return 0;
0338 }
0339
0340 static void
0341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
0342 {
0343     u32 reg[3];
0344     int i;
0345
0346     /* Read from ARL table into an array */
0347     for (i = 0; i < 3; i++) {
0348         reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
0349
0350         dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
0351             __func__, __LINE__, i, reg[i]);
0352     }
0353
0354     fdb->vid = (reg[1] >> CVID) & CVID_MASK;
0355     fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
0356     fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
0357     fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
0358     fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
0359     fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
0360     fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
0361     fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
0362     fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
0363     fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
0364 }
0365
0366 static void
0367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
0368          u8 port_mask, const u8 *mac,
0369          u8 aging, u8 type)
0370 {
0371     u32 reg[3] = { 0 };
0372     int i;
0373
0374     reg[1] |= vid & CVID_MASK;
0375     reg[1] |= ATA2_IVL;
0376     reg[1] |= ATA2_FID(FID_BRIDGED);
0377     reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
0378     reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
0379     /* STATIC_ENT indicate that entry is static wouldn't
0380      * be aged out and STATIC_EMP specified as erasing an
0381      * entry
0382      */
0383     reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
0384     reg[1] |= mac[5] << MAC_BYTE_5;
0385     reg[1] |= mac[4] << MAC_BYTE_4;
0386     reg[0] |= mac[3] << MAC_BYTE_3;
0387     reg[0] |= mac[2] << MAC_BYTE_2;
0388     reg[0] |= mac[1] << MAC_BYTE_1;
0389     reg[0] |= mac[0] << MAC_BYTE_0;
0390
0391     /* Write array into the ARL table */
0392     for (i = 0; i < 3; i++)
0393         mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
0394 }
0395
0396 /* Setup TX circuit including relevant PAD and driving */
0397 static int
0398 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
0399 {
0400     struct mt7530_priv *priv = ds->priv;
0401     u32 ncpo1, ssc_delta, trgint, i, xtal;
0402
0403     xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
0404
0405     if (xtal == HWTRAP_XTAL_20MHZ) {
0406         dev_err(priv->dev,
0407             "%s: MT7530 with a 20MHz XTAL is not supported!\n",
0408             __func__);
0409         return -EINVAL;
0410     }
0411
0412     switch (interface) {
0413     case PHY_INTERFACE_MODE_RGMII:
0414         trgint = 0;
0415         /* PLL frequency: 125MHz */
0416         ncpo1 = 0x0c80;
0417         break;
0418     case PHY_INTERFACE_MODE_TRGMII:
0419         trgint = 1;
0420         if (priv->id == ID_MT7621) {
0421             /* PLL frequency: 150MHz: 1.2GBit */
0422             if (xtal == HWTRAP_XTAL_40MHZ)
0423                 ncpo1 = 0x0780;
0424             if (xtal == HWTRAP_XTAL_25MHZ)
0425                 ncpo1 = 0x0a00;
0426         } else { /* PLL frequency: 250MHz: 2.0Gbit */
0427             if (xtal == HWTRAP_XTAL_40MHZ)
0428                 ncpo1 = 0x0c80;
0429             if (xtal == HWTRAP_XTAL_25MHZ)
0430                 ncpo1 = 0x1400;
0431         }
0432         break;
0433     default:
0434         dev_err(priv->dev, "xMII interface %d not supported\n",
0435             interface);
0436         return -EINVAL;
0437     }
0438
0439     if (xtal == HWTRAP_XTAL_25MHZ)
0440         ssc_delta = 0x57;
0441     else
0442         ssc_delta = 0x87;
0443
0444     mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
0445            P6_INTF_MODE(trgint));
0446
0447     /* Lower Tx Driving for TRGMII path */
0448     for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
0449         mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
0450                  TD_DM_DRVP(8) | TD_DM_DRVN(8));
0451
0452     /* Disable MT7530 core and TRGMII Tx clocks */
0453     core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
0454            REG_GSWCK_EN | REG_TRGMIICK_EN);
0455
0456     /* Setup core clock for MT7530 */
0457     /* Disable PLL */
0458     core_write(priv, CORE_GSWPLL_GRP1, 0);
0459
0460     /* Set core clock into 500Mhz */
0461     core_write(priv, CORE_GSWPLL_GRP2,
0462            RG_GSWPLL_POSDIV_500M(1) |
0463            RG_GSWPLL_FBKDIV_500M(25));
0464
0465     /* Enable PLL */
0466     core_write(priv, CORE_GSWPLL_GRP1,
0467            RG_GSWPLL_EN_PRE |
0468            RG_GSWPLL_POSDIV_200M(2) |
0469            RG_GSWPLL_FBKDIV_200M(32));
0470
0471     /* Setup the MT7530 TRGMII Tx Clock */
0472     core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
0473     core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
0474     core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
0475     core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
0476     core_write(priv, CORE_PLL_GROUP4,
0477            RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
0478            RG_SYSPLL_BIAS_LPF_EN);
0479     core_write(priv, CORE_PLL_GROUP2,
0480            RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
0481            RG_SYSPLL_POSDIV(1));
0482     core_write(priv, CORE_PLL_GROUP7,
0483            RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
0484            RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
0485
0486     /* Enable MT7530 core and TRGMII Tx clocks */
0487     core_set(priv, CORE_TRGMII_GSW_CLK_CG,
0488          REG_GSWCK_EN | REG_TRGMIICK_EN);
0489
0490     if (!trgint)
0491         for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
0492             mt7530_rmw(priv, MT7530_TRGMII_RD(i),
0493                    RD_TAP_MASK, RD_TAP(16));
0494     return 0;
0495 }
0496
0497 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
0498 {
0499     u32 val;
0500
0501     val = mt7530_read(priv, MT7531_TOP_SIG_SR);
0502
0503     return (val & PAD_DUAL_SGMII_EN) != 0;
0504 }
0505
0506 static int
0507 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
0508 {
0509     return 0;
0510 }
0511
0512 static void
0513 mt7531_pll_setup(struct mt7530_priv *priv)
0514 {
0515     u32 top_sig;
0516     u32 hwstrap;
0517     u32 xtal;
0518     u32 val;
0519
0520     if (mt7531_dual_sgmii_supported(priv))
0521         return;
0522
0523     val = mt7530_read(priv, MT7531_CREV);
0524     top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
0525     hwstrap = mt7530_read(priv, MT7531_HWTRAP);
0526     if ((val & CHIP_REV_M) > 0)
0527         xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
0528                             HWTRAP_XTAL_FSEL_25MHZ;
0529     else
0530         xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
0531
0532     /* Step 1 : Disable MT7531 COREPLL */
0533     val = mt7530_read(priv, MT7531_PLLGP_EN);
0534     val &= ~EN_COREPLL;
0535     mt7530_write(priv, MT7531_PLLGP_EN, val);
0536
0537     /* Step 2: switch to XTAL output */
0538     val = mt7530_read(priv, MT7531_PLLGP_EN);
0539     val |= SW_CLKSW;
0540     mt7530_write(priv, MT7531_PLLGP_EN, val);
0541
0542     val = mt7530_read(priv, MT7531_PLLGP_CR0);
0543     val &= ~RG_COREPLL_EN;
0544     mt7530_write(priv, MT7531_PLLGP_CR0, val);
0545
0546     /* Step 3: disable PLLGP and enable program PLLGP */
0547     val = mt7530_read(priv, MT7531_PLLGP_EN);
0548     val |= SW_PLLGP;
0549     mt7530_write(priv, MT7531_PLLGP_EN, val);
0550
0551     /* Step 4: program COREPLL output frequency to 500MHz */
0552     val = mt7530_read(priv, MT7531_PLLGP_CR0);
0553     val &= ~RG_COREPLL_POSDIV_M;
0554     val |= 2 << RG_COREPLL_POSDIV_S;
0555     mt7530_write(priv, MT7531_PLLGP_CR0, val);
0556     usleep_range(25, 35);
0557
0558     switch (xtal) {
0559     case HWTRAP_XTAL_FSEL_25MHZ:
0560         val = mt7530_read(priv, MT7531_PLLGP_CR0);
0561         val &= ~RG_COREPLL_SDM_PCW_M;
0562         val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
0563         mt7530_write(priv, MT7531_PLLGP_CR0, val);
0564         break;
0565     case HWTRAP_XTAL_FSEL_40MHZ:
0566         val = mt7530_read(priv, MT7531_PLLGP_CR0);
0567         val &= ~RG_COREPLL_SDM_PCW_M;
0568         val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
0569         mt7530_write(priv, MT7531_PLLGP_CR0, val);
0570         break;
0571     }
0572
0573     /* Set feedback divide ratio update signal to high */
0574     val = mt7530_read(priv, MT7531_PLLGP_CR0);
0575     val |= RG_COREPLL_SDM_PCW_CHG;
0576     mt7530_write(priv, MT7531_PLLGP_CR0, val);
0577     /* Wait for at least 16 XTAL clocks */
0578     usleep_range(10, 20);
0579
0580     /* Step 5: set feedback divide ratio update signal to low */
0581     val = mt7530_read(priv, MT7531_PLLGP_CR0);
0582     val &= ~RG_COREPLL_SDM_PCW_CHG;
0583     mt7530_write(priv, MT7531_PLLGP_CR0, val);
0584
0585     /* Enable 325M clock for SGMII */
0586     mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
0587
0588     /* Enable 250SSC clock for RGMII */
0589     mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
0590
0591     /* Step 6: Enable MT7531 PLL */
0592     val = mt7530_read(priv, MT7531_PLLGP_CR0);
0593     val |= RG_COREPLL_EN;
0594     mt7530_write(priv, MT7531_PLLGP_CR0, val);
0595
0596     val = mt7530_read(priv, MT7531_PLLGP_EN);
0597     val |= EN_COREPLL;
0598     mt7530_write(priv, MT7531_PLLGP_EN, val);
0599     usleep_range(25, 35);
0600 }
0601
0602 static void
0603 mt7530_mib_reset(struct dsa_switch *ds)
0604 {
0605     struct mt7530_priv *priv = ds->priv;
0606
0607     mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
0608     mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
0609 }
0610
0611 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
0612 {
0613     return mdiobus_read_nested(priv->bus, port, regnum);
0614 }
0615
0616 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
0617                 u16 val)
0618 {
0619     return mdiobus_write_nested(priv->bus, port, regnum, val);
0620 }
0621
0622 static int
0623 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
0624             int regnum)
0625 {
0626     struct mii_bus *bus = priv->bus;
0627     struct mt7530_dummy_poll p;
0628     u32 reg, val;
0629     int ret;
0630
0631     INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
0632
0633     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0634
0635     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0636                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0637     if (ret < 0) {
0638         dev_err(priv->dev, "poll timeout\n");
0639         goto out;
0640     }
0641
0642     reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
0643           MT7531_MDIO_DEV_ADDR(devad) | regnum;
0644     mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
0645
0646     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0647                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0648     if (ret < 0) {
0649         dev_err(priv->dev, "poll timeout\n");
0650         goto out;
0651     }
0652
0653     reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
0654           MT7531_MDIO_DEV_ADDR(devad);
0655     mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
0656
0657     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0658                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0659     if (ret < 0) {
0660         dev_err(priv->dev, "poll timeout\n");
0661         goto out;
0662     }
0663
0664     ret = val & MT7531_MDIO_RW_DATA_MASK;
0665 out:
0666     mutex_unlock(&bus->mdio_lock);
0667
0668     return ret;
0669 }
0670
0671 static int
0672 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
0673              int regnum, u32 data)
0674 {
0675     struct mii_bus *bus = priv->bus;
0676     struct mt7530_dummy_poll p;
0677     u32 val, reg;
0678     int ret;
0679
0680     INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
0681
0682     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0683
0684     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0685                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0686     if (ret < 0) {
0687         dev_err(priv->dev, "poll timeout\n");
0688         goto out;
0689     }
0690
0691     reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
0692           MT7531_MDIO_DEV_ADDR(devad) | regnum;
0693     mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
0694
0695     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0696                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0697     if (ret < 0) {
0698         dev_err(priv->dev, "poll timeout\n");
0699         goto out;
0700     }
0701
0702     reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
0703           MT7531_MDIO_DEV_ADDR(devad) | data;
0704     mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
0705
0706     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0707                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0708     if (ret < 0) {
0709         dev_err(priv->dev, "poll timeout\n");
0710         goto out;
0711     }
0712
0713 out:
0714     mutex_unlock(&bus->mdio_lock);
0715
0716     return ret;
0717 }
0718
0719 static int
0720 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
0721 {
0722     struct mii_bus *bus = priv->bus;
0723     struct mt7530_dummy_poll p;
0724     int ret;
0725     u32 val;
0726
0727     INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
0728
0729     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0730
0731     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0732                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0733     if (ret < 0) {
0734         dev_err(priv->dev, "poll timeout\n");
0735         goto out;
0736     }
0737
0738     val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
0739           MT7531_MDIO_REG_ADDR(regnum);
0740
0741     mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
0742
0743     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
0744                  !(val & MT7531_PHY_ACS_ST), 20, 100000);
0745     if (ret < 0) {
0746         dev_err(priv->dev, "poll timeout\n");
0747         goto out;
0748     }
0749
0750     ret = val & MT7531_MDIO_RW_DATA_MASK;
0751 out:
0752     mutex_unlock(&bus->mdio_lock);
0753
0754     return ret;
0755 }
0756
0757 static int
0758 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
0759              u16 data)
0760 {
0761     struct mii_bus *bus = priv->bus;
0762     struct mt7530_dummy_poll p;
0763     int ret;
0764     u32 reg;
0765
0766     INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
0767
0768     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
0769
0770     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
0771                  !(reg & MT7531_PHY_ACS_ST), 20, 100000);
0772     if (ret < 0) {
0773         dev_err(priv->dev, "poll timeout\n");
0774         goto out;
0775     }
0776
0777     reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
0778           MT7531_MDIO_REG_ADDR(regnum) | data;
0779
0780     mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
0781
0782     ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
0783                  !(reg & MT7531_PHY_ACS_ST), 20, 100000);
0784     if (ret < 0) {
0785         dev_err(priv->dev, "poll timeout\n");
0786         goto out;
0787     }
0788
0789 out:
0790     mutex_unlock(&bus->mdio_lock);
0791
0792     return ret;
0793 }
0794
0795 static int
0796 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
0797 {
0798     int devad;
0799     int ret;
0800
0801     if (regnum & MII_ADDR_C45) {
0802         devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
0803         ret = mt7531_ind_c45_phy_read(priv, port, devad,
0804                           regnum & MII_REGADDR_C45_MASK);
0805     } else {
0806         ret = mt7531_ind_c22_phy_read(priv, port, regnum);
0807     }
0808
0809     return ret;
0810 }
0811
0812 static int
0813 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
0814              u16 data)
0815 {
0816     int devad;
0817     int ret;
0818
0819     if (regnum & MII_ADDR_C45) {
0820         devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
0821         ret = mt7531_ind_c45_phy_write(priv, port, devad,
0822                            regnum & MII_REGADDR_C45_MASK,
0823                            data);
0824     } else {
0825         ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
0826     }
0827
0828     return ret;
0829 }
0830
0831 static int
0832 mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
0833 {
0834     struct mt7530_priv *priv = bus->priv;
0835
0836     return priv->info->phy_read(priv, port, regnum);
0837 }
0838
0839 static int
0840 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
0841 {
0842     struct mt7530_priv *priv = bus->priv;
0843
0844     return priv->info->phy_write(priv, port, regnum, val);
0845 }
0846
0847 static void
0848 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
0849            uint8_t *data)
0850 {
0851     int i;
0852
0853     if (stringset != ETH_SS_STATS)
0854         return;
0855
0856     for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
0857         strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
0858             ETH_GSTRING_LEN);
0859 }
0860
0861 static void
0862 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
0863              uint64_t *data)
0864 {
0865     struct mt7530_priv *priv = ds->priv;
0866     const struct mt7530_mib_desc *mib;
0867     u32 reg, i;
0868     u64 hi;
0869
0870     for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
0871         mib = &mt7530_mib[i];
0872         reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
0873
0874         data[i] = mt7530_read(priv, reg);
0875         if (mib->size == 2) {
0876             hi = mt7530_read(priv, reg + 4);
0877             data[i] |= hi << 32;
0878         }
0879     }
0880 }
0881
0882 static int
0883 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
0884 {
0885     if (sset != ETH_SS_STATS)
0886         return 0;
0887
0888     return ARRAY_SIZE(mt7530_mib);
0889 }
0890
0891 static int
0892 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
0893 {
0894     struct mt7530_priv *priv = ds->priv;
0895     unsigned int secs = msecs / 1000;
0896     unsigned int tmp_age_count;
0897     unsigned int error = -1;
0898     unsigned int age_count;
0899     unsigned int age_unit;
0900
0901     /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
0902     if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
0903         return -ERANGE;
0904
0905     /* iterate through all possible age_count to find the closest pair */
0906     for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
0907         unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
0908
0909         if (tmp_age_unit <= AGE_UNIT_MAX) {
0910             unsigned int tmp_error = secs -
0911                 (tmp_age_count + 1) * (tmp_age_unit + 1);
0912
0913             /* found a closer pair */
0914             if (error > tmp_error) {
0915                 error = tmp_error;
0916                 age_count = tmp_age_count;
0917                 age_unit = tmp_age_unit;
0918             }
0919
0920             /* found the exact match, so break the loop */
0921             if (!error)
0922                 break;
0923         }
0924     }
0925
0926     mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
0927
0928     return 0;
0929 }
0930
0931 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
0932 {
0933     struct mt7530_priv *priv = ds->priv;
0934     u8 tx_delay = 0;
0935     int val;
0936
0937     mutex_lock(&priv->reg_mutex);
0938
0939     val = mt7530_read(priv, MT7530_MHWTRAP);
0940
0941     val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
0942     val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
0943
0944     switch (priv->p5_intf_sel) {
0945     case P5_INTF_SEL_PHY_P0:
0946         /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
0947         val |= MHWTRAP_PHY0_SEL;
0948         fallthrough;
0949     case P5_INTF_SEL_PHY_P4:
0950         /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
0951         val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
0952
0953         /* Setup the MAC by default for the cpu port */
0954         mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
0955         break;
0956     case P5_INTF_SEL_GMAC5:
0957         /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
0958         val &= ~MHWTRAP_P5_DIS;
0959         break;
0960     case P5_DISABLED:
0961         interface = PHY_INTERFACE_MODE_NA;
0962         break;
0963     default:
0964         dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
0965             priv->p5_intf_sel);
0966         goto unlock_exit;
0967     }
0968
0969     /* Setup RGMII settings */
0970     if (phy_interface_mode_is_rgmii(interface)) {
0971         val |= MHWTRAP_P5_RGMII_MODE;
0972
0973         /* P5 RGMII RX Clock Control: delay setting for 1000M */
0974         mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
0975
0976         /* Don't set delay in DSA mode */
0977         if (!dsa_is_dsa_port(priv->ds, 5) &&
0978             (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
0979              interface == PHY_INTERFACE_MODE_RGMII_ID))
0980             tx_delay = 4; /* n * 0.5 ns */
0981
0982         /* P5 RGMII TX Clock Control: delay x */
0983         mt7530_write(priv, MT7530_P5RGMIITXCR,
0984                  CSR_RGMII_TXC_CFG(0x10 + tx_delay));
0985
0986         /* reduce P5 RGMII Tx driving, 8mA */
0987         mt7530_write(priv, MT7530_IO_DRV_CR,
0988                  P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
0989     }
0990
0991     mt7530_write(priv, MT7530_MHWTRAP, val);
0992
0993     dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
0994         val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
0995
0996     priv->p5_interface = interface;
0997
0998 unlock_exit:
0999     mutex_unlock(&priv->reg_mutex);
1000 }
1001
1002 static int
1003 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
1004 {
1005     struct mt7530_priv *priv = ds->priv;
1006     int ret;
1007
1008     /* Setup max capability of CPU port at first */
1009     if (priv->info->cpu_port_config) {
1010         ret = priv->info->cpu_port_config(ds, port);
1011         if (ret)
1012             return ret;
1013     }
1014
1015     /* Enable Mediatek header mode on the cpu port */
1016     mt7530_write(priv, MT7530_PVC_P(port),
1017              PORT_SPEC_TAG);
1018
1019     /* Disable flooding by default */
1020     mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1021            BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
1022
1023     /* Set CPU port number */
1024     if (priv->id == ID_MT7621)
1025         mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1026
1027     /* CPU port gets connected to all user ports of
1028      * the switch.
1029      */
1030     mt7530_write(priv, MT7530_PCR_P(port),
1031              PCR_MATRIX(dsa_user_ports(priv->ds)));
1032
1033     /* Set to fallback mode for independent VLAN learning */
1034     mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1035            MT7530_PORT_FALLBACK_MODE);
1036
1037     return 0;
1038 }
1039
1040 static int
1041 mt7530_port_enable(struct dsa_switch *ds, int port,
1042            struct phy_device *phy)
1043 {
1044     struct dsa_port *dp = dsa_to_port(ds, port);
1045     struct mt7530_priv *priv = ds->priv;
1046
1047     mutex_lock(&priv->reg_mutex);
1048
1049     /* Allow the user port gets connected to the cpu port and also
1050      * restore the port matrix if the port is the member of a certain
1051      * bridge.
1052      */
1053     if (dsa_port_is_user(dp)) {
1054         struct dsa_port *cpu_dp = dp->cpu_dp;
1055
1056         priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
1057     }
1058     priv->ports[port].enable = true;
1059     mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1060            priv->ports[port].pm);
1061     mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1062
1063     mutex_unlock(&priv->reg_mutex);
1064
1065     return 0;
1066 }
1067
1068 static void
1069 mt7530_port_disable(struct dsa_switch *ds, int port)
1070 {
1071     struct mt7530_priv *priv = ds->priv;
1072
1073     mutex_lock(&priv->reg_mutex);
1074
1075     /* Clear up all port matrix which could be restored in the next
1076      * enablement for the port.
1077      */
1078     priv->ports[port].enable = false;
1079     mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1080            PCR_MATRIX_CLR);
1081     mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1082
1083     mutex_unlock(&priv->reg_mutex);
1084 }
1085
1086 static int
1087 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1088 {
1089     struct mt7530_priv *priv = ds->priv;
1090     struct mii_bus *bus = priv->bus;
1091     int length;
1092     u32 val;
1093
1094     /* When a new MTU is set, DSA always set the CPU port's MTU to the
1095      * largest MTU of the slave ports. Because the switch only has a global
1096      * RX length register, only allowing CPU port here is enough.
1097      */
1098     if (!dsa_is_cpu_port(ds, port))
1099         return 0;
1100
1101     mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1102
1103     val = mt7530_mii_read(priv, MT7530_GMACCR);
1104     val &= ~MAX_RX_PKT_LEN_MASK;
1105
1106     /* RX length also includes Ethernet header, MTK tag, and FCS length */
1107     length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1108     if (length <= 1522) {
1109         val |= MAX_RX_PKT_LEN_1522;
1110     } else if (length <= 1536) {
1111         val |= MAX_RX_PKT_LEN_1536;
1112     } else if (length <= 1552) {
1113         val |= MAX_RX_PKT_LEN_1552;
1114     } else {
1115         val &= ~MAX_RX_JUMBO_MASK;
1116         val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1117         val |= MAX_RX_PKT_LEN_JUMBO;
1118     }
1119
1120     mt7530_mii_write(priv, MT7530_GMACCR, val);
1121
1122     mutex_unlock(&bus->mdio_lock);
1123
1124     return 0;
1125 }
1126
1127 static int
1128 mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1129 {
1130     return MT7530_MAX_MTU;
1131 }
1132
1133 static void
1134 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1135 {
1136     struct mt7530_priv *priv = ds->priv;
1137     u32 stp_state;
1138
1139     switch (state) {
1140     case BR_STATE_DISABLED:
1141         stp_state = MT7530_STP_DISABLED;
1142         break;
1143     case BR_STATE_BLOCKING:
1144         stp_state = MT7530_STP_BLOCKING;
1145         break;
1146     case BR_STATE_LISTENING:
1147         stp_state = MT7530_STP_LISTENING;
1148         break;
1149     case BR_STATE_LEARNING:
1150         stp_state = MT7530_STP_LEARNING;
1151         break;
1152     case BR_STATE_FORWARDING:
1153     default:
1154         stp_state = MT7530_STP_FORWARDING;
1155         break;
1156     }
1157
1158     mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1159            FID_PST(FID_BRIDGED, stp_state));
1160 }
1161
1162 static int
1163 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1164                  struct switchdev_brport_flags flags,
1165                  struct netlink_ext_ack *extack)
1166 {
1167     if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1168                BR_BCAST_FLOOD))
1169         return -EINVAL;
1170
1171     return 0;
1172 }
1173
1174 static int
1175 mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1176              struct switchdev_brport_flags flags,
1177              struct netlink_ext_ack *extack)
1178 {
1179     struct mt7530_priv *priv = ds->priv;
1180
1181     if (flags.mask & BR_LEARNING)
1182         mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1183                flags.val & BR_LEARNING ? 0 : SA_DIS);
1184
1185     if (flags.mask & BR_FLOOD)
1186         mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1187                flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1188
1189     if (flags.mask & BR_MCAST_FLOOD)
1190         mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1191                flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1192
1193     if (flags.mask & BR_BCAST_FLOOD)
1194         mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1195                flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1196
1197     return 0;
1198 }
1199
1200 static int
1201 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1202             struct dsa_bridge bridge, bool *tx_fwd_offload,
1203             struct netlink_ext_ack *extack)
1204 {
1205     struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1206     struct dsa_port *cpu_dp = dp->cpu_dp;
1207     u32 port_bitmap = BIT(cpu_dp->index);
1208     struct mt7530_priv *priv = ds->priv;
1209
1210     mutex_lock(&priv->reg_mutex);
1211
1212     dsa_switch_for_each_user_port(other_dp, ds) {
1213         int other_port = other_dp->index;
1214
1215         if (dp == other_dp)
1216             continue;
1217
1218         /* Add this port to the port matrix of the other ports in the
1219          * same bridge. If the port is disabled, port matrix is kept
1220          * and not being setup until the port becomes enabled.
1221          */
1222         if (!dsa_port_offloads_bridge(other_dp, &bridge))
1223             continue;
1224
1225         if (priv->ports[other_port].enable)
1226             mt7530_set(priv, MT7530_PCR_P(other_port),
1227                    PCR_MATRIX(BIT(port)));
1228         priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1229
1230         port_bitmap |= BIT(other_port);
1231     }
1232
1233     /* Add the all other ports to this port matrix. */
1234     if (priv->ports[port].enable)
1235         mt7530_rmw(priv, MT7530_PCR_P(port),
1236                PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1237     priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1238
1239     /* Set to fallback mode for independent VLAN learning */
1240     mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1241            MT7530_PORT_FALLBACK_MODE);
1242
1243     mutex_unlock(&priv->reg_mutex);
1244
1245     return 0;
1246 }
1247
1248 static void
1249 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1250 {
1251     struct mt7530_priv *priv = ds->priv;
1252     bool all_user_ports_removed = true;
1253     int i;
1254
1255     /* This is called after .port_bridge_leave when leaving a VLAN-aware
1256      * bridge. Don't set standalone ports to fallback mode.
1257      */
1258     if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
1259         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1260                MT7530_PORT_FALLBACK_MODE);
1261
1262     mt7530_rmw(priv, MT7530_PVC_P(port),
1263            VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
1264            VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1265            PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1266            MT7530_VLAN_ACC_ALL);
1267
1268     /* Set PVID to 0 */
1269     mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1270            G0_PORT_VID_DEF);
1271
1272     for (i = 0; i < MT7530_NUM_PORTS; i++) {
1273         if (dsa_is_user_port(ds, i) &&
1274             dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1275             all_user_ports_removed = false;
1276             break;
1277         }
1278     }
1279
1280     /* CPU port also does the same thing until all user ports belonging to
1281      * the CPU port get out of VLAN filtering mode.
1282      */
1283     if (all_user_ports_removed) {
1284         struct dsa_port *dp = dsa_to_port(ds, port);
1285         struct dsa_port *cpu_dp = dp->cpu_dp;
1286
1287         mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
1288                  PCR_MATRIX(dsa_user_ports(priv->ds)));
1289         mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
1290                  | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1291     }
1292 }
1293
1294 static void
1295 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1296 {
1297     struct mt7530_priv *priv = ds->priv;
1298
1299     /* Trapped into security mode allows packet forwarding through VLAN
1300      * table lookup.
1301      */
1302     if (dsa_is_user_port(ds, port)) {
1303         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1304                MT7530_PORT_SECURITY_MODE);
1305         mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1306                G0_PORT_VID(priv->ports[port].pvid));
1307
1308         /* Only accept tagged frames if PVID is not set */
1309         if (!priv->ports[port].pvid)
1310             mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1311                    MT7530_VLAN_ACC_TAGGED);
1312     }
1313
1314     /* Set the port as a user port which is to be able to recognize VID
1315      * from incoming packets before fetching entry within the VLAN table.
1316      */
1317     mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1318            VLAN_ATTR(MT7530_VLAN_USER) |
1319            PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1320 }
1321
1322 static void
1323 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1324              struct dsa_bridge bridge)
1325 {
1326     struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1327     struct dsa_port *cpu_dp = dp->cpu_dp;
1328     struct mt7530_priv *priv = ds->priv;
1329
1330     mutex_lock(&priv->reg_mutex);
1331
1332     dsa_switch_for_each_user_port(other_dp, ds) {
1333         int other_port = other_dp->index;
1334
1335         if (dp == other_dp)
1336             continue;
1337
1338         /* Remove this port from the port matrix of the other ports
1339          * in the same bridge. If the port is disabled, port matrix
1340          * is kept and not being setup until the port becomes enabled.
1341          */
1342         if (!dsa_port_offloads_bridge(other_dp, &bridge))
1343             continue;
1344
1345         if (priv->ports[other_port].enable)
1346             mt7530_clear(priv, MT7530_PCR_P(other_port),
1347                      PCR_MATRIX(BIT(port)));
1348         priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
1349     }
1350
1351     /* Set the cpu port to be the only one in the port matrix of
1352      * this port.
1353      */
1354     if (priv->ports[port].enable)
1355         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1356                PCR_MATRIX(BIT(cpu_dp->index)));
1357     priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
1358
1359     /* When a port is removed from the bridge, the port would be set up
1360      * back to the default as is at initial boot which is a VLAN-unaware
1361      * port.
1362      */
1363     mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1364            MT7530_PORT_MATRIX_MODE);
1365
1366     mutex_unlock(&priv->reg_mutex);
1367 }
1368
1369 static int
1370 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1371             const unsigned char *addr, u16 vid,
1372             struct dsa_db db)
1373 {
1374     struct mt7530_priv *priv = ds->priv;
1375     int ret;
1376     u8 port_mask = BIT(port);
1377
1378     mutex_lock(&priv->reg_mutex);
1379     mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1380     ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1381     mutex_unlock(&priv->reg_mutex);
1382
1383     return ret;
1384 }
1385
1386 static int
1387 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1388             const unsigned char *addr, u16 vid,
1389             struct dsa_db db)
1390 {
1391     struct mt7530_priv *priv = ds->priv;
1392     int ret;
1393     u8 port_mask = BIT(port);
1394
1395     mutex_lock(&priv->reg_mutex);
1396     mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1397     ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1398     mutex_unlock(&priv->reg_mutex);
1399
1400     return ret;
1401 }
1402
1403 static int
1404 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1405              dsa_fdb_dump_cb_t *cb, void *data)
1406 {
1407     struct mt7530_priv *priv = ds->priv;
1408     struct mt7530_fdb _fdb = { 0 };
1409     int cnt = MT7530_NUM_FDB_RECORDS;
1410     int ret = 0;
1411     u32 rsp = 0;
1412
1413     mutex_lock(&priv->reg_mutex);
1414
1415     ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1416     if (ret < 0)
1417         goto err;
1418
1419     do {
1420         if (rsp & ATC_SRCH_HIT) {
1421             mt7530_fdb_read(priv, &_fdb);
1422             if (_fdb.port_mask & BIT(port)) {
1423                 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1424                      data);
1425                 if (ret < 0)
1426                     break;
1427             }
1428         }
1429     } while (--cnt &&
1430          !(rsp & ATC_SRCH_END) &&
1431          !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1432 err:
1433     mutex_unlock(&priv->reg_mutex);
1434
1435     return 0;
1436 }
1437
1438 static int
1439 mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1440             const struct switchdev_obj_port_mdb *mdb,
1441             struct dsa_db db)
1442 {
1443     struct mt7530_priv *priv = ds->priv;
1444     const u8 *addr = mdb->addr;
1445     u16 vid = mdb->vid;
1446     u8 port_mask = 0;
1447     int ret;
1448
1449     mutex_lock(&priv->reg_mutex);
1450
1451     mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1452     if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1453         port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1454                 & PORT_MAP_MASK;
1455
1456     port_mask |= BIT(port);
1457     mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1458     ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1459
1460     mutex_unlock(&priv->reg_mutex);
1461
1462     return ret;
1463 }
1464
1465 static int
1466 mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1467             const struct switchdev_obj_port_mdb *mdb,
1468             struct dsa_db db)
1469 {
1470     struct mt7530_priv *priv = ds->priv;
1471     const u8 *addr = mdb->addr;
1472     u16 vid = mdb->vid;
1473     u8 port_mask = 0;
1474     int ret;
1475
1476     mutex_lock(&priv->reg_mutex);
1477
1478     mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1479     if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1480         port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1481                 & PORT_MAP_MASK;
1482
1483     port_mask &= ~BIT(port);
1484     mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1485              port_mask ? STATIC_ENT : STATIC_EMP);
1486     ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1487
1488     mutex_unlock(&priv->reg_mutex);
1489
1490     return ret;
1491 }
1492
1493 static int
1494 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1495 {
1496     struct mt7530_dummy_poll p;
1497     u32 val;
1498     int ret;
1499
1500     val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1501     mt7530_write(priv, MT7530_VTCR, val);
1502
1503     INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1504     ret = readx_poll_timeout(_mt7530_read, &p, val,
1505                  !(val & VTCR_BUSY), 20, 20000);
1506     if (ret < 0) {
1507         dev_err(priv->dev, "poll timeout\n");
1508         return ret;
1509     }
1510
1511     val = mt7530_read(priv, MT7530_VTCR);
1512     if (val & VTCR_INVALID) {
1513         dev_err(priv->dev, "read VTCR invalid\n");
1514         return -EINVAL;
1515     }
1516
1517     return 0;
1518 }
1519
1520 static int
1521 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1522                struct netlink_ext_ack *extack)
1523 {
1524     struct dsa_port *dp = dsa_to_port(ds, port);
1525     struct dsa_port *cpu_dp = dp->cpu_dp;
1526
1527     if (vlan_filtering) {
1528         /* The port is being kept as VLAN-unaware port when bridge is
1529          * set up with vlan_filtering not being set, Otherwise, the
1530          * port and the corresponding CPU port is required the setup
1531          * for becoming a VLAN-aware port.
1532          */
1533         mt7530_port_set_vlan_aware(ds, port);
1534         mt7530_port_set_vlan_aware(ds, cpu_dp->index);
1535     } else {
1536         mt7530_port_set_vlan_unaware(ds, port);
1537     }
1538
1539     return 0;
1540 }
1541
1542 static void
1543 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1544            struct mt7530_hw_vlan_entry *entry)
1545 {
1546     struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
1547     u8 new_members;
1548     u32 val;
1549
1550     new_members = entry->old_members | BIT(entry->port);
1551
1552     /* Validate the entry with independent learning, create egress tag per
1553      * VLAN and joining the port as one of the port members.
1554      */
1555     val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1556           VLAN_VALID;
1557     mt7530_write(priv, MT7530_VAWD1, val);
1558
1559     /* Decide whether adding tag or not for those outgoing packets from the
1560      * port inside the VLAN.
1561      * CPU port is always taken as a tagged port for serving more than one
1562      * VLANs across and also being applied with egress type stack mode for
1563      * that VLAN tags would be appended after hardware special tag used as
1564      * DSA tag.
1565      */
1566     if (dsa_port_is_cpu(dp))
1567         val = MT7530_VLAN_EGRESS_STACK;
1568     else if (entry->untagged)
1569         val = MT7530_VLAN_EGRESS_UNTAG;
1570     else
1571         val = MT7530_VLAN_EGRESS_TAG;
1572     mt7530_rmw(priv, MT7530_VAWD2,
1573            ETAG_CTRL_P_MASK(entry->port),
1574            ETAG_CTRL_P(entry->port, val));
1575 }
1576
1577 static void
1578 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1579            struct mt7530_hw_vlan_entry *entry)
1580 {
1581     u8 new_members;
1582     u32 val;
1583
1584     new_members = entry->old_members & ~BIT(entry->port);
1585
1586     val = mt7530_read(priv, MT7530_VAWD1);
1587     if (!(val & VLAN_VALID)) {
1588         dev_err(priv->dev,
1589             "Cannot be deleted due to invalid entry\n");
1590         return;
1591     }
1592
1593     if (new_members) {
1594         val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1595               VLAN_VALID;
1596         mt7530_write(priv, MT7530_VAWD1, val);
1597     } else {
1598         mt7530_write(priv, MT7530_VAWD1, 0);
1599         mt7530_write(priv, MT7530_VAWD2, 0);
1600     }
1601 }
1602
1603 static void
1604 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1605               struct mt7530_hw_vlan_entry *entry,
1606               mt7530_vlan_op vlan_op)
1607 {
1608     u32 val;
1609
1610     /* Fetch entry */
1611     mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1612
1613     val = mt7530_read(priv, MT7530_VAWD1);
1614
1615     entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1616
1617     /* Manipulate entry */
1618     vlan_op(priv, entry);
1619
1620     /* Flush result to hardware */
1621     mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1622 }
1623
1624 static int
1625 mt7530_setup_vlan0(struct mt7530_priv *priv)
1626 {
1627     u32 val;
1628
1629     /* Validate the entry with independent learning, keep the original
1630      * ingress tag attribute.
1631      */
1632     val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1633           VLAN_VALID;
1634     mt7530_write(priv, MT7530_VAWD1, val);
1635
1636     return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1637 }
1638
1639 static int
1640 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1641              const struct switchdev_obj_port_vlan *vlan,
1642              struct netlink_ext_ack *extack)
1643 {
1644     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1645     bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1646     struct mt7530_hw_vlan_entry new_entry;
1647     struct mt7530_priv *priv = ds->priv;
1648
1649     mutex_lock(&priv->reg_mutex);
1650
1651     mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1652     mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
1653
1654     if (pvid) {
1655         priv->ports[port].pvid = vlan->vid;
1656
1657         /* Accept all frames if PVID is set */
1658         mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1659                MT7530_VLAN_ACC_ALL);
1660
1661         /* Only configure PVID if VLAN filtering is enabled */
1662         if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1663             mt7530_rmw(priv, MT7530_PPBV1_P(port),
1664                    G0_PORT_VID_MASK,
1665                    G0_PORT_VID(vlan->vid));
1666     } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1667         /* This VLAN is overwritten without PVID, so unset it */
1668         priv->ports[port].pvid = G0_PORT_VID_DEF;
1669
1670         /* Only accept tagged frames if the port is VLAN-aware */
1671         if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1672             mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1673                    MT7530_VLAN_ACC_TAGGED);
1674
1675         mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1676                G0_PORT_VID_DEF);
1677     }
1678
1679     mutex_unlock(&priv->reg_mutex);
1680
1681     return 0;
1682 }
1683
1684 static int
1685 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1686              const struct switchdev_obj_port_vlan *vlan)
1687 {
1688     struct mt7530_hw_vlan_entry target_entry;
1689     struct mt7530_priv *priv = ds->priv;
1690
1691     mutex_lock(&priv->reg_mutex);
1692
1693     mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1694     mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1695                   mt7530_hw_vlan_del);
1696
1697     /* PVID is being restored to the default whenever the PVID port
1698      * is being removed from the VLAN.
1699      */
1700     if (priv->ports[port].pvid == vlan->vid) {
1701         priv->ports[port].pvid = G0_PORT_VID_DEF;
1702
1703         /* Only accept tagged frames if the port is VLAN-aware */
1704         if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1705             mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1706                    MT7530_VLAN_ACC_TAGGED);
1707
1708         mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1709                G0_PORT_VID_DEF);
1710     }
1711
1712
1713     mutex_unlock(&priv->reg_mutex);
1714
1715     return 0;
1716 }
1717
1718 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1719 {
1720     return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1721                    MIRROR_PORT(val);
1722 }
1723
1724 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1725 {
1726     return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1727                    MIRROR_PORT(val);
1728 }
1729
1730 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1731                   struct dsa_mall_mirror_tc_entry *mirror,
1732                   bool ingress, struct netlink_ext_ack *extack)
1733 {
1734     struct mt7530_priv *priv = ds->priv;
1735     int monitor_port;
1736     u32 val;
1737
1738     /* Check for existent entry */
1739     if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1740         return -EEXIST;
1741
1742     val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1743
1744     /* MT7530 only supports one monitor port */
1745     monitor_port = mt753x_mirror_port_get(priv->id, val);
1746     if (val & MT753X_MIRROR_EN(priv->id) &&
1747         monitor_port != mirror->to_local_port)
1748         return -EEXIST;
1749
1750     val |= MT753X_MIRROR_EN(priv->id);
1751     val &= ~MT753X_MIRROR_MASK(priv->id);
1752     val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1753     mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1754
1755     val = mt7530_read(priv, MT7530_PCR_P(port));
1756     if (ingress) {
1757         val |= PORT_RX_MIR;
1758         priv->mirror_rx |= BIT(port);
1759     } else {
1760         val |= PORT_TX_MIR;
1761         priv->mirror_tx |= BIT(port);
1762     }
1763     mt7530_write(priv, MT7530_PCR_P(port), val);
1764
1765     return 0;
1766 }
1767
1768 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1769                    struct dsa_mall_mirror_tc_entry *mirror)
1770 {
1771     struct mt7530_priv *priv = ds->priv;
1772     u32 val;
1773
1774     val = mt7530_read(priv, MT7530_PCR_P(port));
1775     if (mirror->ingress) {
1776         val &= ~PORT_RX_MIR;
1777         priv->mirror_rx &= ~BIT(port);
1778     } else {
1779         val &= ~PORT_TX_MIR;
1780         priv->mirror_tx &= ~BIT(port);
1781     }
1782     mt7530_write(priv, MT7530_PCR_P(port), val);
1783
1784     if (!priv->mirror_rx && !priv->mirror_tx) {
1785         val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1786         val &= ~MT753X_MIRROR_EN(priv->id);
1787         mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1788     }
1789 }
1790
1791 static enum dsa_tag_protocol
1792 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1793              enum dsa_tag_protocol mp)
1794 {
1795     return DSA_TAG_PROTO_MTK;
1796 }
1797
1798 #ifdef CONFIG_GPIOLIB
1799 static inline u32
1800 mt7530_gpio_to_bit(unsigned int offset)
1801 {
1802     /* Map GPIO offset to register bit
1803      * [ 2: 0]  port 0 LED 0..2 as GPIO 0..2
1804      * [ 6: 4]  port 1 LED 0..2 as GPIO 3..5
1805      * [10: 8]  port 2 LED 0..2 as GPIO 6..8
1806      * [14:12]  port 3 LED 0..2 as GPIO 9..11
1807      * [18:16]  port 4 LED 0..2 as GPIO 12..14
1808      */
1809     return BIT(offset + offset / 3);
1810 }
1811
1812 static int
1813 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1814 {
1815     struct mt7530_priv *priv = gpiochip_get_data(gc);
1816     u32 bit = mt7530_gpio_to_bit(offset);
1817
1818     return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1819 }
1820
1821 static void
1822 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1823 {
1824     struct mt7530_priv *priv = gpiochip_get_data(gc);
1825     u32 bit = mt7530_gpio_to_bit(offset);
1826
1827     if (value)
1828         mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1829     else
1830         mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1831 }
1832
1833 static int
1834 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1835 {
1836     struct mt7530_priv *priv = gpiochip_get_data(gc);
1837     u32 bit = mt7530_gpio_to_bit(offset);
1838
1839     return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1840         GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1841 }
1842
1843 static int
1844 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1845 {
1846     struct mt7530_priv *priv = gpiochip_get_data(gc);
1847     u32 bit = mt7530_gpio_to_bit(offset);
1848
1849     mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1850     mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1851
1852     return 0;
1853 }
1854
1855 static int
1856 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1857 {
1858     struct mt7530_priv *priv = gpiochip_get_data(gc);
1859     u32 bit = mt7530_gpio_to_bit(offset);
1860
1861     mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1862
1863     if (value)
1864         mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1865     else
1866         mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1867
1868     mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1869
1870     return 0;
1871 }
1872
1873 static int
1874 mt7530_setup_gpio(struct mt7530_priv *priv)
1875 {
1876     struct device *dev = priv->dev;
1877     struct gpio_chip *gc;
1878
1879     gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1880     if (!gc)
1881         return -ENOMEM;
1882
1883     mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1884     mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1885     mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1886
1887     gc->label = "mt7530";
1888     gc->parent = dev;
1889     gc->owner = THIS_MODULE;
1890     gc->get_direction = mt7530_gpio_get_direction;
1891     gc->direction_input = mt7530_gpio_direction_input;
1892     gc->direction_output = mt7530_gpio_direction_output;
1893     gc->get = mt7530_gpio_get;
1894     gc->set = mt7530_gpio_set;
1895     gc->base = -1;
1896     gc->ngpio = 15;
1897     gc->can_sleep = true;
1898
1899     return devm_gpiochip_add_data(dev, gc, priv);
1900 }
1901 #endif /* CONFIG_GPIOLIB */
1902
1903 static irqreturn_t
1904 mt7530_irq_thread_fn(int irq, void *dev_id)
1905 {
1906     struct mt7530_priv *priv = dev_id;
1907     bool handled = false;
1908     u32 val;
1909     int p;
1910
1911     mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1912     val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1913     mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1914     mutex_unlock(&priv->bus->mdio_lock);
1915
1916     for (p = 0; p < MT7530_NUM_PHYS; p++) {
1917         if (BIT(p) & val) {
1918             unsigned int irq;
1919
1920             irq = irq_find_mapping(priv->irq_domain, p);
1921             handle_nested_irq(irq);
1922             handled = true;
1923         }
1924     }
1925
1926     return IRQ_RETVAL(handled);
1927 }
1928
1929 static void
1930 mt7530_irq_mask(struct irq_data *d)
1931 {
1932     struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1933
1934     priv->irq_enable &= ~BIT(d->hwirq);
1935 }
1936
1937 static void
1938 mt7530_irq_unmask(struct irq_data *d)
1939 {
1940     struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1941
1942     priv->irq_enable |= BIT(d->hwirq);
1943 }
1944
1945 static void
1946 mt7530_irq_bus_lock(struct irq_data *d)
1947 {
1948     struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1949
1950     mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1951 }
1952
1953 static void
1954 mt7530_irq_bus_sync_unlock(struct irq_data *d)
1955 {
1956     struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1957
1958     mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1959     mutex_unlock(&priv->bus->mdio_lock);
1960 }
1961
1962 static struct irq_chip mt7530_irq_chip = {
1963     .name = KBUILD_MODNAME,
1964     .irq_mask = mt7530_irq_mask,
1965     .irq_unmask = mt7530_irq_unmask,
1966     .irq_bus_lock = mt7530_irq_bus_lock,
1967     .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1968 };
1969
1970 static int
1971 mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1972            irq_hw_number_t hwirq)
1973 {
1974     irq_set_chip_data(irq, domain->host_data);
1975     irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1976     irq_set_nested_thread(irq, true);
1977     irq_set_noprobe(irq);
1978
1979     return 0;
1980 }
1981
1982 static const struct irq_domain_ops mt7530_irq_domain_ops = {
1983     .map = mt7530_irq_map,
1984     .xlate = irq_domain_xlate_onecell,
1985 };
1986
1987 static void
1988 mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1989 {
1990     struct dsa_switch *ds = priv->ds;
1991     int p;
1992
1993     for (p = 0; p < MT7530_NUM_PHYS; p++) {
1994         if (BIT(p) & ds->phys_mii_mask) {
1995             unsigned int irq;
1996
1997             irq = irq_create_mapping(priv->irq_domain, p);
1998             ds->slave_mii_bus->irq[p] = irq;
1999         }
2000     }
2001 }
2002
2003 static int
2004 mt7530_setup_irq(struct mt7530_priv *priv)
2005 {
2006     struct device *dev = priv->dev;
2007     struct device_node *np = dev->of_node;
2008     int ret;
2009
2010     if (!of_property_read_bool(np, "interrupt-controller")) {
2011         dev_info(dev, "no interrupt support\n");
2012         return 0;
2013     }
2014
2015     priv->irq = of_irq_get(np, 0);
2016     if (priv->irq <= 0) {
2017         dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
2018         return priv->irq ? : -EINVAL;
2019     }
2020
2021     priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2022                          &mt7530_irq_domain_ops, priv);
2023     if (!priv->irq_domain) {
2024         dev_err(dev, "failed to create IRQ domain\n");
2025         return -ENOMEM;
2026     }
2027
2028     /* This register must be set for MT7530 to properly fire interrupts */
2029     if (priv->id != ID_MT7531)
2030         mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2031
2032     ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2033                    IRQF_ONESHOT, KBUILD_MODNAME, priv);
2034     if (ret) {
2035         irq_domain_remove(priv->irq_domain);
2036         dev_err(dev, "failed to request IRQ: %d\n", ret);
2037         return ret;
2038     }
2039
2040     return 0;
2041 }
2042
2043 static void
2044 mt7530_free_mdio_irq(struct mt7530_priv *priv)
2045 {
2046     int p;
2047
2048     for (p = 0; p < MT7530_NUM_PHYS; p++) {
2049         if (BIT(p) & priv->ds->phys_mii_mask) {
2050             unsigned int irq;
2051
2052             irq = irq_find_mapping(priv->irq_domain, p);
2053             irq_dispose_mapping(irq);
2054         }
2055     }
2056 }
2057
2058 static void
2059 mt7530_free_irq_common(struct mt7530_priv *priv)
2060 {
2061     free_irq(priv->irq, priv);
2062     irq_domain_remove(priv->irq_domain);
2063 }
2064
2065 static void
2066 mt7530_free_irq(struct mt7530_priv *priv)
2067 {
2068     mt7530_free_mdio_irq(priv);
2069     mt7530_free_irq_common(priv);
2070 }
2071
2072 static int
2073 mt7530_setup_mdio(struct mt7530_priv *priv)
2074 {
2075     struct dsa_switch *ds = priv->ds;
2076     struct device *dev = priv->dev;
2077     struct mii_bus *bus;
2078     static int idx;
2079     int ret;
2080
2081     bus = devm_mdiobus_alloc(dev);
2082     if (!bus)
2083         return -ENOMEM;
2084
2085     ds->slave_mii_bus = bus;
2086     bus->priv = priv;
2087     bus->name = KBUILD_MODNAME "-mii";
2088     snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2089     bus->read = mt753x_phy_read;
2090     bus->write = mt753x_phy_write;
2091     bus->parent = dev;
2092     bus->phy_mask = ~ds->phys_mii_mask;
2093
2094     if (priv->irq)
2095         mt7530_setup_mdio_irq(priv);
2096
2097     ret = devm_mdiobus_register(dev, bus);
2098     if (ret) {
2099         dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2100         if (priv->irq)
2101             mt7530_free_mdio_irq(priv);
2102     }
2103
2104     return ret;
2105 }
2106
2107 static int
2108 mt7530_setup(struct dsa_switch *ds)
2109 {
2110     struct mt7530_priv *priv = ds->priv;
2111     struct device_node *dn = NULL;
2112     struct device_node *phy_node;
2113     struct device_node *mac_np;
2114     struct mt7530_dummy_poll p;
2115     phy_interface_t interface;
2116     struct dsa_port *cpu_dp;
2117     u32 id, val;
2118     int ret, i;
2119
2120     /* The parent node of master netdev which holds the common system
2121      * controller also is the container for two GMACs nodes representing
2122      * as two netdev instances.
2123      */
2124     dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2125         dn = cpu_dp->master->dev.of_node->parent;
2126         /* It doesn't matter which CPU port is found first,
2127          * their masters should share the same parent OF node
2128          */
2129         break;
2130     }
2131
2132     if (!dn) {
2133         dev_err(ds->dev, "parent OF node of DSA master not found");
2134         return -EINVAL;
2135     }
2136
2137     ds->assisted_learning_on_cpu_port = true;
2138     ds->mtu_enforcement_ingress = true;
2139
2140     if (priv->id == ID_MT7530) {
2141         regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2142         ret = regulator_enable(priv->core_pwr);
2143         if (ret < 0) {
2144             dev_err(priv->dev,
2145                 "Failed to enable core power: %d\n", ret);
2146             return ret;
2147         }
2148
2149         regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2150         ret = regulator_enable(priv->io_pwr);
2151         if (ret < 0) {
2152             dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2153                 ret);
2154             return ret;
2155         }
2156     }
2157
2158     /* Reset whole chip through gpio pin or memory-mapped registers for
2159      * different type of hardware
2160      */
2161     if (priv->mcm) {
2162         reset_control_assert(priv->rstc);
2163         usleep_range(1000, 1100);
2164         reset_control_deassert(priv->rstc);
2165     } else {
2166         gpiod_set_value_cansleep(priv->reset, 0);
2167         usleep_range(1000, 1100);
2168         gpiod_set_value_cansleep(priv->reset, 1);
2169     }
2170
2171     /* Waiting for MT7530 got to stable */
2172     INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2173     ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2174                  20, 1000000);
2175     if (ret < 0) {
2176         dev_err(priv->dev, "reset timeout\n");
2177         return ret;
2178     }
2179
2180     id = mt7530_read(priv, MT7530_CREV);
2181     id >>= CHIP_NAME_SHIFT;
2182     if (id != MT7530_ID) {
2183         dev_err(priv->dev, "chip %x can't be supported\n", id);
2184         return -ENODEV;
2185     }
2186
2187     /* Reset the switch through internal reset */
2188     mt7530_write(priv, MT7530_SYS_CTRL,
2189              SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2190              SYS_CTRL_REG_RST);
2191
2192     /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2193     val = mt7530_read(priv, MT7530_MHWTRAP);
2194     val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2195     val |= MHWTRAP_MANUAL;
2196     mt7530_write(priv, MT7530_MHWTRAP, val);
2197
2198     priv->p6_interface = PHY_INTERFACE_MODE_NA;
2199
2200     /* Enable and reset MIB counters */
2201     mt7530_mib_reset(ds);
2202
2203     for (i = 0; i < MT7530_NUM_PORTS; i++) {
2204         /* Disable forwarding by default on all ports */
2205         mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2206                PCR_MATRIX_CLR);
2207
2208         /* Disable learning by default on all ports */
2209         mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2210
2211         if (dsa_is_cpu_port(ds, i)) {
2212             ret = mt753x_cpu_port_enable(ds, i);
2213             if (ret)
2214                 return ret;
2215         } else {
2216             mt7530_port_disable(ds, i);
2217
2218             /* Set default PVID to 0 on all user ports */
2219             mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2220                    G0_PORT_VID_DEF);
2221         }
2222         /* Enable consistent egress tag */
2223         mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2224                PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2225     }
2226
2227     /* Setup VLAN ID 0 for VLAN-unaware bridges */
2228     ret = mt7530_setup_vlan0(priv);
2229     if (ret)
2230         return ret;
2231
2232     /* Setup port 5 */
2233     priv->p5_intf_sel = P5_DISABLED;
2234     interface = PHY_INTERFACE_MODE_NA;
2235
2236     if (!dsa_is_unused_port(ds, 5)) {
2237         priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2238         ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2239         if (ret && ret != -ENODEV)
2240             return ret;
2241     } else {
2242         /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2243         for_each_child_of_node(dn, mac_np) {
2244             if (!of_device_is_compatible(mac_np,
2245                              "mediatek,eth-mac"))
2246                 continue;
2247
2248             ret = of_property_read_u32(mac_np, "reg", &id);
2249             if (ret < 0 || id != 1)
2250                 continue;
2251
2252             phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
2253             if (!phy_node)
2254                 continue;
2255
2256             if (phy_node->parent == priv->dev->of_node->parent) {
2257                 ret = of_get_phy_mode(mac_np, &interface);
2258                 if (ret && ret != -ENODEV) {
2259                     of_node_put(mac_np);
2260                     of_node_put(phy_node);
2261                     return ret;
2262                 }
2263                 id = of_mdio_parse_addr(ds->dev, phy_node);
2264                 if (id == 0)
2265                     priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2266                 if (id == 4)
2267                     priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2268             }
2269             of_node_put(mac_np);
2270             of_node_put(phy_node);
2271             break;
2272         }
2273     }
2274
2275 #ifdef CONFIG_GPIOLIB
2276     if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2277         ret = mt7530_setup_gpio(priv);
2278         if (ret)
2279             return ret;
2280     }
2281 #endif /* CONFIG_GPIOLIB */
2282
2283     mt7530_setup_port5(ds, interface);
2284
2285     /* Flush the FDB table */
2286     ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2287     if (ret < 0)
2288         return ret;
2289
2290     return 0;
2291 }
2292
2293 static int
2294 mt7531_setup(struct dsa_switch *ds)
2295 {
2296     struct mt7530_priv *priv = ds->priv;
2297     struct mt7530_dummy_poll p;
2298     struct dsa_port *cpu_dp;
2299     u32 val, id;
2300     int ret, i;
2301
2302     /* Reset whole chip through gpio pin or memory-mapped registers for
2303      * different type of hardware
2304      */
2305     if (priv->mcm) {
2306         reset_control_assert(priv->rstc);
2307         usleep_range(1000, 1100);
2308         reset_control_deassert(priv->rstc);
2309     } else {
2310         gpiod_set_value_cansleep(priv->reset, 0);
2311         usleep_range(1000, 1100);
2312         gpiod_set_value_cansleep(priv->reset, 1);
2313     }
2314
2315     /* Waiting for MT7530 got to stable */
2316     INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2317     ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2318                  20, 1000000);
2319     if (ret < 0) {
2320         dev_err(priv->dev, "reset timeout\n");
2321         return ret;
2322     }
2323
2324     id = mt7530_read(priv, MT7531_CREV);
2325     id >>= CHIP_NAME_SHIFT;
2326
2327     if (id != MT7531_ID) {
2328         dev_err(priv->dev, "chip %x can't be supported\n", id);
2329         return -ENODEV;
2330     }
2331
2332     /* all MACs must be forced link-down before sw reset */
2333     for (i = 0; i < MT7530_NUM_PORTS; i++)
2334         mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
2335
2336     /* Reset the switch through internal reset */
2337     mt7530_write(priv, MT7530_SYS_CTRL,
2338              SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2339              SYS_CTRL_REG_RST);
2340
2341     mt7531_pll_setup(priv);
2342
2343     if (mt7531_dual_sgmii_supported(priv)) {
2344         priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2345
2346         /* Let ds->slave_mii_bus be able to access external phy. */
2347         mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2348                MT7531_EXT_P_MDC_11);
2349         mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2350                MT7531_EXT_P_MDIO_12);
2351     } else {
2352         priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2353     }
2354     dev_dbg(ds->dev, "P5 support %s interface\n",
2355         p5_intf_modes(priv->p5_intf_sel));
2356
2357     mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2358            MT7531_GPIO0_INTERRUPT);
2359
2360     /* Let phylink decide the interface later. */
2361     priv->p5_interface = PHY_INTERFACE_MODE_NA;
2362     priv->p6_interface = PHY_INTERFACE_MODE_NA;
2363
2364     /* Enable PHY core PLL, since phy_device has not yet been created
2365      * provided for phy_[read,write]_mmd_indirect is called, we provide
2366      * our own mt7531_ind_mmd_phy_[read,write] to complete this
2367      * function.
2368      */
2369     val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2370                       MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2371     val |= MT7531_PHY_PLL_BYPASS_MODE;
2372     val &= ~MT7531_PHY_PLL_OFF;
2373     mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2374                  CORE_PLL_GROUP4, val);
2375
2376     /* BPDU to CPU port */
2377     dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2378         mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2379                BIT(cpu_dp->index));
2380         break;
2381     }
2382     mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2383            MT753X_BPDU_CPU_ONLY);
2384
2385     /* Enable and reset MIB counters */
2386     mt7530_mib_reset(ds);
2387
2388     for (i = 0; i < MT7530_NUM_PORTS; i++) {
2389         /* Disable forwarding by default on all ports */
2390         mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2391                PCR_MATRIX_CLR);
2392
2393         /* Disable learning by default on all ports */
2394         mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2395
2396         mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2397
2398         if (dsa_is_cpu_port(ds, i)) {
2399             ret = mt753x_cpu_port_enable(ds, i);
2400             if (ret)
2401                 return ret;
2402         } else {
2403             mt7530_port_disable(ds, i);
2404
2405             /* Set default PVID to 0 on all user ports */
2406             mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2407                    G0_PORT_VID_DEF);
2408         }
2409
2410         /* Enable consistent egress tag */
2411         mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2412                PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2413     }
2414
2415     /* Setup VLAN ID 0 for VLAN-unaware bridges */
2416     ret = mt7530_setup_vlan0(priv);
2417     if (ret)
2418         return ret;
2419
2420     ds->assisted_learning_on_cpu_port = true;
2421     ds->mtu_enforcement_ingress = true;
2422
2423     /* Flush the FDB table */
2424     ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2425     if (ret < 0)
2426         return ret;
2427
2428     return 0;
2429 }
2430
2431 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
2432                      struct phylink_config *config)
2433 {
2434     switch (port) {
2435     case 0 ... 4: /* Internal phy */
2436         __set_bit(PHY_INTERFACE_MODE_GMII,
2437               config->supported_interfaces);
2438         break;
2439
2440     case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2441         phy_interface_set_rgmii(config->supported_interfaces);
2442         __set_bit(PHY_INTERFACE_MODE_MII,
2443               config->supported_interfaces);
2444         __set_bit(PHY_INTERFACE_MODE_GMII,
2445               config->supported_interfaces);
2446         break;
2447
2448     case 6: /* 1st cpu port */
2449         __set_bit(PHY_INTERFACE_MODE_RGMII,
2450               config->supported_interfaces);
2451         __set_bit(PHY_INTERFACE_MODE_TRGMII,
2452               config->supported_interfaces);
2453         break;
2454     }
2455 }
2456
2457 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2458 {
2459     return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2460 }
2461
2462 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
2463                      struct phylink_config *config)
2464 {
2465     struct mt7530_priv *priv = ds->priv;
2466
2467     switch (port) {
2468     case 0 ... 4: /* Internal phy */
2469         __set_bit(PHY_INTERFACE_MODE_GMII,
2470               config->supported_interfaces);
2471         break;
2472
2473     case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2474         if (mt7531_is_rgmii_port(priv, port)) {
2475             phy_interface_set_rgmii(config->supported_interfaces);
2476             break;
2477         }
2478         fallthrough;
2479
2480     case 6: /* 1st cpu port supports sgmii/8023z only */
2481         __set_bit(PHY_INTERFACE_MODE_SGMII,
2482               config->supported_interfaces);
2483         __set_bit(PHY_INTERFACE_MODE_1000BASEX,
2484               config->supported_interfaces);
2485         __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2486               config->supported_interfaces);
2487
2488         config->mac_capabilities |= MAC_2500FD;
2489         break;
2490     }
2491 }
2492
2493 static int
2494 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2495 {
2496     struct mt7530_priv *priv = ds->priv;
2497
2498     return priv->info->pad_setup(ds, state->interface);
2499 }
2500
2501 static int
2502 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2503           phy_interface_t interface)
2504 {
2505     struct mt7530_priv *priv = ds->priv;
2506
2507     /* Only need to setup port5. */
2508     if (port != 5)
2509         return 0;
2510
2511     mt7530_setup_port5(priv->ds, interface);
2512
2513     return 0;
2514 }
2515
2516 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2517                   phy_interface_t interface,
2518                   struct phy_device *phydev)
2519 {
2520     u32 val;
2521
2522     if (!mt7531_is_rgmii_port(priv, port)) {
2523         dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2524             port);
2525         return -EINVAL;
2526     }
2527
2528     val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2529     val |= GP_CLK_EN;
2530     val &= ~GP_MODE_MASK;
2531     val |= GP_MODE(MT7531_GP_MODE_RGMII);
2532     val &= ~CLK_SKEW_IN_MASK;
2533     val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2534     val &= ~CLK_SKEW_OUT_MASK;
2535     val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2536     val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2537
2538     /* Do not adjust rgmii delay when vendor phy driver presents. */
2539     if (!phydev || phy_driver_is_genphy(phydev)) {
2540         val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2541         switch (interface) {
2542         case PHY_INTERFACE_MODE_RGMII:
2543             val |= TXCLK_NO_REVERSE;
2544             val |= RXCLK_NO_DELAY;
2545             break;
2546         case PHY_INTERFACE_MODE_RGMII_RXID:
2547             val |= TXCLK_NO_REVERSE;
2548             break;
2549         case PHY_INTERFACE_MODE_RGMII_TXID:
2550             val |= RXCLK_NO_DELAY;
2551             break;
2552         case PHY_INTERFACE_MODE_RGMII_ID:
2553             break;
2554         default:
2555             return -EINVAL;
2556         }
2557     }
2558     mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2559
2560     return 0;
2561 }
2562
2563 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
2564                    phy_interface_t interface, int speed, int duplex)
2565 {
2566     struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2567     int port = pcs_to_mt753x_pcs(pcs)->port;
2568     unsigned int val;
2569
2570     /* For adjusting speed and duplex of SGMII force mode. */
2571     if (interface != PHY_INTERFACE_MODE_SGMII ||
2572         phylink_autoneg_inband(mode))
2573         return;
2574
2575     /* SGMII force mode setting */
2576     val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2577     val &= ~MT7531_SGMII_IF_MODE_MASK;
2578
2579     switch (speed) {
2580     case SPEED_10:
2581         val |= MT7531_SGMII_FORCE_SPEED_10;
2582         break;
2583     case SPEED_100:
2584         val |= MT7531_SGMII_FORCE_SPEED_100;
2585         break;
2586     case SPEED_1000:
2587         val |= MT7531_SGMII_FORCE_SPEED_1000;
2588         break;
2589     }
2590
2591     /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2592      * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2593      *
2594      * The speed check is unnecessary as the MAC capabilities apply
2595      * this restriction. --rmk
2596      */
2597     if ((speed == SPEED_10 || speed == SPEED_100) &&
2598         duplex != DUPLEX_FULL)
2599         val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2600
2601     mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2602 }
2603
2604 static bool mt753x_is_mac_port(u32 port)
2605 {
2606     return (port == 5 || port == 6);
2607 }
2608
2609 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2610                      phy_interface_t interface)
2611 {
2612     u32 val;
2613
2614     if (!mt753x_is_mac_port(port))
2615         return -EINVAL;
2616
2617     mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2618            MT7531_SGMII_PHYA_PWD);
2619
2620     val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2621     val &= ~MT7531_RG_TPHY_SPEED_MASK;
2622     /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2623      * encoding.
2624      */
2625     val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2626         MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2627     mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2628
2629     mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2630
2631     /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2632      * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2633      */
2634     mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2635            MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2636            MT7531_SGMII_FORCE_SPEED_1000);
2637
2638     mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2639
2640     return 0;
2641 }
2642
2643 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2644                       phy_interface_t interface)
2645 {
2646     if (!mt753x_is_mac_port(port))
2647         return -EINVAL;
2648
2649     mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2650            MT7531_SGMII_PHYA_PWD);
2651
2652     mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2653            MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2654
2655     mt7530_set(priv, MT7531_SGMII_MODE(port),
2656            MT7531_SGMII_REMOTE_FAULT_DIS |
2657            MT7531_SGMII_SPEED_DUPLEX_AN);
2658
2659     mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2660            MT7531_SGMII_TX_CONFIG_MASK, 1);
2661
2662     mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2663
2664     mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2665
2666     mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2667
2668     return 0;
2669 }
2670
2671 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs)
2672 {
2673     struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2674     int port = pcs_to_mt753x_pcs(pcs)->port;
2675     u32 val;
2676
2677     /* Only restart AN when AN is enabled */
2678     val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2679     if (val & MT7531_SGMII_AN_ENABLE) {
2680         val |= MT7531_SGMII_AN_RESTART;
2681         mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2682     }
2683 }
2684
2685 static int
2686 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2687           phy_interface_t interface)
2688 {
2689     struct mt7530_priv *priv = ds->priv;
2690     struct phy_device *phydev;
2691     struct dsa_port *dp;
2692
2693     if (!mt753x_is_mac_port(port)) {
2694         dev_err(priv->dev, "port %d is not a MAC port\n", port);
2695         return -EINVAL;
2696     }
2697
2698     switch (interface) {
2699     case PHY_INTERFACE_MODE_RGMII:
2700     case PHY_INTERFACE_MODE_RGMII_ID:
2701     case PHY_INTERFACE_MODE_RGMII_RXID:
2702     case PHY_INTERFACE_MODE_RGMII_TXID:
2703         dp = dsa_to_port(ds, port);
2704         phydev = dp->slave->phydev;
2705         return mt7531_rgmii_setup(priv, port, interface, phydev);
2706     case PHY_INTERFACE_MODE_SGMII:
2707         return mt7531_sgmii_setup_mode_an(priv, port, interface);
2708     case PHY_INTERFACE_MODE_NA:
2709     case PHY_INTERFACE_MODE_1000BASEX:
2710     case PHY_INTERFACE_MODE_2500BASEX:
2711         if (phylink_autoneg_inband(mode))
2712             return -EINVAL;
2713
2714         return mt7531_sgmii_setup_mode_force(priv, port, interface);
2715     default:
2716         return -EINVAL;
2717     }
2718
2719     return -EINVAL;
2720 }
2721
2722 static int
2723 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2724           const struct phylink_link_state *state)
2725 {
2726     struct mt7530_priv *priv = ds->priv;
2727
2728     return priv->info->mac_port_config(ds, port, mode, state->interface);
2729 }
2730
2731 static struct phylink_pcs *
2732 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
2733                   phy_interface_t interface)
2734 {
2735     struct mt7530_priv *priv = ds->priv;
2736
2737     switch (interface) {
2738     case PHY_INTERFACE_MODE_TRGMII:
2739     case PHY_INTERFACE_MODE_SGMII:
2740     case PHY_INTERFACE_MODE_1000BASEX:
2741     case PHY_INTERFACE_MODE_2500BASEX:
2742         return &priv->pcs[port].pcs;
2743
2744     default:
2745         return NULL;
2746     }
2747 }
2748
2749 static void
2750 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2751               const struct phylink_link_state *state)
2752 {
2753     struct mt7530_priv *priv = ds->priv;
2754     u32 mcr_cur, mcr_new;
2755
2756     switch (port) {
2757     case 0 ... 4: /* Internal phy */
2758         if (state->interface != PHY_INTERFACE_MODE_GMII)
2759             goto unsupported;
2760         break;
2761     case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2762         if (priv->p5_interface == state->interface)
2763             break;
2764
2765         if (mt753x_mac_config(ds, port, mode, state) < 0)
2766             goto unsupported;
2767
2768         if (priv->p5_intf_sel != P5_DISABLED)
2769             priv->p5_interface = state->interface;
2770         break;
2771     case 6: /* 1st cpu port */
2772         if (priv->p6_interface == state->interface)
2773             break;
2774
2775         mt753x_pad_setup(ds, state);
2776
2777         if (mt753x_mac_config(ds, port, mode, state) < 0)
2778             goto unsupported;
2779
2780         priv->p6_interface = state->interface;
2781         break;
2782     default:
2783 unsupported:
2784         dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2785             __func__, phy_modes(state->interface), port);
2786         return;
2787     }
2788
2789     if (phylink_autoneg_inband(mode) &&
2790         state->interface != PHY_INTERFACE_MODE_SGMII) {
2791         dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2792             __func__);
2793         return;
2794     }
2795
2796     mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2797     mcr_new = mcr_cur;
2798     mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2799     mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2800            PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2801
2802     /* Are we connected to external phy */
2803     if (port == 5 && dsa_is_user_port(ds, 5))
2804         mcr_new |= PMCR_EXT_PHY;
2805
2806     if (mcr_new != mcr_cur)
2807         mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2808 }
2809
2810 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2811                      unsigned int mode,
2812                      phy_interface_t interface)
2813 {
2814     struct mt7530_priv *priv = ds->priv;
2815
2816     mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2817 }
2818
2819 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
2820                        unsigned int mode,
2821                        phy_interface_t interface,
2822                        int speed, int duplex)
2823 {
2824     if (pcs->ops->pcs_link_up)
2825         pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
2826 }
2827
2828 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2829                        unsigned int mode,
2830                        phy_interface_t interface,
2831                        struct phy_device *phydev,
2832                        int speed, int duplex,
2833                        bool tx_pause, bool rx_pause)
2834 {
2835     struct mt7530_priv *priv = ds->priv;
2836     u32 mcr;
2837
2838     mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2839
2840     /* MT753x MAC works in 1G full duplex mode for all up-clocked
2841      * variants.
2842      */
2843     if (interface == PHY_INTERFACE_MODE_TRGMII ||
2844         (phy_interface_mode_is_8023z(interface))) {
2845         speed = SPEED_1000;
2846         duplex = DUPLEX_FULL;
2847     }
2848
2849     switch (speed) {
2850     case SPEED_1000:
2851         mcr |= PMCR_FORCE_SPEED_1000;
2852         break;
2853     case SPEED_100:
2854         mcr |= PMCR_FORCE_SPEED_100;
2855         break;
2856     }
2857     if (duplex == DUPLEX_FULL) {
2858         mcr |= PMCR_FORCE_FDX;
2859         if (tx_pause)
2860             mcr |= PMCR_TX_FC_EN;
2861         if (rx_pause)
2862             mcr |= PMCR_RX_FC_EN;
2863     }
2864
2865     if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
2866         switch (speed) {
2867         case SPEED_1000:
2868             mcr |= PMCR_FORCE_EEE1G;
2869             break;
2870         case SPEED_100:
2871             mcr |= PMCR_FORCE_EEE100;
2872             break;
2873         }
2874     }
2875
2876     mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2877 }
2878
2879 static int
2880 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2881 {
2882     struct mt7530_priv *priv = ds->priv;
2883     phy_interface_t interface;
2884     int speed;
2885     int ret;
2886
2887     switch (port) {
2888     case 5:
2889         if (mt7531_is_rgmii_port(priv, port))
2890             interface = PHY_INTERFACE_MODE_RGMII;
2891         else
2892             interface = PHY_INTERFACE_MODE_2500BASEX;
2893
2894         priv->p5_interface = interface;
2895         break;
2896     case 6:
2897         interface = PHY_INTERFACE_MODE_2500BASEX;
2898
2899         priv->p6_interface = interface;
2900         break;
2901     default:
2902         return -EINVAL;
2903     }
2904
2905     if (interface == PHY_INTERFACE_MODE_2500BASEX)
2906         speed = SPEED_2500;
2907     else
2908         speed = SPEED_1000;
2909
2910     ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2911     if (ret)
2912         return ret;
2913     mt7530_write(priv, MT7530_PMCR_P(port),
2914              PMCR_CPU_PORT_SETTING(priv->id));
2915     mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
2916                    interface, speed, DUPLEX_FULL);
2917     mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2918                    speed, DUPLEX_FULL, true, true);
2919
2920     return 0;
2921 }
2922
2923 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
2924                     struct phylink_config *config)
2925 {
2926     struct mt7530_priv *priv = ds->priv;
2927
2928     /* This switch only supports full-duplex at 1Gbps */
2929     config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2930                    MAC_10 | MAC_100 | MAC_1000FD;
2931
2932     /* This driver does not make use of the speed, duplex, pause or the
2933      * advertisement in its mac_config, so it is safe to mark this driver
2934      * as non-legacy.
2935      */
2936     config->legacy_pre_march2020 = false;
2937
2938     priv->info->mac_port_get_caps(ds, port, config);
2939 }
2940
2941 static int mt753x_pcs_validate(struct phylink_pcs *pcs,
2942                    unsigned long *supported,
2943                    const struct phylink_link_state *state)
2944 {
2945     /* Autonegotiation is not supported in TRGMII nor 802.3z modes */
2946     if (state->interface == PHY_INTERFACE_MODE_TRGMII ||
2947         phy_interface_mode_is_8023z(state->interface))
2948         phylink_clear(supported, Autoneg);
2949
2950     return 0;
2951 }
2952
2953 static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
2954                  struct phylink_link_state *state)
2955 {
2956     struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2957     int port = pcs_to_mt753x_pcs(pcs)->port;
2958     u32 pmsr;
2959
2960     pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2961
2962     state->link = (pmsr & PMSR_LINK);
2963     state->an_complete = state->link;
2964     state->duplex = !!(pmsr & PMSR_DPX);
2965
2966     switch (pmsr & PMSR_SPEED_MASK) {
2967     case PMSR_SPEED_10:
2968         state->speed = SPEED_10;
2969         break;
2970     case PMSR_SPEED_100:
2971         state->speed = SPEED_100;
2972         break;
2973     case PMSR_SPEED_1000:
2974         state->speed = SPEED_1000;
2975         break;
2976     default:
2977         state->speed = SPEED_UNKNOWN;
2978         break;
2979     }
2980
2981     state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2982     if (pmsr & PMSR_RX_FC)
2983         state->pause |= MLO_PAUSE_RX;
2984     if (pmsr & PMSR_TX_FC)
2985         state->pause |= MLO_PAUSE_TX;
2986 }
2987
2988 static int
2989 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2990                   struct phylink_link_state *state)
2991 {
2992     u32 status, val;
2993     u16 config_reg;
2994
2995     status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2996     state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2997     if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2998         (status & MT7531_SGMII_AN_ENABLE)) {
2999         val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
3000         config_reg = val >> 16;
3001
3002         switch (config_reg & LPA_SGMII_SPD_MASK) {
3003         case LPA_SGMII_1000:
3004             state->speed = SPEED_1000;
3005             break;
3006         case LPA_SGMII_100:
3007             state->speed = SPEED_100;
3008             break;
3009         case LPA_SGMII_10:
3010             state->speed = SPEED_10;
3011             break;
3012         default:
3013             dev_err(priv->dev, "invalid sgmii PHY speed\n");
3014             state->link = false;
3015             return -EINVAL;
3016         }
3017
3018         if (config_reg & LPA_SGMII_FULL_DUPLEX)
3019             state->duplex = DUPLEX_FULL;
3020         else
3021             state->duplex = DUPLEX_HALF;
3022     }
3023
3024     return 0;
3025 }
3026
3027 static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
3028                  struct phylink_link_state *state)
3029 {
3030     struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
3031     int port = pcs_to_mt753x_pcs(pcs)->port;
3032
3033     if (state->interface == PHY_INTERFACE_MODE_SGMII)
3034         mt7531_sgmii_pcs_get_state_an(priv, port, state);
3035     else
3036         state->link = false;
3037 }
3038
3039 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
3040                  phy_interface_t interface,
3041                  const unsigned long *advertising,
3042                  bool permit_pause_to_mac)
3043 {
3044     return 0;
3045 }
3046
3047 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs)
3048 {
3049 }
3050
3051 static const struct phylink_pcs_ops mt7530_pcs_ops = {
3052     .pcs_validate = mt753x_pcs_validate,
3053     .pcs_get_state = mt7530_pcs_get_state,
3054     .pcs_config = mt753x_pcs_config,
3055     .pcs_an_restart = mt7530_pcs_an_restart,
3056 };
3057
3058 static const struct phylink_pcs_ops mt7531_pcs_ops = {
3059     .pcs_validate = mt753x_pcs_validate,
3060     .pcs_get_state = mt7531_pcs_get_state,
3061     .pcs_config = mt753x_pcs_config,
3062     .pcs_an_restart = mt7531_pcs_an_restart,
3063     .pcs_link_up = mt7531_pcs_link_up,
3064 };
3065
3066 static int
3067 mt753x_setup(struct dsa_switch *ds)
3068 {
3069     struct mt7530_priv *priv = ds->priv;
3070     int i, ret;
3071
3072     /* Initialise the PCS devices */
3073     for (i = 0; i < priv->ds->num_ports; i++) {
3074         priv->pcs[i].pcs.ops = priv->info->pcs_ops;
3075         priv->pcs[i].priv = priv;
3076         priv->pcs[i].port = i;
3077     }
3078
3079     ret = priv->info->sw_setup(ds);
3080     if (ret)
3081         return ret;
3082
3083     ret = mt7530_setup_irq(priv);
3084     if (ret)
3085         return ret;
3086
3087     ret = mt7530_setup_mdio(priv);
3088     if (ret && priv->irq)
3089         mt7530_free_irq_common(priv);
3090
3091     return ret;
3092 }
3093
3094 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3095                   struct ethtool_eee *e)
3096 {
3097     struct mt7530_priv *priv = ds->priv;
3098     u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3099
3100     e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3101     e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3102
3103     return 0;
3104 }
3105
3106 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3107                   struct ethtool_eee *e)
3108 {
3109     struct mt7530_priv *priv = ds->priv;
3110     u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3111
3112     if (e->tx_lpi_timer > 0xFFF)
3113         return -EINVAL;
3114
3115     set = SET_LPI_THRESH(e->tx_lpi_timer);
3116     if (!e->tx_lpi_enabled)
3117         /* Force LPI Mode without a delay */
3118         set |= LPI_MODE_EN;
3119     mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3120
3121     return 0;
3122 }
3123
3124 static const struct dsa_switch_ops mt7530_switch_ops = {
3125     .get_tag_protocol   = mtk_get_tag_protocol,
3126     .setup          = mt753x_setup,
3127     .get_strings        = mt7530_get_strings,
3128     .get_ethtool_stats  = mt7530_get_ethtool_stats,
3129     .get_sset_count     = mt7530_get_sset_count,
3130     .set_ageing_time    = mt7530_set_ageing_time,
3131     .port_enable        = mt7530_port_enable,
3132     .port_disable       = mt7530_port_disable,
3133     .port_change_mtu    = mt7530_port_change_mtu,
3134     .port_max_mtu       = mt7530_port_max_mtu,
3135     .port_stp_state_set = mt7530_stp_state_set,
3136     .port_pre_bridge_flags  = mt7530_port_pre_bridge_flags,
3137     .port_bridge_flags  = mt7530_port_bridge_flags,
3138     .port_bridge_join   = mt7530_port_bridge_join,
3139     .port_bridge_leave  = mt7530_port_bridge_leave,
3140     .port_fdb_add       = mt7530_port_fdb_add,
3141     .port_fdb_del       = mt7530_port_fdb_del,
3142     .port_fdb_dump      = mt7530_port_fdb_dump,
3143     .port_mdb_add       = mt7530_port_mdb_add,
3144     .port_mdb_del       = mt7530_port_mdb_del,
3145     .port_vlan_filtering    = mt7530_port_vlan_filtering,
3146     .port_vlan_add      = mt7530_port_vlan_add,
3147     .port_vlan_del      = mt7530_port_vlan_del,
3148     .port_mirror_add    = mt753x_port_mirror_add,
3149     .port_mirror_del    = mt753x_port_mirror_del,
3150     .phylink_get_caps   = mt753x_phylink_get_caps,
3151     .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
3152     .phylink_mac_config = mt753x_phylink_mac_config,
3153     .phylink_mac_link_down  = mt753x_phylink_mac_link_down,
3154     .phylink_mac_link_up    = mt753x_phylink_mac_link_up,
3155     .get_mac_eee        = mt753x_get_mac_eee,
3156     .set_mac_eee        = mt753x_set_mac_eee,
3157 };
3158
3159 static const struct mt753x_info mt753x_table[] = {
3160     [ID_MT7621] = {
3161         .id = ID_MT7621,
3162         .pcs_ops = &mt7530_pcs_ops,
3163         .sw_setup = mt7530_setup,
3164         .phy_read = mt7530_phy_read,
3165         .phy_write = mt7530_phy_write,
3166         .pad_setup = mt7530_pad_clk_setup,
3167         .mac_port_get_caps = mt7530_mac_port_get_caps,
3168         .mac_port_config = mt7530_mac_config,
3169     },
3170     [ID_MT7530] = {
3171         .id = ID_MT7530,
3172         .pcs_ops = &mt7530_pcs_ops,
3173         .sw_setup = mt7530_setup,
3174         .phy_read = mt7530_phy_read,
3175         .phy_write = mt7530_phy_write,
3176         .pad_setup = mt7530_pad_clk_setup,
3177         .mac_port_get_caps = mt7530_mac_port_get_caps,
3178         .mac_port_config = mt7530_mac_config,
3179     },
3180     [ID_MT7531] = {
3181         .id = ID_MT7531,
3182         .pcs_ops = &mt7531_pcs_ops,
3183         .sw_setup = mt7531_setup,
3184         .phy_read = mt7531_ind_phy_read,
3185         .phy_write = mt7531_ind_phy_write,
3186         .pad_setup = mt7531_pad_setup,
3187         .cpu_port_config = mt7531_cpu_port_config,
3188         .mac_port_get_caps = mt7531_mac_port_get_caps,
3189         .mac_port_config = mt7531_mac_config,
3190     },
3191 };
3192
3193 static const struct of_device_id mt7530_of_match[] = {
3194     { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3195     { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
3196     { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
3197     { /* sentinel */ },
3198 };
3199 MODULE_DEVICE_TABLE(of, mt7530_of_match);
3200
3201 static int
3202 mt7530_probe(struct mdio_device *mdiodev)
3203 {
3204     struct mt7530_priv *priv;
3205     struct device_node *dn;
3206
3207     dn = mdiodev->dev.of_node;
3208
3209     priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3210     if (!priv)
3211         return -ENOMEM;
3212
3213     priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
3214     if (!priv->ds)
3215         return -ENOMEM;
3216
3217     priv->ds->dev = &mdiodev->dev;
3218     priv->ds->num_ports = MT7530_NUM_PORTS;
3219
3220     /* Use medatek,mcm property to distinguish hardware type that would
3221      * casues a little bit differences on power-on sequence.
3222      */
3223     priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3224     if (priv->mcm) {
3225         dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3226
3227         priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3228         if (IS_ERR(priv->rstc)) {
3229             dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3230             return PTR_ERR(priv->rstc);
3231         }
3232     }
3233
3234     /* Get the hardware identifier from the devicetree node.
3235      * We will need it for some of the clock and regulator setup.
3236      */
3237     priv->info = of_device_get_match_data(&mdiodev->dev);
3238     if (!priv->info)
3239         return -EINVAL;
3240
3241     /* Sanity check if these required device operations are filled
3242      * properly.
3243      */
3244     if (!priv->info->sw_setup || !priv->info->pad_setup ||
3245         !priv->info->phy_read || !priv->info->phy_write ||
3246         !priv->info->mac_port_get_caps ||
3247         !priv->info->mac_port_config)
3248         return -EINVAL;
3249
3250     priv->id = priv->info->id;
3251
3252     if (priv->id == ID_MT7530) {
3253         priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3254         if (IS_ERR(priv->core_pwr))
3255             return PTR_ERR(priv->core_pwr);
3256
3257         priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3258         if (IS_ERR(priv->io_pwr))
3259             return PTR_ERR(priv->io_pwr);
3260     }
3261
3262     /* Not MCM that indicates switch works as the remote standalone
3263      * integrated circuit so the GPIO pin would be used to complete
3264      * the reset, otherwise memory-mapped register accessing used
3265      * through syscon provides in the case of MCM.
3266      */
3267     if (!priv->mcm) {
3268         priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3269                               GPIOD_OUT_LOW);
3270         if (IS_ERR(priv->reset)) {
3271             dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3272             return PTR_ERR(priv->reset);
3273         }
3274     }
3275
3276     priv->bus = mdiodev->bus;
3277     priv->dev = &mdiodev->dev;
3278     priv->ds->priv = priv;
3279     priv->ds->ops = &mt7530_switch_ops;
3280     mutex_init(&priv->reg_mutex);
3281     dev_set_drvdata(&mdiodev->dev, priv);
3282
3283     return dsa_register_switch(priv->ds);
3284 }
3285
3286 static void
3287 mt7530_remove(struct mdio_device *mdiodev)
3288 {
3289     struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3290     int ret = 0;
3291
3292     if (!priv)
3293         return;
3294
3295     ret = regulator_disable(priv->core_pwr);
3296     if (ret < 0)
3297         dev_err(priv->dev,
3298             "Failed to disable core power: %d\n", ret);
3299
3300     ret = regulator_disable(priv->io_pwr);
3301     if (ret < 0)
3302         dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3303             ret);
3304
3305     if (priv->irq)
3306         mt7530_free_irq(priv);
3307
3308     dsa_unregister_switch(priv->ds);
3309     mutex_destroy(&priv->reg_mutex);
3310
3311     dev_set_drvdata(&mdiodev->dev, NULL);
3312 }
3313
3314 static void mt7530_shutdown(struct mdio_device *mdiodev)
3315 {
3316     struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3317
3318     if (!priv)
3319         return;
3320
3321     dsa_switch_shutdown(priv->ds);
3322
3323     dev_set_drvdata(&mdiodev->dev, NULL);
3324 }
3325
3326 static struct mdio_driver mt7530_mdio_driver = {
3327     .probe  = mt7530_probe,
3328     .remove = mt7530_remove,
3329     .shutdown = mt7530_shutdown,
3330     .mdiodrv.driver = {
3331         .name = "mt7530",
3332         .of_match_table = mt7530_of_match,
3333     },
3334 };
3335
3336 mdio_module_driver(mt7530_mdio_driver);
3337
3338 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3339 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3340 MODULE_LICENSE("GPL");