dsa/microchip/lan937x_main.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Microchip LAN937X switch driver main logic
0003  * Copyright (C) 2019-2022 Microchip Technology Inc.
0004  */
0005 #include <linux/kernel.h>
0006 #include <linux/module.h>
0007 #include <linux/iopoll.h>
0008 #include <linux/phy.h>
0009 #include <linux/of_net.h>
0010 #include <linux/of_mdio.h>
0011 #include <linux/if_bridge.h>
0012 #include <linux/if_vlan.h>
0013 #include <linux/math.h>
0014 #include <net/dsa.h>
0015 #include <net/switchdev.h>
0016
0017 #include "lan937x_reg.h"
0018 #include "ksz_common.h"
0019 #include "lan937x.h"
0020
0021 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
0022 {
0023     return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
0024 }
0025
0026 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
0027                 u8 bits, bool set)
0028 {
0029     return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
0030                   bits, set ? bits : 0);
0031 }
0032
0033 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
0034 {
0035     u16 data16;
0036     int ret;
0037
0038     /* Enable Phy access through SPI */
0039     ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
0040     if (ret < 0)
0041         return ret;
0042
0043     ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
0044     if (ret < 0)
0045         return ret;
0046
0047     /* Allow SPI access */
0048     data16 |= VPHY_SPI_INDIRECT_ENABLE;
0049
0050     return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
0051 }
0052
0053 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
0054 {
0055     u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
0056     u16 temp;
0057
0058     /* get register address based on the logical port */
0059     temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
0060
0061     return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
0062 }
0063
0064 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
0065                       u16 val)
0066 {
0067     unsigned int value;
0068     int ret;
0069
0070     /* Check for internal phy port */
0071     if (!dev->info->internal_phy[addr])
0072         return -EOPNOTSUPP;
0073
0074     ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
0075     if (ret < 0)
0076         return ret;
0077
0078     /* Write the data to be written to the VPHY reg */
0079     ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
0080     if (ret < 0)
0081         return ret;
0082
0083     /* Write the Write En and Busy bit */
0084     ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
0085               (VPHY_IND_WRITE | VPHY_IND_BUSY));
0086     if (ret < 0)
0087         return ret;
0088
0089     ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
0090                        value, !(value & VPHY_IND_BUSY), 10,
0091                        1000);
0092     if (ret < 0) {
0093         dev_err(dev->dev, "Failed to write phy register\n");
0094         return ret;
0095     }
0096
0097     return 0;
0098 }
0099
0100 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
0101                      u16 *val)
0102 {
0103     unsigned int value;
0104     int ret;
0105
0106     /* Check for internal phy port, return 0xffff for non-existent phy */
0107     if (!dev->info->internal_phy[addr])
0108         return 0xffff;
0109
0110     ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
0111     if (ret < 0)
0112         return ret;
0113
0114     /* Write Read and Busy bit to start the transaction */
0115     ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
0116     if (ret < 0)
0117         return ret;
0118
0119     ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
0120                        value, !(value & VPHY_IND_BUSY), 10,
0121                        1000);
0122     if (ret < 0) {
0123         dev_err(dev->dev, "Failed to read phy register\n");
0124         return ret;
0125     }
0126
0127     /* Read the VPHY register which has the PHY data */
0128     return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
0129 }
0130
0131 void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
0132 {
0133     lan937x_internal_phy_read(dev, addr, reg, data);
0134 }
0135
0136 void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
0137 {
0138     lan937x_internal_phy_write(dev, addr, reg, val);
0139 }
0140
0141 static int lan937x_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
0142 {
0143     struct ksz_device *dev = bus->priv;
0144     u16 val;
0145     int ret;
0146
0147     if (regnum & MII_ADDR_C45)
0148         return -EOPNOTSUPP;
0149
0150     ret = lan937x_internal_phy_read(dev, addr, regnum, &val);
0151     if (ret < 0)
0152         return ret;
0153
0154     return val;
0155 }
0156
0157 static int lan937x_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
0158                  u16 val)
0159 {
0160     struct ksz_device *dev = bus->priv;
0161
0162     if (regnum & MII_ADDR_C45)
0163         return -EOPNOTSUPP;
0164
0165     return lan937x_internal_phy_write(dev, addr, regnum, val);
0166 }
0167
0168 static int lan937x_mdio_register(struct ksz_device *dev)
0169 {
0170     struct dsa_switch *ds = dev->ds;
0171     struct device_node *mdio_np;
0172     struct mii_bus *bus;
0173     int ret;
0174
0175     mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
0176     if (!mdio_np) {
0177         dev_err(ds->dev, "no MDIO bus node\n");
0178         return -ENODEV;
0179     }
0180
0181     bus = devm_mdiobus_alloc(ds->dev);
0182     if (!bus) {
0183         of_node_put(mdio_np);
0184         return -ENOMEM;
0185     }
0186
0187     bus->priv = dev;
0188     bus->read = lan937x_sw_mdio_read;
0189     bus->write = lan937x_sw_mdio_write;
0190     bus->name = "lan937x slave smi";
0191     snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
0192     bus->parent = ds->dev;
0193     bus->phy_mask = ~ds->phys_mii_mask;
0194
0195     ds->slave_mii_bus = bus;
0196
0197     ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
0198     if (ret) {
0199         dev_err(ds->dev, "unable to register MDIO bus %s\n",
0200             bus->id);
0201     }
0202
0203     of_node_put(mdio_np);
0204
0205     return ret;
0206 }
0207
0208 int lan937x_reset_switch(struct ksz_device *dev)
0209 {
0210     u32 data32;
0211     int ret;
0212
0213     /* reset switch */
0214     ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
0215     if (ret < 0)
0216         return ret;
0217
0218     /* Enable Auto Aging */
0219     ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
0220     if (ret < 0)
0221         return ret;
0222
0223     /* disable interrupts */
0224     ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
0225     if (ret < 0)
0226         return ret;
0227
0228     ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
0229     if (ret < 0)
0230         return ret;
0231
0232     return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
0233 }
0234
0235 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
0236 {
0237     const u32 *masks = dev->info->masks;
0238     const u16 *regs = dev->info->regs;
0239     struct dsa_switch *ds = dev->ds;
0240     u8 member;
0241
0242     /* enable tag tail for host port */
0243     if (cpu_port)
0244         lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
0245                  PORT_TAIL_TAG_ENABLE, true);
0246
0247     /* set back pressure for half duplex */
0248     lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
0249              true);
0250
0251     /* enable 802.1p priority */
0252     lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
0253
0254     if (!dev->info->internal_phy[port])
0255         lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
0256                  masks[P_MII_TX_FLOW_CTRL] |
0257                  masks[P_MII_RX_FLOW_CTRL],
0258                  true);
0259
0260     if (cpu_port)
0261         member = dsa_user_ports(ds);
0262     else
0263         member = BIT(dsa_upstream_port(ds, port));
0264
0265     dev->dev_ops->cfg_port_member(dev, port, member);
0266 }
0267
0268 void lan937x_config_cpu_port(struct dsa_switch *ds)
0269 {
0270     struct ksz_device *dev = ds->priv;
0271     struct dsa_port *dp;
0272
0273     dsa_switch_for_each_cpu_port(dp, ds) {
0274         if (dev->info->cpu_ports & (1 << dp->index)) {
0275             dev->cpu_port = dp->index;
0276
0277             /* enable cpu port */
0278             lan937x_port_setup(dev, dp->index, true);
0279         }
0280     }
0281
0282     dsa_switch_for_each_user_port(dp, ds) {
0283         ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
0284     }
0285 }
0286
0287 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
0288 {
0289     struct dsa_switch *ds = dev->ds;
0290     int ret;
0291
0292     new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
0293
0294     if (dsa_is_cpu_port(ds, port))
0295         new_mtu += LAN937X_TAG_LEN;
0296
0297     if (new_mtu >= FR_MIN_SIZE)
0298         ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
0299                        PORT_JUMBO_PACKET, true);
0300     else
0301         ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
0302                        PORT_JUMBO_PACKET, false);
0303     if (ret < 0) {
0304         dev_err(ds->dev, "failed to enable jumbo\n");
0305         return ret;
0306     }
0307
0308     /* Write the frame size in PORT_MAX_FR_SIZE register */
0309     ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
0310
0311     return 0;
0312 }
0313
0314 static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
0315                  u16 reg, u8 val)
0316 {
0317     u16 data16;
0318
0319     ksz_pread16(dev, port, reg, &data16);
0320
0321     /* Update tune Adjust */
0322     data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
0323     ksz_pwrite16(dev, port, reg, data16);
0324
0325     /* write DLL reset to take effect */
0326     data16 |= PORT_DLL_RESET;
0327     ksz_pwrite16(dev, port, reg, data16);
0328 }
0329
0330 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
0331 {
0332     u8 val;
0333
0334     /* Apply different codes based on the ports as per characterization
0335      * results
0336      */
0337     val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
0338         RGMII_2_TX_DELAY_2NS;
0339
0340     lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
0341 }
0342
0343 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
0344 {
0345     u8 val;
0346
0347     val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
0348         RGMII_2_RX_DELAY_2NS;
0349
0350     lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
0351 }
0352
0353 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
0354                   struct phylink_config *config)
0355 {
0356     config->mac_capabilities = MAC_100FD;
0357
0358     if (dev->info->supports_rgmii[port]) {
0359         /* MII/RMII/RGMII ports */
0360         config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
0361                         MAC_100HD | MAC_10 | MAC_1000FD;
0362     }
0363 }
0364
0365 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
0366 {
0367     struct ksz_port *p = &dev->ports[port];
0368
0369     if (p->rgmii_tx_val) {
0370         lan937x_set_rgmii_tx_delay(dev, port);
0371         dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
0372              port);
0373     }
0374
0375     if (p->rgmii_rx_val) {
0376         lan937x_set_rgmii_rx_delay(dev, port);
0377         dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
0378              port);
0379     }
0380 }
0381
0382 int lan937x_setup(struct dsa_switch *ds)
0383 {
0384     struct ksz_device *dev = ds->priv;
0385     int ret;
0386
0387     /* enable Indirect Access from SPI to the VPHY registers */
0388     ret = lan937x_enable_spi_indirect_access(dev);
0389     if (ret < 0) {
0390         dev_err(dev->dev, "failed to enable spi indirect access");
0391         return ret;
0392     }
0393
0394     ret = lan937x_mdio_register(dev);
0395     if (ret < 0) {
0396         dev_err(dev->dev, "failed to register the mdio");
0397         return ret;
0398     }
0399
0400     /* The VLAN aware is a global setting. Mixed vlan
0401      * filterings are not supported.
0402      */
0403     ds->vlan_filtering_is_global = true;
0404
0405     /* Enable aggressive back off for half duplex & UNH mode */
0406     lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
0407             (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF),
0408             true);
0409
0410     /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
0411      * packets when 16 or more collisions occur
0412      */
0413     lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
0414
0415     /* enable global MIB counter freeze function */
0416     lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
0417
0418     /* disable CLK125 & CLK25, 1: disable, 0: enable */
0419     lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
0420             (SW_CLK125_ENB | SW_CLK25_ENB), true);
0421
0422     return 0;
0423 }
0424
0425 int lan937x_switch_init(struct ksz_device *dev)
0426 {
0427     dev->port_mask = (1 << dev->info->port_cnt) - 1;
0428
0429     return 0;
0430 }
0431
0432 void lan937x_switch_exit(struct ksz_device *dev)
0433 {
0434     lan937x_reset_switch(dev);
0435 }
0436
0437 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
0438 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
0439 MODULE_LICENSE("GPL");