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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Microchip switch driver common header
0003  *
0004  * Copyright (C) 2017-2019 Microchip Technology Inc.
0005  */
0006 
0007 #ifndef __KSZ_COMMON_H
0008 #define __KSZ_COMMON_H
0009 
0010 #include <linux/etherdevice.h>
0011 #include <linux/kernel.h>
0012 #include <linux/mutex.h>
0013 #include <linux/phy.h>
0014 #include <linux/regmap.h>
0015 #include <net/dsa.h>
0016 
0017 #define KSZ_MAX_NUM_PORTS 8
0018 
0019 struct vlan_table {
0020     u32 table[3];
0021 };
0022 
0023 struct ksz_port_mib {
0024     struct mutex cnt_mutex;     /* structure access */
0025     u8 cnt_ptr;
0026     u64 *counters;
0027     struct rtnl_link_stats64 stats64;
0028     struct ethtool_pause_stats pause_stats;
0029     struct spinlock stats64_lock;
0030 };
0031 
0032 struct ksz_mib_names {
0033     int index;
0034     char string[ETH_GSTRING_LEN];
0035 };
0036 
0037 struct ksz_chip_data {
0038     u32 chip_id;
0039     const char *dev_name;
0040     int num_vlans;
0041     int num_alus;
0042     int num_statics;
0043     int cpu_ports;
0044     int port_cnt;
0045     const struct ksz_dev_ops *ops;
0046     bool phy_errata_9477;
0047     bool ksz87xx_eee_link_erratum;
0048     const struct ksz_mib_names *mib_names;
0049     int mib_cnt;
0050     u8 reg_mib_cnt;
0051     const u16 *regs;
0052     const u32 *masks;
0053     const u8 *shifts;
0054     const u8 *xmii_ctrl0;
0055     const u8 *xmii_ctrl1;
0056     int stp_ctrl_reg;
0057     int broadcast_ctrl_reg;
0058     int multicast_ctrl_reg;
0059     int start_ctrl_reg;
0060     bool supports_mii[KSZ_MAX_NUM_PORTS];
0061     bool supports_rmii[KSZ_MAX_NUM_PORTS];
0062     bool supports_rgmii[KSZ_MAX_NUM_PORTS];
0063     bool internal_phy[KSZ_MAX_NUM_PORTS];
0064 };
0065 
0066 struct ksz_port {
0067     bool remove_tag;        /* Remove Tag flag set, for ksz8795 only */
0068     bool learning;
0069     int stp_state;
0070     struct phy_device phydev;
0071 
0072     u32 on:1;           /* port is not disabled by hardware */
0073     u32 phy:1;          /* port has a PHY */
0074     u32 fiber:1;            /* port is fiber */
0075     u32 sgmii:1;            /* port is SGMII */
0076     u32 force:1;
0077     u32 read:1;         /* read MIB counters in background */
0078     u32 freeze:1;           /* MIB counter freeze is enabled */
0079 
0080     struct ksz_port_mib mib;
0081     phy_interface_t interface;
0082     u16 max_frame;
0083     u32 rgmii_tx_val;
0084     u32 rgmii_rx_val;
0085 };
0086 
0087 struct ksz_device {
0088     struct dsa_switch *ds;
0089     struct ksz_platform_data *pdata;
0090     const struct ksz_chip_data *info;
0091 
0092     struct mutex dev_mutex;     /* device access */
0093     struct mutex regmap_mutex;  /* regmap access */
0094     struct mutex alu_mutex;     /* ALU access */
0095     struct mutex vlan_mutex;    /* vlan access */
0096     const struct ksz_dev_ops *dev_ops;
0097 
0098     struct device *dev;
0099     struct regmap *regmap[3];
0100 
0101     void *priv;
0102 
0103     struct gpio_desc *reset_gpio;   /* Optional reset GPIO */
0104 
0105     /* chip specific data */
0106     u32 chip_id;
0107     u8 chip_rev;
0108     int cpu_port;           /* port connected to CPU */
0109     int phy_port_cnt;
0110     phy_interface_t compat_interface;
0111     bool synclko_125;
0112     bool synclko_disable;
0113 
0114     struct vlan_table *vlan_cache;
0115 
0116     struct ksz_port *ports;
0117     struct delayed_work mib_read;
0118     unsigned long mib_read_interval;
0119     u16 mirror_rx;
0120     u16 mirror_tx;
0121     u32 features;           /* chip specific features */
0122     u16 port_mask;
0123 };
0124 
0125 /* List of supported models */
0126 enum ksz_model {
0127     KSZ8795,
0128     KSZ8794,
0129     KSZ8765,
0130     KSZ8830,
0131     KSZ9477,
0132     KSZ9897,
0133     KSZ9893,
0134     KSZ9567,
0135     LAN9370,
0136     LAN9371,
0137     LAN9372,
0138     LAN9373,
0139     LAN9374,
0140 };
0141 
0142 enum ksz_chip_id {
0143     KSZ8795_CHIP_ID = 0x8795,
0144     KSZ8794_CHIP_ID = 0x8794,
0145     KSZ8765_CHIP_ID = 0x8765,
0146     KSZ8830_CHIP_ID = 0x8830,
0147     KSZ9477_CHIP_ID = 0x00947700,
0148     KSZ9897_CHIP_ID = 0x00989700,
0149     KSZ9893_CHIP_ID = 0x00989300,
0150     KSZ9567_CHIP_ID = 0x00956700,
0151     LAN9370_CHIP_ID = 0x00937000,
0152     LAN9371_CHIP_ID = 0x00937100,
0153     LAN9372_CHIP_ID = 0x00937200,
0154     LAN9373_CHIP_ID = 0x00937300,
0155     LAN9374_CHIP_ID = 0x00937400,
0156 };
0157 
0158 enum ksz_regs {
0159     REG_IND_CTRL_0,
0160     REG_IND_DATA_8,
0161     REG_IND_DATA_CHECK,
0162     REG_IND_DATA_HI,
0163     REG_IND_DATA_LO,
0164     REG_IND_MIB_CHECK,
0165     REG_IND_BYTE,
0166     P_FORCE_CTRL,
0167     P_LINK_STATUS,
0168     P_LOCAL_CTRL,
0169     P_NEG_RESTART_CTRL,
0170     P_REMOTE_STATUS,
0171     P_SPEED_STATUS,
0172     S_TAIL_TAG_CTRL,
0173     P_STP_CTRL,
0174     S_START_CTRL,
0175     S_BROADCAST_CTRL,
0176     S_MULTICAST_CTRL,
0177     P_XMII_CTRL_0,
0178     P_XMII_CTRL_1,
0179 };
0180 
0181 enum ksz_masks {
0182     PORT_802_1P_REMAPPING,
0183     SW_TAIL_TAG_ENABLE,
0184     MIB_COUNTER_OVERFLOW,
0185     MIB_COUNTER_VALID,
0186     VLAN_TABLE_FID,
0187     VLAN_TABLE_MEMBERSHIP,
0188     VLAN_TABLE_VALID,
0189     STATIC_MAC_TABLE_VALID,
0190     STATIC_MAC_TABLE_USE_FID,
0191     STATIC_MAC_TABLE_FID,
0192     STATIC_MAC_TABLE_OVERRIDE,
0193     STATIC_MAC_TABLE_FWD_PORTS,
0194     DYNAMIC_MAC_TABLE_ENTRIES_H,
0195     DYNAMIC_MAC_TABLE_MAC_EMPTY,
0196     DYNAMIC_MAC_TABLE_NOT_READY,
0197     DYNAMIC_MAC_TABLE_ENTRIES,
0198     DYNAMIC_MAC_TABLE_FID,
0199     DYNAMIC_MAC_TABLE_SRC_PORT,
0200     DYNAMIC_MAC_TABLE_TIMESTAMP,
0201     ALU_STAT_WRITE,
0202     ALU_STAT_READ,
0203     P_MII_TX_FLOW_CTRL,
0204     P_MII_RX_FLOW_CTRL,
0205 };
0206 
0207 enum ksz_shifts {
0208     VLAN_TABLE_MEMBERSHIP_S,
0209     VLAN_TABLE,
0210     STATIC_MAC_FWD_PORTS,
0211     STATIC_MAC_FID,
0212     DYNAMIC_MAC_ENTRIES_H,
0213     DYNAMIC_MAC_ENTRIES,
0214     DYNAMIC_MAC_FID,
0215     DYNAMIC_MAC_TIMESTAMP,
0216     DYNAMIC_MAC_SRC_PORT,
0217     ALU_STAT_INDEX,
0218 };
0219 
0220 enum ksz_xmii_ctrl0 {
0221     P_MII_100MBIT,
0222     P_MII_10MBIT,
0223     P_MII_FULL_DUPLEX,
0224     P_MII_HALF_DUPLEX,
0225 };
0226 
0227 enum ksz_xmii_ctrl1 {
0228     P_RGMII_SEL,
0229     P_RMII_SEL,
0230     P_GMII_SEL,
0231     P_MII_SEL,
0232     P_GMII_1GBIT,
0233     P_GMII_NOT_1GBIT,
0234 };
0235 
0236 struct alu_struct {
0237     /* entry 1 */
0238     u8  is_static:1;
0239     u8  is_src_filter:1;
0240     u8  is_dst_filter:1;
0241     u8  prio_age:3;
0242     u32 _reserv_0_1:23;
0243     u8  mstp:3;
0244     /* entry 2 */
0245     u8  is_override:1;
0246     u8  is_use_fid:1;
0247     u32 _reserv_1_1:23;
0248     u8  port_forward:7;
0249     /* entry 3 & 4*/
0250     u32 _reserv_2_1:9;
0251     u8  fid:7;
0252     u8  mac[ETH_ALEN];
0253 };
0254 
0255 struct ksz_dev_ops {
0256     int (*setup)(struct dsa_switch *ds);
0257     u32 (*get_port_addr)(int port, int offset);
0258     void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
0259     void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
0260     void (*port_cleanup)(struct ksz_device *dev, int port);
0261     void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
0262     void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
0263     void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
0264     void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
0265               u64 *cnt);
0266     void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
0267               u64 *dropped, u64 *cnt);
0268     void (*r_mib_stat64)(struct ksz_device *dev, int port);
0269     int  (*vlan_filtering)(struct ksz_device *dev, int port,
0270                    bool flag, struct netlink_ext_ack *extack);
0271     int  (*vlan_add)(struct ksz_device *dev, int port,
0272              const struct switchdev_obj_port_vlan *vlan,
0273              struct netlink_ext_ack *extack);
0274     int  (*vlan_del)(struct ksz_device *dev, int port,
0275              const struct switchdev_obj_port_vlan *vlan);
0276     int (*mirror_add)(struct ksz_device *dev, int port,
0277               struct dsa_mall_mirror_tc_entry *mirror,
0278               bool ingress, struct netlink_ext_ack *extack);
0279     void (*mirror_del)(struct ksz_device *dev, int port,
0280                struct dsa_mall_mirror_tc_entry *mirror);
0281     int (*fdb_add)(struct ksz_device *dev, int port,
0282                const unsigned char *addr, u16 vid, struct dsa_db db);
0283     int (*fdb_del)(struct ksz_device *dev, int port,
0284                const unsigned char *addr, u16 vid, struct dsa_db db);
0285     int (*fdb_dump)(struct ksz_device *dev, int port,
0286             dsa_fdb_dump_cb_t *cb, void *data);
0287     int (*mdb_add)(struct ksz_device *dev, int port,
0288                const struct switchdev_obj_port_mdb *mdb,
0289                struct dsa_db db);
0290     int (*mdb_del)(struct ksz_device *dev, int port,
0291                const struct switchdev_obj_port_mdb *mdb,
0292                struct dsa_db db);
0293     void (*get_caps)(struct ksz_device *dev, int port,
0294              struct phylink_config *config);
0295     int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
0296     int (*max_mtu)(struct ksz_device *dev, int port);
0297     void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
0298     void (*port_init_cnt)(struct ksz_device *dev, int port);
0299     void (*phylink_mac_config)(struct ksz_device *dev, int port,
0300                    unsigned int mode,
0301                    const struct phylink_link_state *state);
0302     void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
0303                     unsigned int mode,
0304                     phy_interface_t interface,
0305                     struct phy_device *phydev, int speed,
0306                     int duplex, bool tx_pause, bool rx_pause);
0307     void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
0308     void (*config_cpu_port)(struct dsa_switch *ds);
0309     int (*enable_stp_addr)(struct ksz_device *dev);
0310     int (*reset)(struct ksz_device *dev);
0311     int (*init)(struct ksz_device *dev);
0312     void (*exit)(struct ksz_device *dev);
0313 };
0314 
0315 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
0316 int ksz_switch_register(struct ksz_device *dev);
0317 void ksz_switch_remove(struct ksz_device *dev);
0318 
0319 void ksz_init_mib_timer(struct ksz_device *dev);
0320 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
0321 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
0322 bool ksz_get_gbit(struct ksz_device *dev, int port);
0323 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
0324 extern const struct ksz_chip_data ksz_switch_chips[];
0325 
0326 /* Common register access functions */
0327 
0328 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
0329 {
0330     unsigned int value;
0331     int ret = regmap_read(dev->regmap[0], reg, &value);
0332 
0333     *val = value;
0334     return ret;
0335 }
0336 
0337 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
0338 {
0339     unsigned int value;
0340     int ret = regmap_read(dev->regmap[1], reg, &value);
0341 
0342     *val = value;
0343     return ret;
0344 }
0345 
0346 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
0347 {
0348     unsigned int value;
0349     int ret = regmap_read(dev->regmap[2], reg, &value);
0350 
0351     *val = value;
0352     return ret;
0353 }
0354 
0355 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
0356 {
0357     u32 value[2];
0358     int ret;
0359 
0360     ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
0361     if (!ret)
0362         *val = (u64)value[0] << 32 | value[1];
0363 
0364     return ret;
0365 }
0366 
0367 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
0368 {
0369     return regmap_write(dev->regmap[0], reg, value);
0370 }
0371 
0372 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
0373 {
0374     return regmap_write(dev->regmap[1], reg, value);
0375 }
0376 
0377 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
0378 {
0379     return regmap_write(dev->regmap[2], reg, value);
0380 }
0381 
0382 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
0383 {
0384     u32 val[2];
0385 
0386     /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
0387     value = swab64(value);
0388     val[0] = swab32(value & 0xffffffffULL);
0389     val[1] = swab32(value >> 32ULL);
0390 
0391     return regmap_bulk_write(dev->regmap[2], reg, val, 2);
0392 }
0393 
0394 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset,
0395                   u8 *data)
0396 {
0397     ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
0398 }
0399 
0400 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset,
0401                    u16 *data)
0402 {
0403     ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
0404 }
0405 
0406 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset,
0407                    u32 *data)
0408 {
0409     ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
0410 }
0411 
0412 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset,
0413                    u8 data)
0414 {
0415     ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
0416 }
0417 
0418 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset,
0419                 u16 data)
0420 {
0421     ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data);
0422 }
0423 
0424 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset,
0425                 u32 data)
0426 {
0427     ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data);
0428 }
0429 
0430 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset,
0431                  u8 mask, u8 val)
0432 {
0433     regmap_update_bits(dev->regmap[0],
0434                dev->dev_ops->get_port_addr(port, offset),
0435                mask, val);
0436 }
0437 
0438 static inline void ksz_regmap_lock(void *__mtx)
0439 {
0440     struct mutex *mtx = __mtx;
0441     mutex_lock(mtx);
0442 }
0443 
0444 static inline void ksz_regmap_unlock(void *__mtx)
0445 {
0446     struct mutex *mtx = __mtx;
0447     mutex_unlock(mtx);
0448 }
0449 
0450 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
0451 {
0452     return dev->chip_id == KSZ8830_CHIP_ID;
0453 }
0454 
0455 static inline int is_lan937x(struct ksz_device *dev)
0456 {
0457     return dev->chip_id == LAN9370_CHIP_ID ||
0458         dev->chip_id == LAN9371_CHIP_ID ||
0459         dev->chip_id == LAN9372_CHIP_ID ||
0460         dev->chip_id == LAN9373_CHIP_ID ||
0461         dev->chip_id == LAN9374_CHIP_ID;
0462 }
0463 
0464 /* STP State Defines */
0465 #define PORT_TX_ENABLE          BIT(2)
0466 #define PORT_RX_ENABLE          BIT(1)
0467 #define PORT_LEARN_DISABLE      BIT(0)
0468 
0469 /* Switch ID Defines */
0470 #define REG_CHIP_ID0            0x00
0471 
0472 #define SW_FAMILY_ID_M          GENMASK(15, 8)
0473 #define KSZ87_FAMILY_ID         0x87
0474 #define KSZ88_FAMILY_ID         0x88
0475 
0476 #define KSZ8_PORT_STATUS_0      0x08
0477 #define KSZ8_PORT_FIBER_MODE        BIT(7)
0478 
0479 #define SW_CHIP_ID_M            GENMASK(7, 4)
0480 #define KSZ87_CHIP_ID_94        0x6
0481 #define KSZ87_CHIP_ID_95        0x9
0482 #define KSZ88_CHIP_ID_63        0x3
0483 
0484 #define SW_REV_ID_M         GENMASK(7, 4)
0485 
0486 /* Driver set switch broadcast storm protection at 10% rate. */
0487 #define BROADCAST_STORM_PROT_RATE   10
0488 
0489 /* 148,800 frames * 67 ms / 100 */
0490 #define BROADCAST_STORM_VALUE       9969
0491 
0492 #define BROADCAST_STORM_RATE_HI     0x07
0493 #define BROADCAST_STORM_RATE_LO     0xFF
0494 #define BROADCAST_STORM_RATE        0x07FF
0495 
0496 #define MULTICAST_STORM_DISABLE     BIT(6)
0497 
0498 #define SW_START            0x01
0499 
0500 /* Used with variable features to indicate capabilities. */
0501 #define GBIT_SUPPORT            BIT(0)
0502 #define IS_9893             BIT(2)
0503 
0504 /* xMII configuration */
0505 #define P_MII_DUPLEX_M          BIT(6)
0506 #define P_MII_100MBIT_M         BIT(4)
0507 
0508 #define P_GMII_1GBIT_M          BIT(6)
0509 #define P_RGMII_ID_IG_ENABLE        BIT(4)
0510 #define P_RGMII_ID_EG_ENABLE        BIT(3)
0511 #define P_MII_MAC_MODE          BIT(2)
0512 #define P_MII_SEL_M         0x3
0513 
0514 /* Regmap tables generation */
0515 #define KSZ_SPI_OP_RD       3
0516 #define KSZ_SPI_OP_WR       2
0517 
0518 #define swabnot_used(x)     0
0519 
0520 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad)      \
0521     swab##swp((opcode) << ((regbits) + (regpad)))
0522 
0523 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign)     \
0524     {                               \
0525         .name = #width,                     \
0526         .val_bits = (width),                    \
0527         .reg_stride = 1,                    \
0528         .reg_bits = (regbits) + (regalign),         \
0529         .pad_bits = (regpad),                   \
0530         .max_register = BIT(regbits) - 1,           \
0531         .cache_type = REGCACHE_NONE,                \
0532         .read_flag_mask =                   \
0533             KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp,    \
0534                          regbits, regpad),      \
0535         .write_flag_mask =                  \
0536             KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp,    \
0537                          regbits, regpad),      \
0538         .lock = ksz_regmap_lock,                \
0539         .unlock = ksz_regmap_unlock,                \
0540         .reg_format_endian = REGMAP_ENDIAN_BIG,         \
0541         .val_format_endian = REGMAP_ENDIAN_BIG          \
0542     }
0543 
0544 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign)       \
0545     static const struct regmap_config ksz##_regmap_config[] = { \
0546         KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
0547         KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
0548         KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
0549     }
0550 
0551 #endif
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