Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip switch driver main logic
0004  *
0005  * Copyright (C) 2017-2019 Microchip Technology Inc.
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/export.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_data/microchip-ksz.h>
0014 #include <linux/phy.h>
0015 #include <linux/etherdevice.h>
0016 #include <linux/if_bridge.h>
0017 #include <linux/of_device.h>
0018 #include <linux/of_net.h>
0019 #include <linux/micrel_phy.h>
0020 #include <net/dsa.h>
0021 #include <net/switchdev.h>
0022 
0023 #include "ksz_common.h"
0024 #include "ksz8.h"
0025 #include "ksz9477.h"
0026 #include "lan937x.h"
0027 
0028 #define MIB_COUNTER_NUM 0x20
0029 
0030 struct ksz_stats_raw {
0031     u64 rx_hi;
0032     u64 rx_undersize;
0033     u64 rx_fragments;
0034     u64 rx_oversize;
0035     u64 rx_jabbers;
0036     u64 rx_symbol_err;
0037     u64 rx_crc_err;
0038     u64 rx_align_err;
0039     u64 rx_mac_ctrl;
0040     u64 rx_pause;
0041     u64 rx_bcast;
0042     u64 rx_mcast;
0043     u64 rx_ucast;
0044     u64 rx_64_or_less;
0045     u64 rx_65_127;
0046     u64 rx_128_255;
0047     u64 rx_256_511;
0048     u64 rx_512_1023;
0049     u64 rx_1024_1522;
0050     u64 rx_1523_2000;
0051     u64 rx_2001;
0052     u64 tx_hi;
0053     u64 tx_late_col;
0054     u64 tx_pause;
0055     u64 tx_bcast;
0056     u64 tx_mcast;
0057     u64 tx_ucast;
0058     u64 tx_deferred;
0059     u64 tx_total_col;
0060     u64 tx_exc_col;
0061     u64 tx_single_col;
0062     u64 tx_mult_col;
0063     u64 rx_total;
0064     u64 tx_total;
0065     u64 rx_discards;
0066     u64 tx_discards;
0067 };
0068 
0069 static const struct ksz_mib_names ksz88xx_mib_names[] = {
0070     { 0x00, "rx" },
0071     { 0x01, "rx_hi" },
0072     { 0x02, "rx_undersize" },
0073     { 0x03, "rx_fragments" },
0074     { 0x04, "rx_oversize" },
0075     { 0x05, "rx_jabbers" },
0076     { 0x06, "rx_symbol_err" },
0077     { 0x07, "rx_crc_err" },
0078     { 0x08, "rx_align_err" },
0079     { 0x09, "rx_mac_ctrl" },
0080     { 0x0a, "rx_pause" },
0081     { 0x0b, "rx_bcast" },
0082     { 0x0c, "rx_mcast" },
0083     { 0x0d, "rx_ucast" },
0084     { 0x0e, "rx_64_or_less" },
0085     { 0x0f, "rx_65_127" },
0086     { 0x10, "rx_128_255" },
0087     { 0x11, "rx_256_511" },
0088     { 0x12, "rx_512_1023" },
0089     { 0x13, "rx_1024_1522" },
0090     { 0x14, "tx" },
0091     { 0x15, "tx_hi" },
0092     { 0x16, "tx_late_col" },
0093     { 0x17, "tx_pause" },
0094     { 0x18, "tx_bcast" },
0095     { 0x19, "tx_mcast" },
0096     { 0x1a, "tx_ucast" },
0097     { 0x1b, "tx_deferred" },
0098     { 0x1c, "tx_total_col" },
0099     { 0x1d, "tx_exc_col" },
0100     { 0x1e, "tx_single_col" },
0101     { 0x1f, "tx_mult_col" },
0102     { 0x100, "rx_discards" },
0103     { 0x101, "tx_discards" },
0104 };
0105 
0106 static const struct ksz_mib_names ksz9477_mib_names[] = {
0107     { 0x00, "rx_hi" },
0108     { 0x01, "rx_undersize" },
0109     { 0x02, "rx_fragments" },
0110     { 0x03, "rx_oversize" },
0111     { 0x04, "rx_jabbers" },
0112     { 0x05, "rx_symbol_err" },
0113     { 0x06, "rx_crc_err" },
0114     { 0x07, "rx_align_err" },
0115     { 0x08, "rx_mac_ctrl" },
0116     { 0x09, "rx_pause" },
0117     { 0x0A, "rx_bcast" },
0118     { 0x0B, "rx_mcast" },
0119     { 0x0C, "rx_ucast" },
0120     { 0x0D, "rx_64_or_less" },
0121     { 0x0E, "rx_65_127" },
0122     { 0x0F, "rx_128_255" },
0123     { 0x10, "rx_256_511" },
0124     { 0x11, "rx_512_1023" },
0125     { 0x12, "rx_1024_1522" },
0126     { 0x13, "rx_1523_2000" },
0127     { 0x14, "rx_2001" },
0128     { 0x15, "tx_hi" },
0129     { 0x16, "tx_late_col" },
0130     { 0x17, "tx_pause" },
0131     { 0x18, "tx_bcast" },
0132     { 0x19, "tx_mcast" },
0133     { 0x1A, "tx_ucast" },
0134     { 0x1B, "tx_deferred" },
0135     { 0x1C, "tx_total_col" },
0136     { 0x1D, "tx_exc_col" },
0137     { 0x1E, "tx_single_col" },
0138     { 0x1F, "tx_mult_col" },
0139     { 0x80, "rx_total" },
0140     { 0x81, "tx_total" },
0141     { 0x82, "rx_discards" },
0142     { 0x83, "tx_discards" },
0143 };
0144 
0145 static const struct ksz_dev_ops ksz8_dev_ops = {
0146     .setup = ksz8_setup,
0147     .get_port_addr = ksz8_get_port_addr,
0148     .cfg_port_member = ksz8_cfg_port_member,
0149     .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
0150     .port_setup = ksz8_port_setup,
0151     .r_phy = ksz8_r_phy,
0152     .w_phy = ksz8_w_phy,
0153     .r_mib_cnt = ksz8_r_mib_cnt,
0154     .r_mib_pkt = ksz8_r_mib_pkt,
0155     .freeze_mib = ksz8_freeze_mib,
0156     .port_init_cnt = ksz8_port_init_cnt,
0157     .fdb_dump = ksz8_fdb_dump,
0158     .mdb_add = ksz8_mdb_add,
0159     .mdb_del = ksz8_mdb_del,
0160     .vlan_filtering = ksz8_port_vlan_filtering,
0161     .vlan_add = ksz8_port_vlan_add,
0162     .vlan_del = ksz8_port_vlan_del,
0163     .mirror_add = ksz8_port_mirror_add,
0164     .mirror_del = ksz8_port_mirror_del,
0165     .get_caps = ksz8_get_caps,
0166     .config_cpu_port = ksz8_config_cpu_port,
0167     .enable_stp_addr = ksz8_enable_stp_addr,
0168     .reset = ksz8_reset_switch,
0169     .init = ksz8_switch_init,
0170     .exit = ksz8_switch_exit,
0171 };
0172 
0173 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
0174                     unsigned int mode,
0175                     phy_interface_t interface,
0176                     struct phy_device *phydev, int speed,
0177                     int duplex, bool tx_pause,
0178                     bool rx_pause);
0179 
0180 static const struct ksz_dev_ops ksz9477_dev_ops = {
0181     .setup = ksz9477_setup,
0182     .get_port_addr = ksz9477_get_port_addr,
0183     .cfg_port_member = ksz9477_cfg_port_member,
0184     .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
0185     .port_setup = ksz9477_port_setup,
0186     .r_phy = ksz9477_r_phy,
0187     .w_phy = ksz9477_w_phy,
0188     .r_mib_cnt = ksz9477_r_mib_cnt,
0189     .r_mib_pkt = ksz9477_r_mib_pkt,
0190     .r_mib_stat64 = ksz_r_mib_stats64,
0191     .freeze_mib = ksz9477_freeze_mib,
0192     .port_init_cnt = ksz9477_port_init_cnt,
0193     .vlan_filtering = ksz9477_port_vlan_filtering,
0194     .vlan_add = ksz9477_port_vlan_add,
0195     .vlan_del = ksz9477_port_vlan_del,
0196     .mirror_add = ksz9477_port_mirror_add,
0197     .mirror_del = ksz9477_port_mirror_del,
0198     .get_caps = ksz9477_get_caps,
0199     .fdb_dump = ksz9477_fdb_dump,
0200     .fdb_add = ksz9477_fdb_add,
0201     .fdb_del = ksz9477_fdb_del,
0202     .mdb_add = ksz9477_mdb_add,
0203     .mdb_del = ksz9477_mdb_del,
0204     .change_mtu = ksz9477_change_mtu,
0205     .max_mtu = ksz9477_max_mtu,
0206     .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
0207     .config_cpu_port = ksz9477_config_cpu_port,
0208     .enable_stp_addr = ksz9477_enable_stp_addr,
0209     .reset = ksz9477_reset_switch,
0210     .init = ksz9477_switch_init,
0211     .exit = ksz9477_switch_exit,
0212 };
0213 
0214 static const struct ksz_dev_ops lan937x_dev_ops = {
0215     .setup = lan937x_setup,
0216     .get_port_addr = ksz9477_get_port_addr,
0217     .cfg_port_member = ksz9477_cfg_port_member,
0218     .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
0219     .port_setup = lan937x_port_setup,
0220     .r_phy = lan937x_r_phy,
0221     .w_phy = lan937x_w_phy,
0222     .r_mib_cnt = ksz9477_r_mib_cnt,
0223     .r_mib_pkt = ksz9477_r_mib_pkt,
0224     .r_mib_stat64 = ksz_r_mib_stats64,
0225     .freeze_mib = ksz9477_freeze_mib,
0226     .port_init_cnt = ksz9477_port_init_cnt,
0227     .vlan_filtering = ksz9477_port_vlan_filtering,
0228     .vlan_add = ksz9477_port_vlan_add,
0229     .vlan_del = ksz9477_port_vlan_del,
0230     .mirror_add = ksz9477_port_mirror_add,
0231     .mirror_del = ksz9477_port_mirror_del,
0232     .get_caps = lan937x_phylink_get_caps,
0233     .setup_rgmii_delay = lan937x_setup_rgmii_delay,
0234     .fdb_dump = ksz9477_fdb_dump,
0235     .fdb_add = ksz9477_fdb_add,
0236     .fdb_del = ksz9477_fdb_del,
0237     .mdb_add = ksz9477_mdb_add,
0238     .mdb_del = ksz9477_mdb_del,
0239     .change_mtu = lan937x_change_mtu,
0240     .max_mtu = ksz9477_max_mtu,
0241     .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
0242     .config_cpu_port = lan937x_config_cpu_port,
0243     .enable_stp_addr = ksz9477_enable_stp_addr,
0244     .reset = lan937x_reset_switch,
0245     .init = lan937x_switch_init,
0246     .exit = lan937x_switch_exit,
0247 };
0248 
0249 static const u16 ksz8795_regs[] = {
0250     [REG_IND_CTRL_0]        = 0x6E,
0251     [REG_IND_DATA_8]        = 0x70,
0252     [REG_IND_DATA_CHECK]        = 0x72,
0253     [REG_IND_DATA_HI]       = 0x71,
0254     [REG_IND_DATA_LO]       = 0x75,
0255     [REG_IND_MIB_CHECK]     = 0x74,
0256     [REG_IND_BYTE]          = 0xA0,
0257     [P_FORCE_CTRL]          = 0x0C,
0258     [P_LINK_STATUS]         = 0x0E,
0259     [P_LOCAL_CTRL]          = 0x07,
0260     [P_NEG_RESTART_CTRL]        = 0x0D,
0261     [P_REMOTE_STATUS]       = 0x08,
0262     [P_SPEED_STATUS]        = 0x09,
0263     [S_TAIL_TAG_CTRL]       = 0x0C,
0264     [P_STP_CTRL]            = 0x02,
0265     [S_START_CTRL]          = 0x01,
0266     [S_BROADCAST_CTRL]      = 0x06,
0267     [S_MULTICAST_CTRL]      = 0x04,
0268     [P_XMII_CTRL_0]         = 0x06,
0269     [P_XMII_CTRL_1]         = 0x56,
0270 };
0271 
0272 static const u32 ksz8795_masks[] = {
0273     [PORT_802_1P_REMAPPING]     = BIT(7),
0274     [SW_TAIL_TAG_ENABLE]        = BIT(1),
0275     [MIB_COUNTER_OVERFLOW]      = BIT(6),
0276     [MIB_COUNTER_VALID]     = BIT(5),
0277     [VLAN_TABLE_FID]        = GENMASK(6, 0),
0278     [VLAN_TABLE_MEMBERSHIP]     = GENMASK(11, 7),
0279     [VLAN_TABLE_VALID]      = BIT(12),
0280     [STATIC_MAC_TABLE_VALID]    = BIT(21),
0281     [STATIC_MAC_TABLE_USE_FID]  = BIT(23),
0282     [STATIC_MAC_TABLE_FID]      = GENMASK(30, 24),
0283     [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
0284     [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(24, 20),
0285     [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(6, 0),
0286     [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(8),
0287     [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
0288     [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
0289     [DYNAMIC_MAC_TABLE_FID]     = GENMASK(26, 20),
0290     [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
0291     [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
0292     [P_MII_TX_FLOW_CTRL]        = BIT(5),
0293     [P_MII_RX_FLOW_CTRL]        = BIT(5),
0294 };
0295 
0296 static const u8 ksz8795_xmii_ctrl0[] = {
0297     [P_MII_100MBIT]         = 0,
0298     [P_MII_10MBIT]          = 1,
0299     [P_MII_FULL_DUPLEX]     = 0,
0300     [P_MII_HALF_DUPLEX]     = 1,
0301 };
0302 
0303 static const u8 ksz8795_xmii_ctrl1[] = {
0304     [P_RGMII_SEL]           = 3,
0305     [P_GMII_SEL]            = 2,
0306     [P_RMII_SEL]            = 1,
0307     [P_MII_SEL]         = 0,
0308     [P_GMII_1GBIT]          = 1,
0309     [P_GMII_NOT_1GBIT]      = 0,
0310 };
0311 
0312 static const u8 ksz8795_shifts[] = {
0313     [VLAN_TABLE_MEMBERSHIP_S]   = 7,
0314     [VLAN_TABLE]            = 16,
0315     [STATIC_MAC_FWD_PORTS]      = 16,
0316     [STATIC_MAC_FID]        = 24,
0317     [DYNAMIC_MAC_ENTRIES_H]     = 3,
0318     [DYNAMIC_MAC_ENTRIES]       = 29,
0319     [DYNAMIC_MAC_FID]       = 16,
0320     [DYNAMIC_MAC_TIMESTAMP]     = 27,
0321     [DYNAMIC_MAC_SRC_PORT]      = 24,
0322 };
0323 
0324 static const u16 ksz8863_regs[] = {
0325     [REG_IND_CTRL_0]        = 0x79,
0326     [REG_IND_DATA_8]        = 0x7B,
0327     [REG_IND_DATA_CHECK]        = 0x7B,
0328     [REG_IND_DATA_HI]       = 0x7C,
0329     [REG_IND_DATA_LO]       = 0x80,
0330     [REG_IND_MIB_CHECK]     = 0x80,
0331     [P_FORCE_CTRL]          = 0x0C,
0332     [P_LINK_STATUS]         = 0x0E,
0333     [P_LOCAL_CTRL]          = 0x0C,
0334     [P_NEG_RESTART_CTRL]        = 0x0D,
0335     [P_REMOTE_STATUS]       = 0x0E,
0336     [P_SPEED_STATUS]        = 0x0F,
0337     [S_TAIL_TAG_CTRL]       = 0x03,
0338     [P_STP_CTRL]            = 0x02,
0339     [S_START_CTRL]          = 0x01,
0340     [S_BROADCAST_CTRL]      = 0x06,
0341     [S_MULTICAST_CTRL]      = 0x04,
0342 };
0343 
0344 static const u32 ksz8863_masks[] = {
0345     [PORT_802_1P_REMAPPING]     = BIT(3),
0346     [SW_TAIL_TAG_ENABLE]        = BIT(6),
0347     [MIB_COUNTER_OVERFLOW]      = BIT(7),
0348     [MIB_COUNTER_VALID]     = BIT(6),
0349     [VLAN_TABLE_FID]        = GENMASK(15, 12),
0350     [VLAN_TABLE_MEMBERSHIP]     = GENMASK(18, 16),
0351     [VLAN_TABLE_VALID]      = BIT(19),
0352     [STATIC_MAC_TABLE_VALID]    = BIT(19),
0353     [STATIC_MAC_TABLE_USE_FID]  = BIT(21),
0354     [STATIC_MAC_TABLE_FID]      = GENMASK(29, 26),
0355     [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
0356     [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(18, 16),
0357     [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(5, 0),
0358     [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(7),
0359     [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
0360     [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
0361     [DYNAMIC_MAC_TABLE_FID]     = GENMASK(19, 16),
0362     [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(21, 20),
0363     [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(23, 22),
0364 };
0365 
0366 static u8 ksz8863_shifts[] = {
0367     [VLAN_TABLE_MEMBERSHIP_S]   = 16,
0368     [STATIC_MAC_FWD_PORTS]      = 16,
0369     [STATIC_MAC_FID]        = 22,
0370     [DYNAMIC_MAC_ENTRIES_H]     = 3,
0371     [DYNAMIC_MAC_ENTRIES]       = 24,
0372     [DYNAMIC_MAC_FID]       = 16,
0373     [DYNAMIC_MAC_TIMESTAMP]     = 24,
0374     [DYNAMIC_MAC_SRC_PORT]      = 20,
0375 };
0376 
0377 static const u16 ksz9477_regs[] = {
0378     [P_STP_CTRL]            = 0x0B04,
0379     [S_START_CTRL]          = 0x0300,
0380     [S_BROADCAST_CTRL]      = 0x0332,
0381     [S_MULTICAST_CTRL]      = 0x0331,
0382     [P_XMII_CTRL_0]         = 0x0300,
0383     [P_XMII_CTRL_1]         = 0x0301,
0384 };
0385 
0386 static const u32 ksz9477_masks[] = {
0387     [ALU_STAT_WRITE]        = 0,
0388     [ALU_STAT_READ]         = 1,
0389     [P_MII_TX_FLOW_CTRL]        = BIT(5),
0390     [P_MII_RX_FLOW_CTRL]        = BIT(3),
0391 };
0392 
0393 static const u8 ksz9477_shifts[] = {
0394     [ALU_STAT_INDEX]        = 16,
0395 };
0396 
0397 static const u8 ksz9477_xmii_ctrl0[] = {
0398     [P_MII_100MBIT]         = 1,
0399     [P_MII_10MBIT]          = 0,
0400     [P_MII_FULL_DUPLEX]     = 1,
0401     [P_MII_HALF_DUPLEX]     = 0,
0402 };
0403 
0404 static const u8 ksz9477_xmii_ctrl1[] = {
0405     [P_RGMII_SEL]           = 0,
0406     [P_RMII_SEL]            = 1,
0407     [P_GMII_SEL]            = 2,
0408     [P_MII_SEL]         = 3,
0409     [P_GMII_1GBIT]          = 0,
0410     [P_GMII_NOT_1GBIT]      = 1,
0411 };
0412 
0413 static const u32 lan937x_masks[] = {
0414     [ALU_STAT_WRITE]        = 1,
0415     [ALU_STAT_READ]         = 2,
0416     [P_MII_TX_FLOW_CTRL]        = BIT(5),
0417     [P_MII_RX_FLOW_CTRL]        = BIT(3),
0418 };
0419 
0420 static const u8 lan937x_shifts[] = {
0421     [ALU_STAT_INDEX]        = 8,
0422 };
0423 
0424 const struct ksz_chip_data ksz_switch_chips[] = {
0425     [KSZ8795] = {
0426         .chip_id = KSZ8795_CHIP_ID,
0427         .dev_name = "KSZ8795",
0428         .num_vlans = 4096,
0429         .num_alus = 0,
0430         .num_statics = 8,
0431         .cpu_ports = 0x10,  /* can be configured as cpu port */
0432         .port_cnt = 5,      /* total cpu and user ports */
0433         .ops = &ksz8_dev_ops,
0434         .ksz87xx_eee_link_erratum = true,
0435         .mib_names = ksz9477_mib_names,
0436         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0437         .reg_mib_cnt = MIB_COUNTER_NUM,
0438         .regs = ksz8795_regs,
0439         .masks = ksz8795_masks,
0440         .shifts = ksz8795_shifts,
0441         .xmii_ctrl0 = ksz8795_xmii_ctrl0,
0442         .xmii_ctrl1 = ksz8795_xmii_ctrl1,
0443         .supports_mii = {false, false, false, false, true},
0444         .supports_rmii = {false, false, false, false, true},
0445         .supports_rgmii = {false, false, false, false, true},
0446         .internal_phy = {true, true, true, true, false},
0447     },
0448 
0449     [KSZ8794] = {
0450         /* WARNING
0451          * =======
0452          * KSZ8794 is similar to KSZ8795, except the port map
0453          * contains a gap between external and CPU ports, the
0454          * port map is NOT continuous. The per-port register
0455          * map is shifted accordingly too, i.e. registers at
0456          * offset 0x40 are NOT used on KSZ8794 and they ARE
0457          * used on KSZ8795 for external port 3.
0458          *           external  cpu
0459          * KSZ8794   0,1,2      4
0460          * KSZ8795   0,1,2,3    4
0461          * KSZ8765   0,1,2,3    4
0462          * port_cnt is configured as 5, even though it is 4
0463          */
0464         .chip_id = KSZ8794_CHIP_ID,
0465         .dev_name = "KSZ8794",
0466         .num_vlans = 4096,
0467         .num_alus = 0,
0468         .num_statics = 8,
0469         .cpu_ports = 0x10,  /* can be configured as cpu port */
0470         .port_cnt = 5,      /* total cpu and user ports */
0471         .ops = &ksz8_dev_ops,
0472         .ksz87xx_eee_link_erratum = true,
0473         .mib_names = ksz9477_mib_names,
0474         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0475         .reg_mib_cnt = MIB_COUNTER_NUM,
0476         .regs = ksz8795_regs,
0477         .masks = ksz8795_masks,
0478         .shifts = ksz8795_shifts,
0479         .xmii_ctrl0 = ksz8795_xmii_ctrl0,
0480         .xmii_ctrl1 = ksz8795_xmii_ctrl1,
0481         .supports_mii = {false, false, false, false, true},
0482         .supports_rmii = {false, false, false, false, true},
0483         .supports_rgmii = {false, false, false, false, true},
0484         .internal_phy = {true, true, true, false, false},
0485     },
0486 
0487     [KSZ8765] = {
0488         .chip_id = KSZ8765_CHIP_ID,
0489         .dev_name = "KSZ8765",
0490         .num_vlans = 4096,
0491         .num_alus = 0,
0492         .num_statics = 8,
0493         .cpu_ports = 0x10,  /* can be configured as cpu port */
0494         .port_cnt = 5,      /* total cpu and user ports */
0495         .ops = &ksz8_dev_ops,
0496         .ksz87xx_eee_link_erratum = true,
0497         .mib_names = ksz9477_mib_names,
0498         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0499         .reg_mib_cnt = MIB_COUNTER_NUM,
0500         .regs = ksz8795_regs,
0501         .masks = ksz8795_masks,
0502         .shifts = ksz8795_shifts,
0503         .xmii_ctrl0 = ksz8795_xmii_ctrl0,
0504         .xmii_ctrl1 = ksz8795_xmii_ctrl1,
0505         .supports_mii = {false, false, false, false, true},
0506         .supports_rmii = {false, false, false, false, true},
0507         .supports_rgmii = {false, false, false, false, true},
0508         .internal_phy = {true, true, true, true, false},
0509     },
0510 
0511     [KSZ8830] = {
0512         .chip_id = KSZ8830_CHIP_ID,
0513         .dev_name = "KSZ8863/KSZ8873",
0514         .num_vlans = 16,
0515         .num_alus = 0,
0516         .num_statics = 8,
0517         .cpu_ports = 0x4,   /* can be configured as cpu port */
0518         .port_cnt = 3,
0519         .ops = &ksz8_dev_ops,
0520         .mib_names = ksz88xx_mib_names,
0521         .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
0522         .reg_mib_cnt = MIB_COUNTER_NUM,
0523         .regs = ksz8863_regs,
0524         .masks = ksz8863_masks,
0525         .shifts = ksz8863_shifts,
0526         .supports_mii = {false, false, true},
0527         .supports_rmii = {false, false, true},
0528         .internal_phy = {true, true, false},
0529     },
0530 
0531     [KSZ9477] = {
0532         .chip_id = KSZ9477_CHIP_ID,
0533         .dev_name = "KSZ9477",
0534         .num_vlans = 4096,
0535         .num_alus = 4096,
0536         .num_statics = 16,
0537         .cpu_ports = 0x7F,  /* can be configured as cpu port */
0538         .port_cnt = 7,      /* total physical port count */
0539         .ops = &ksz9477_dev_ops,
0540         .phy_errata_9477 = true,
0541         .mib_names = ksz9477_mib_names,
0542         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0543         .reg_mib_cnt = MIB_COUNTER_NUM,
0544         .regs = ksz9477_regs,
0545         .masks = ksz9477_masks,
0546         .shifts = ksz9477_shifts,
0547         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0548         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0549         .supports_mii   = {false, false, false, false,
0550                    false, true, false},
0551         .supports_rmii  = {false, false, false, false,
0552                    false, true, false},
0553         .supports_rgmii = {false, false, false, false,
0554                    false, true, false},
0555         .internal_phy   = {true, true, true, true,
0556                    true, false, false},
0557     },
0558 
0559     [KSZ9897] = {
0560         .chip_id = KSZ9897_CHIP_ID,
0561         .dev_name = "KSZ9897",
0562         .num_vlans = 4096,
0563         .num_alus = 4096,
0564         .num_statics = 16,
0565         .cpu_ports = 0x7F,  /* can be configured as cpu port */
0566         .port_cnt = 7,      /* total physical port count */
0567         .ops = &ksz9477_dev_ops,
0568         .phy_errata_9477 = true,
0569         .mib_names = ksz9477_mib_names,
0570         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0571         .reg_mib_cnt = MIB_COUNTER_NUM,
0572         .regs = ksz9477_regs,
0573         .masks = ksz9477_masks,
0574         .shifts = ksz9477_shifts,
0575         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0576         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0577         .supports_mii   = {false, false, false, false,
0578                    false, true, true},
0579         .supports_rmii  = {false, false, false, false,
0580                    false, true, true},
0581         .supports_rgmii = {false, false, false, false,
0582                    false, true, true},
0583         .internal_phy   = {true, true, true, true,
0584                    true, false, false},
0585     },
0586 
0587     [KSZ9893] = {
0588         .chip_id = KSZ9893_CHIP_ID,
0589         .dev_name = "KSZ9893",
0590         .num_vlans = 4096,
0591         .num_alus = 4096,
0592         .num_statics = 16,
0593         .cpu_ports = 0x07,  /* can be configured as cpu port */
0594         .port_cnt = 3,      /* total port count */
0595         .ops = &ksz9477_dev_ops,
0596         .mib_names = ksz9477_mib_names,
0597         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0598         .reg_mib_cnt = MIB_COUNTER_NUM,
0599         .regs = ksz9477_regs,
0600         .masks = ksz9477_masks,
0601         .shifts = ksz9477_shifts,
0602         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0603         .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
0604         .supports_mii = {false, false, true},
0605         .supports_rmii = {false, false, true},
0606         .supports_rgmii = {false, false, true},
0607         .internal_phy = {true, true, false},
0608     },
0609 
0610     [KSZ9567] = {
0611         .chip_id = KSZ9567_CHIP_ID,
0612         .dev_name = "KSZ9567",
0613         .num_vlans = 4096,
0614         .num_alus = 4096,
0615         .num_statics = 16,
0616         .cpu_ports = 0x7F,  /* can be configured as cpu port */
0617         .port_cnt = 7,      /* total physical port count */
0618         .ops = &ksz9477_dev_ops,
0619         .phy_errata_9477 = true,
0620         .mib_names = ksz9477_mib_names,
0621         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0622         .reg_mib_cnt = MIB_COUNTER_NUM,
0623         .regs = ksz9477_regs,
0624         .masks = ksz9477_masks,
0625         .shifts = ksz9477_shifts,
0626         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0627         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0628         .supports_mii   = {false, false, false, false,
0629                    false, true, true},
0630         .supports_rmii  = {false, false, false, false,
0631                    false, true, true},
0632         .supports_rgmii = {false, false, false, false,
0633                    false, true, true},
0634         .internal_phy   = {true, true, true, true,
0635                    true, false, false},
0636     },
0637 
0638     [LAN9370] = {
0639         .chip_id = LAN9370_CHIP_ID,
0640         .dev_name = "LAN9370",
0641         .num_vlans = 4096,
0642         .num_alus = 1024,
0643         .num_statics = 256,
0644         .cpu_ports = 0x10,  /* can be configured as cpu port */
0645         .port_cnt = 5,      /* total physical port count */
0646         .ops = &lan937x_dev_ops,
0647         .mib_names = ksz9477_mib_names,
0648         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0649         .reg_mib_cnt = MIB_COUNTER_NUM,
0650         .regs = ksz9477_regs,
0651         .masks = lan937x_masks,
0652         .shifts = lan937x_shifts,
0653         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0654         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0655         .supports_mii = {false, false, false, false, true},
0656         .supports_rmii = {false, false, false, false, true},
0657         .supports_rgmii = {false, false, false, false, true},
0658         .internal_phy = {true, true, true, true, false},
0659     },
0660 
0661     [LAN9371] = {
0662         .chip_id = LAN9371_CHIP_ID,
0663         .dev_name = "LAN9371",
0664         .num_vlans = 4096,
0665         .num_alus = 1024,
0666         .num_statics = 256,
0667         .cpu_ports = 0x30,  /* can be configured as cpu port */
0668         .port_cnt = 6,      /* total physical port count */
0669         .ops = &lan937x_dev_ops,
0670         .mib_names = ksz9477_mib_names,
0671         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0672         .reg_mib_cnt = MIB_COUNTER_NUM,
0673         .regs = ksz9477_regs,
0674         .masks = lan937x_masks,
0675         .shifts = lan937x_shifts,
0676         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0677         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0678         .supports_mii = {false, false, false, false, true, true},
0679         .supports_rmii = {false, false, false, false, true, true},
0680         .supports_rgmii = {false, false, false, false, true, true},
0681         .internal_phy = {true, true, true, true, false, false},
0682     },
0683 
0684     [LAN9372] = {
0685         .chip_id = LAN9372_CHIP_ID,
0686         .dev_name = "LAN9372",
0687         .num_vlans = 4096,
0688         .num_alus = 1024,
0689         .num_statics = 256,
0690         .cpu_ports = 0x30,  /* can be configured as cpu port */
0691         .port_cnt = 8,      /* total physical port count */
0692         .ops = &lan937x_dev_ops,
0693         .mib_names = ksz9477_mib_names,
0694         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0695         .reg_mib_cnt = MIB_COUNTER_NUM,
0696         .regs = ksz9477_regs,
0697         .masks = lan937x_masks,
0698         .shifts = lan937x_shifts,
0699         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0700         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0701         .supports_mii   = {false, false, false, false,
0702                    true, true, false, false},
0703         .supports_rmii  = {false, false, false, false,
0704                    true, true, false, false},
0705         .supports_rgmii = {false, false, false, false,
0706                    true, true, false, false},
0707         .internal_phy   = {true, true, true, true,
0708                    false, false, true, true},
0709     },
0710 
0711     [LAN9373] = {
0712         .chip_id = LAN9373_CHIP_ID,
0713         .dev_name = "LAN9373",
0714         .num_vlans = 4096,
0715         .num_alus = 1024,
0716         .num_statics = 256,
0717         .cpu_ports = 0x38,  /* can be configured as cpu port */
0718         .port_cnt = 5,      /* total physical port count */
0719         .ops = &lan937x_dev_ops,
0720         .mib_names = ksz9477_mib_names,
0721         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0722         .reg_mib_cnt = MIB_COUNTER_NUM,
0723         .regs = ksz9477_regs,
0724         .masks = lan937x_masks,
0725         .shifts = lan937x_shifts,
0726         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0727         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0728         .supports_mii   = {false, false, false, false,
0729                    true, true, false, false},
0730         .supports_rmii  = {false, false, false, false,
0731                    true, true, false, false},
0732         .supports_rgmii = {false, false, false, false,
0733                    true, true, false, false},
0734         .internal_phy   = {true, true, true, false,
0735                    false, false, true, true},
0736     },
0737 
0738     [LAN9374] = {
0739         .chip_id = LAN9374_CHIP_ID,
0740         .dev_name = "LAN9374",
0741         .num_vlans = 4096,
0742         .num_alus = 1024,
0743         .num_statics = 256,
0744         .cpu_ports = 0x30,  /* can be configured as cpu port */
0745         .port_cnt = 8,      /* total physical port count */
0746         .ops = &lan937x_dev_ops,
0747         .mib_names = ksz9477_mib_names,
0748         .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
0749         .reg_mib_cnt = MIB_COUNTER_NUM,
0750         .regs = ksz9477_regs,
0751         .masks = lan937x_masks,
0752         .shifts = lan937x_shifts,
0753         .xmii_ctrl0 = ksz9477_xmii_ctrl0,
0754         .xmii_ctrl1 = ksz9477_xmii_ctrl1,
0755         .supports_mii   = {false, false, false, false,
0756                    true, true, false, false},
0757         .supports_rmii  = {false, false, false, false,
0758                    true, true, false, false},
0759         .supports_rgmii = {false, false, false, false,
0760                    true, true, false, false},
0761         .internal_phy   = {true, true, true, true,
0762                    false, false, true, true},
0763     },
0764 };
0765 EXPORT_SYMBOL_GPL(ksz_switch_chips);
0766 
0767 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
0768 {
0769     int i;
0770 
0771     for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
0772         const struct ksz_chip_data *chip = &ksz_switch_chips[i];
0773 
0774         if (chip->chip_id == prod_num)
0775             return chip;
0776     }
0777 
0778     return NULL;
0779 }
0780 
0781 static int ksz_check_device_id(struct ksz_device *dev)
0782 {
0783     const struct ksz_chip_data *dt_chip_data;
0784 
0785     dt_chip_data = of_device_get_match_data(dev->dev);
0786 
0787     /* Check for Device Tree and Chip ID */
0788     if (dt_chip_data->chip_id != dev->chip_id) {
0789         dev_err(dev->dev,
0790             "Device tree specifies chip %s but found %s, please fix it!\n",
0791             dt_chip_data->dev_name, dev->info->dev_name);
0792         return -ENODEV;
0793     }
0794 
0795     return 0;
0796 }
0797 
0798 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
0799                  struct phylink_config *config)
0800 {
0801     struct ksz_device *dev = ds->priv;
0802 
0803     config->legacy_pre_march2020 = false;
0804 
0805     if (dev->info->supports_mii[port])
0806         __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
0807 
0808     if (dev->info->supports_rmii[port])
0809         __set_bit(PHY_INTERFACE_MODE_RMII,
0810               config->supported_interfaces);
0811 
0812     if (dev->info->supports_rgmii[port])
0813         phy_interface_set_rgmii(config->supported_interfaces);
0814 
0815     if (dev->info->internal_phy[port]) {
0816         __set_bit(PHY_INTERFACE_MODE_INTERNAL,
0817               config->supported_interfaces);
0818         /* Compatibility for phylib's default interface type when the
0819          * phy-mode property is absent
0820          */
0821         __set_bit(PHY_INTERFACE_MODE_GMII,
0822               config->supported_interfaces);
0823     }
0824 
0825     if (dev->dev_ops->get_caps)
0826         dev->dev_ops->get_caps(dev, port, config);
0827 }
0828 
0829 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
0830 {
0831     struct ethtool_pause_stats *pstats;
0832     struct rtnl_link_stats64 *stats;
0833     struct ksz_stats_raw *raw;
0834     struct ksz_port_mib *mib;
0835 
0836     mib = &dev->ports[port].mib;
0837     stats = &mib->stats64;
0838     pstats = &mib->pause_stats;
0839     raw = (struct ksz_stats_raw *)mib->counters;
0840 
0841     spin_lock(&mib->stats64_lock);
0842 
0843     stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
0844         raw->rx_pause;
0845     stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
0846         raw->tx_pause;
0847 
0848     /* HW counters are counting bytes + FCS which is not acceptable
0849      * for rtnl_link_stats64 interface
0850      */
0851     stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
0852     stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
0853 
0854     stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
0855         raw->rx_oversize;
0856 
0857     stats->rx_crc_errors = raw->rx_crc_err;
0858     stats->rx_frame_errors = raw->rx_align_err;
0859     stats->rx_dropped = raw->rx_discards;
0860     stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
0861         stats->rx_frame_errors  + stats->rx_dropped;
0862 
0863     stats->tx_window_errors = raw->tx_late_col;
0864     stats->tx_fifo_errors = raw->tx_discards;
0865     stats->tx_aborted_errors = raw->tx_exc_col;
0866     stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
0867         stats->tx_aborted_errors;
0868 
0869     stats->multicast = raw->rx_mcast;
0870     stats->collisions = raw->tx_total_col;
0871 
0872     pstats->tx_pause_frames = raw->tx_pause;
0873     pstats->rx_pause_frames = raw->rx_pause;
0874 
0875     spin_unlock(&mib->stats64_lock);
0876 }
0877 
0878 static void ksz_get_stats64(struct dsa_switch *ds, int port,
0879                 struct rtnl_link_stats64 *s)
0880 {
0881     struct ksz_device *dev = ds->priv;
0882     struct ksz_port_mib *mib;
0883 
0884     mib = &dev->ports[port].mib;
0885 
0886     spin_lock(&mib->stats64_lock);
0887     memcpy(s, &mib->stats64, sizeof(*s));
0888     spin_unlock(&mib->stats64_lock);
0889 }
0890 
0891 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
0892                 struct ethtool_pause_stats *pause_stats)
0893 {
0894     struct ksz_device *dev = ds->priv;
0895     struct ksz_port_mib *mib;
0896 
0897     mib = &dev->ports[port].mib;
0898 
0899     spin_lock(&mib->stats64_lock);
0900     memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
0901     spin_unlock(&mib->stats64_lock);
0902 }
0903 
0904 static void ksz_get_strings(struct dsa_switch *ds, int port,
0905                 u32 stringset, uint8_t *buf)
0906 {
0907     struct ksz_device *dev = ds->priv;
0908     int i;
0909 
0910     if (stringset != ETH_SS_STATS)
0911         return;
0912 
0913     for (i = 0; i < dev->info->mib_cnt; i++) {
0914         memcpy(buf + i * ETH_GSTRING_LEN,
0915                dev->info->mib_names[i].string, ETH_GSTRING_LEN);
0916     }
0917 }
0918 
0919 static void ksz_update_port_member(struct ksz_device *dev, int port)
0920 {
0921     struct ksz_port *p = &dev->ports[port];
0922     struct dsa_switch *ds = dev->ds;
0923     u8 port_member = 0, cpu_port;
0924     const struct dsa_port *dp;
0925     int i, j;
0926 
0927     if (!dsa_is_user_port(ds, port))
0928         return;
0929 
0930     dp = dsa_to_port(ds, port);
0931     cpu_port = BIT(dsa_upstream_port(ds, port));
0932 
0933     for (i = 0; i < ds->num_ports; i++) {
0934         const struct dsa_port *other_dp = dsa_to_port(ds, i);
0935         struct ksz_port *other_p = &dev->ports[i];
0936         u8 val = 0;
0937 
0938         if (!dsa_is_user_port(ds, i))
0939             continue;
0940         if (port == i)
0941             continue;
0942         if (!dsa_port_bridge_same(dp, other_dp))
0943             continue;
0944         if (other_p->stp_state != BR_STATE_FORWARDING)
0945             continue;
0946 
0947         if (p->stp_state == BR_STATE_FORWARDING) {
0948             val |= BIT(port);
0949             port_member |= BIT(i);
0950         }
0951 
0952         /* Retain port [i]'s relationship to other ports than [port] */
0953         for (j = 0; j < ds->num_ports; j++) {
0954             const struct dsa_port *third_dp;
0955             struct ksz_port *third_p;
0956 
0957             if (j == i)
0958                 continue;
0959             if (j == port)
0960                 continue;
0961             if (!dsa_is_user_port(ds, j))
0962                 continue;
0963             third_p = &dev->ports[j];
0964             if (third_p->stp_state != BR_STATE_FORWARDING)
0965                 continue;
0966             third_dp = dsa_to_port(ds, j);
0967             if (dsa_port_bridge_same(other_dp, third_dp))
0968                 val |= BIT(j);
0969         }
0970 
0971         dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
0972     }
0973 
0974     dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
0975 }
0976 
0977 static int ksz_setup(struct dsa_switch *ds)
0978 {
0979     struct ksz_device *dev = ds->priv;
0980     struct ksz_port *p;
0981     const u16 *regs;
0982     int ret;
0983 
0984     regs = dev->info->regs;
0985 
0986     dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
0987                        dev->info->num_vlans, GFP_KERNEL);
0988     if (!dev->vlan_cache)
0989         return -ENOMEM;
0990 
0991     ret = dev->dev_ops->reset(dev);
0992     if (ret) {
0993         dev_err(ds->dev, "failed to reset switch\n");
0994         return ret;
0995     }
0996 
0997     /* set broadcast storm protection 10% rate */
0998     regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
0999                BROADCAST_STORM_RATE,
1000                (BROADCAST_STORM_VALUE *
1001                BROADCAST_STORM_PROT_RATE) / 100);
1002 
1003     dev->dev_ops->config_cpu_port(ds);
1004 
1005     dev->dev_ops->enable_stp_addr(dev);
1006 
1007     regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
1008                MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
1009 
1010     ksz_init_mib_timer(dev);
1011 
1012     ds->configure_vlan_while_not_filtering = false;
1013 
1014     if (dev->dev_ops->setup) {
1015         ret = dev->dev_ops->setup(ds);
1016         if (ret)
1017             return ret;
1018     }
1019 
1020     /* Start with learning disabled on standalone user ports, and enabled
1021      * on the CPU port. In lack of other finer mechanisms, learning on the
1022      * CPU port will avoid flooding bridge local addresses on the network
1023      * in some cases.
1024      */
1025     p = &dev->ports[dev->cpu_port];
1026     p->learning = true;
1027 
1028     /* start switch */
1029     regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
1030                SW_START, SW_START);
1031 
1032     return 0;
1033 }
1034 
1035 static void port_r_cnt(struct ksz_device *dev, int port)
1036 {
1037     struct ksz_port_mib *mib = &dev->ports[port].mib;
1038     u64 *dropped;
1039 
1040     /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
1041     while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
1042         dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
1043                     &mib->counters[mib->cnt_ptr]);
1044         ++mib->cnt_ptr;
1045     }
1046 
1047     /* last one in storage */
1048     dropped = &mib->counters[dev->info->mib_cnt];
1049 
1050     /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
1051     while (mib->cnt_ptr < dev->info->mib_cnt) {
1052         dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
1053                     dropped, &mib->counters[mib->cnt_ptr]);
1054         ++mib->cnt_ptr;
1055     }
1056     mib->cnt_ptr = 0;
1057 }
1058 
1059 static void ksz_mib_read_work(struct work_struct *work)
1060 {
1061     struct ksz_device *dev = container_of(work, struct ksz_device,
1062                           mib_read.work);
1063     struct ksz_port_mib *mib;
1064     struct ksz_port *p;
1065     int i;
1066 
1067     for (i = 0; i < dev->info->port_cnt; i++) {
1068         if (dsa_is_unused_port(dev->ds, i))
1069             continue;
1070 
1071         p = &dev->ports[i];
1072         mib = &p->mib;
1073         mutex_lock(&mib->cnt_mutex);
1074 
1075         /* Only read MIB counters when the port is told to do.
1076          * If not, read only dropped counters when link is not up.
1077          */
1078         if (!p->read) {
1079             const struct dsa_port *dp = dsa_to_port(dev->ds, i);
1080 
1081             if (!netif_carrier_ok(dp->slave))
1082                 mib->cnt_ptr = dev->info->reg_mib_cnt;
1083         }
1084         port_r_cnt(dev, i);
1085         p->read = false;
1086 
1087         if (dev->dev_ops->r_mib_stat64)
1088             dev->dev_ops->r_mib_stat64(dev, i);
1089 
1090         mutex_unlock(&mib->cnt_mutex);
1091     }
1092 
1093     schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
1094 }
1095 
1096 void ksz_init_mib_timer(struct ksz_device *dev)
1097 {
1098     int i;
1099 
1100     INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
1101 
1102     for (i = 0; i < dev->info->port_cnt; i++) {
1103         struct ksz_port_mib *mib = &dev->ports[i].mib;
1104 
1105         dev->dev_ops->port_init_cnt(dev, i);
1106 
1107         mib->cnt_ptr = 0;
1108         memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
1109     }
1110 }
1111 
1112 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
1113 {
1114     struct ksz_device *dev = ds->priv;
1115     u16 val = 0xffff;
1116 
1117     dev->dev_ops->r_phy(dev, addr, reg, &val);
1118 
1119     return val;
1120 }
1121 
1122 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
1123 {
1124     struct ksz_device *dev = ds->priv;
1125 
1126     dev->dev_ops->w_phy(dev, addr, reg, val);
1127 
1128     return 0;
1129 }
1130 
1131 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
1132 {
1133     struct ksz_device *dev = ds->priv;
1134 
1135     if (dev->chip_id == KSZ8830_CHIP_ID) {
1136         /* Silicon Errata Sheet (DS80000830A):
1137          * Port 1 does not work with LinkMD Cable-Testing.
1138          * Port 1 does not respond to received PAUSE control frames.
1139          */
1140         if (!port)
1141             return MICREL_KSZ8_P1_ERRATA;
1142     }
1143 
1144     return 0;
1145 }
1146 
1147 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
1148                   unsigned int mode, phy_interface_t interface)
1149 {
1150     struct ksz_device *dev = ds->priv;
1151     struct ksz_port *p = &dev->ports[port];
1152 
1153     /* Read all MIB counters when the link is going down. */
1154     p->read = true;
1155     /* timer started */
1156     if (dev->mib_read_interval)
1157         schedule_delayed_work(&dev->mib_read, 0);
1158 }
1159 
1160 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
1161 {
1162     struct ksz_device *dev = ds->priv;
1163 
1164     if (sset != ETH_SS_STATS)
1165         return 0;
1166 
1167     return dev->info->mib_cnt;
1168 }
1169 
1170 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
1171                   uint64_t *buf)
1172 {
1173     const struct dsa_port *dp = dsa_to_port(ds, port);
1174     struct ksz_device *dev = ds->priv;
1175     struct ksz_port_mib *mib;
1176 
1177     mib = &dev->ports[port].mib;
1178     mutex_lock(&mib->cnt_mutex);
1179 
1180     /* Only read dropped counters if no link. */
1181     if (!netif_carrier_ok(dp->slave))
1182         mib->cnt_ptr = dev->info->reg_mib_cnt;
1183     port_r_cnt(dev, port);
1184     memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
1185     mutex_unlock(&mib->cnt_mutex);
1186 }
1187 
1188 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
1189                 struct dsa_bridge bridge,
1190                 bool *tx_fwd_offload,
1191                 struct netlink_ext_ack *extack)
1192 {
1193     /* port_stp_state_set() will be called after to put the port in
1194      * appropriate state so there is no need to do anything.
1195      */
1196 
1197     return 0;
1198 }
1199 
1200 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
1201                   struct dsa_bridge bridge)
1202 {
1203     /* port_stp_state_set() will be called after to put the port in
1204      * forwarding state so there is no need to do anything.
1205      */
1206 }
1207 
1208 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
1209 {
1210     struct ksz_device *dev = ds->priv;
1211 
1212     dev->dev_ops->flush_dyn_mac_table(dev, port);
1213 }
1214 
1215 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
1216                 const unsigned char *addr, u16 vid,
1217                 struct dsa_db db)
1218 {
1219     struct ksz_device *dev = ds->priv;
1220 
1221     if (!dev->dev_ops->fdb_add)
1222         return -EOPNOTSUPP;
1223 
1224     return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
1225 }
1226 
1227 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
1228                 const unsigned char *addr,
1229                 u16 vid, struct dsa_db db)
1230 {
1231     struct ksz_device *dev = ds->priv;
1232 
1233     if (!dev->dev_ops->fdb_del)
1234         return -EOPNOTSUPP;
1235 
1236     return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
1237 }
1238 
1239 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
1240                  dsa_fdb_dump_cb_t *cb, void *data)
1241 {
1242     struct ksz_device *dev = ds->priv;
1243 
1244     if (!dev->dev_ops->fdb_dump)
1245         return -EOPNOTSUPP;
1246 
1247     return dev->dev_ops->fdb_dump(dev, port, cb, data);
1248 }
1249 
1250 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
1251                 const struct switchdev_obj_port_mdb *mdb,
1252                 struct dsa_db db)
1253 {
1254     struct ksz_device *dev = ds->priv;
1255 
1256     if (!dev->dev_ops->mdb_add)
1257         return -EOPNOTSUPP;
1258 
1259     return dev->dev_ops->mdb_add(dev, port, mdb, db);
1260 }
1261 
1262 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
1263                 const struct switchdev_obj_port_mdb *mdb,
1264                 struct dsa_db db)
1265 {
1266     struct ksz_device *dev = ds->priv;
1267 
1268     if (!dev->dev_ops->mdb_del)
1269         return -EOPNOTSUPP;
1270 
1271     return dev->dev_ops->mdb_del(dev, port, mdb, db);
1272 }
1273 
1274 static int ksz_enable_port(struct dsa_switch *ds, int port,
1275                struct phy_device *phy)
1276 {
1277     struct ksz_device *dev = ds->priv;
1278 
1279     if (!dsa_is_user_port(ds, port))
1280         return 0;
1281 
1282     /* setup slave port */
1283     dev->dev_ops->port_setup(dev, port, false);
1284 
1285     /* port_stp_state_set() will be called after to enable the port so
1286      * there is no need to do anything.
1287      */
1288 
1289     return 0;
1290 }
1291 
1292 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1293 {
1294     struct ksz_device *dev = ds->priv;
1295     struct ksz_port *p;
1296     const u16 *regs;
1297     u8 data;
1298 
1299     regs = dev->info->regs;
1300 
1301     ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
1302     data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1303 
1304     p = &dev->ports[port];
1305 
1306     switch (state) {
1307     case BR_STATE_DISABLED:
1308         data |= PORT_LEARN_DISABLE;
1309         break;
1310     case BR_STATE_LISTENING:
1311         data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1312         break;
1313     case BR_STATE_LEARNING:
1314         data |= PORT_RX_ENABLE;
1315         if (!p->learning)
1316             data |= PORT_LEARN_DISABLE;
1317         break;
1318     case BR_STATE_FORWARDING:
1319         data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
1320         if (!p->learning)
1321             data |= PORT_LEARN_DISABLE;
1322         break;
1323     case BR_STATE_BLOCKING:
1324         data |= PORT_LEARN_DISABLE;
1325         break;
1326     default:
1327         dev_err(ds->dev, "invalid STP state: %d\n", state);
1328         return;
1329     }
1330 
1331     ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
1332 
1333     p->stp_state = state;
1334 
1335     ksz_update_port_member(dev, port);
1336 }
1337 
1338 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1339                      struct switchdev_brport_flags flags,
1340                      struct netlink_ext_ack *extack)
1341 {
1342     if (flags.mask & ~BR_LEARNING)
1343         return -EINVAL;
1344 
1345     return 0;
1346 }
1347 
1348 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
1349                  struct switchdev_brport_flags flags,
1350                  struct netlink_ext_ack *extack)
1351 {
1352     struct ksz_device *dev = ds->priv;
1353     struct ksz_port *p = &dev->ports[port];
1354 
1355     if (flags.mask & BR_LEARNING) {
1356         p->learning = !!(flags.val & BR_LEARNING);
1357 
1358         /* Make the change take effect immediately */
1359         ksz_port_stp_state_set(ds, port, p->stp_state);
1360     }
1361 
1362     return 0;
1363 }
1364 
1365 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
1366                           int port,
1367                           enum dsa_tag_protocol mp)
1368 {
1369     struct ksz_device *dev = ds->priv;
1370     enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
1371 
1372     if (dev->chip_id == KSZ8795_CHIP_ID ||
1373         dev->chip_id == KSZ8794_CHIP_ID ||
1374         dev->chip_id == KSZ8765_CHIP_ID)
1375         proto = DSA_TAG_PROTO_KSZ8795;
1376 
1377     if (dev->chip_id == KSZ8830_CHIP_ID ||
1378         dev->chip_id == KSZ9893_CHIP_ID)
1379         proto = DSA_TAG_PROTO_KSZ9893;
1380 
1381     if (dev->chip_id == KSZ9477_CHIP_ID ||
1382         dev->chip_id == KSZ9897_CHIP_ID ||
1383         dev->chip_id == KSZ9567_CHIP_ID)
1384         proto = DSA_TAG_PROTO_KSZ9477;
1385 
1386     if (is_lan937x(dev))
1387         proto = DSA_TAG_PROTO_LAN937X_VALUE;
1388 
1389     return proto;
1390 }
1391 
1392 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
1393                    bool flag, struct netlink_ext_ack *extack)
1394 {
1395     struct ksz_device *dev = ds->priv;
1396 
1397     if (!dev->dev_ops->vlan_filtering)
1398         return -EOPNOTSUPP;
1399 
1400     return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
1401 }
1402 
1403 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
1404                  const struct switchdev_obj_port_vlan *vlan,
1405                  struct netlink_ext_ack *extack)
1406 {
1407     struct ksz_device *dev = ds->priv;
1408 
1409     if (!dev->dev_ops->vlan_add)
1410         return -EOPNOTSUPP;
1411 
1412     return dev->dev_ops->vlan_add(dev, port, vlan, extack);
1413 }
1414 
1415 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
1416                  const struct switchdev_obj_port_vlan *vlan)
1417 {
1418     struct ksz_device *dev = ds->priv;
1419 
1420     if (!dev->dev_ops->vlan_del)
1421         return -EOPNOTSUPP;
1422 
1423     return dev->dev_ops->vlan_del(dev, port, vlan);
1424 }
1425 
1426 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
1427                    struct dsa_mall_mirror_tc_entry *mirror,
1428                    bool ingress, struct netlink_ext_ack *extack)
1429 {
1430     struct ksz_device *dev = ds->priv;
1431 
1432     if (!dev->dev_ops->mirror_add)
1433         return -EOPNOTSUPP;
1434 
1435     return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
1436 }
1437 
1438 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
1439                 struct dsa_mall_mirror_tc_entry *mirror)
1440 {
1441     struct ksz_device *dev = ds->priv;
1442 
1443     if (dev->dev_ops->mirror_del)
1444         dev->dev_ops->mirror_del(dev, port, mirror);
1445 }
1446 
1447 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
1448 {
1449     struct ksz_device *dev = ds->priv;
1450 
1451     if (!dev->dev_ops->change_mtu)
1452         return -EOPNOTSUPP;
1453 
1454     return dev->dev_ops->change_mtu(dev, port, mtu);
1455 }
1456 
1457 static int ksz_max_mtu(struct dsa_switch *ds, int port)
1458 {
1459     struct ksz_device *dev = ds->priv;
1460 
1461     if (!dev->dev_ops->max_mtu)
1462         return -EOPNOTSUPP;
1463 
1464     return dev->dev_ops->max_mtu(dev, port);
1465 }
1466 
1467 static void ksz_set_xmii(struct ksz_device *dev, int port,
1468              phy_interface_t interface)
1469 {
1470     const u8 *bitval = dev->info->xmii_ctrl1;
1471     struct ksz_port *p = &dev->ports[port];
1472     const u16 *regs = dev->info->regs;
1473     u8 data8;
1474 
1475     ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1476 
1477     data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
1478            P_RGMII_ID_EG_ENABLE);
1479 
1480     switch (interface) {
1481     case PHY_INTERFACE_MODE_MII:
1482         data8 |= bitval[P_MII_SEL];
1483         break;
1484     case PHY_INTERFACE_MODE_RMII:
1485         data8 |= bitval[P_RMII_SEL];
1486         break;
1487     case PHY_INTERFACE_MODE_GMII:
1488         data8 |= bitval[P_GMII_SEL];
1489         break;
1490     case PHY_INTERFACE_MODE_RGMII:
1491     case PHY_INTERFACE_MODE_RGMII_ID:
1492     case PHY_INTERFACE_MODE_RGMII_TXID:
1493     case PHY_INTERFACE_MODE_RGMII_RXID:
1494         data8 |= bitval[P_RGMII_SEL];
1495         /* On KSZ9893, disable RGMII in-band status support */
1496         if (dev->features & IS_9893)
1497             data8 &= ~P_MII_MAC_MODE;
1498         break;
1499     default:
1500         dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
1501             phy_modes(interface), port);
1502         return;
1503     }
1504 
1505     if (p->rgmii_tx_val)
1506         data8 |= P_RGMII_ID_EG_ENABLE;
1507 
1508     if (p->rgmii_rx_val)
1509         data8 |= P_RGMII_ID_IG_ENABLE;
1510 
1511     /* Write the updated value */
1512     ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
1513 }
1514 
1515 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
1516 {
1517     const u8 *bitval = dev->info->xmii_ctrl1;
1518     const u16 *regs = dev->info->regs;
1519     phy_interface_t interface;
1520     u8 data8;
1521     u8 val;
1522 
1523     ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1524 
1525     val = FIELD_GET(P_MII_SEL_M, data8);
1526 
1527     if (val == bitval[P_MII_SEL]) {
1528         if (gbit)
1529             interface = PHY_INTERFACE_MODE_GMII;
1530         else
1531             interface = PHY_INTERFACE_MODE_MII;
1532     } else if (val == bitval[P_RMII_SEL]) {
1533         interface = PHY_INTERFACE_MODE_RGMII;
1534     } else {
1535         interface = PHY_INTERFACE_MODE_RGMII;
1536         if (data8 & P_RGMII_ID_EG_ENABLE)
1537             interface = PHY_INTERFACE_MODE_RGMII_TXID;
1538         if (data8 & P_RGMII_ID_IG_ENABLE) {
1539             interface = PHY_INTERFACE_MODE_RGMII_RXID;
1540             if (data8 & P_RGMII_ID_EG_ENABLE)
1541                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1542         }
1543     }
1544 
1545     return interface;
1546 }
1547 
1548 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
1549                    unsigned int mode,
1550                    const struct phylink_link_state *state)
1551 {
1552     struct ksz_device *dev = ds->priv;
1553 
1554     if (ksz_is_ksz88x3(dev))
1555         return;
1556 
1557     /* Internal PHYs */
1558     if (dev->info->internal_phy[port])
1559         return;
1560 
1561     if (phylink_autoneg_inband(mode)) {
1562         dev_err(dev->dev, "In-band AN not supported!\n");
1563         return;
1564     }
1565 
1566     ksz_set_xmii(dev, port, state->interface);
1567 
1568     if (dev->dev_ops->phylink_mac_config)
1569         dev->dev_ops->phylink_mac_config(dev, port, mode, state);
1570 
1571     if (dev->dev_ops->setup_rgmii_delay)
1572         dev->dev_ops->setup_rgmii_delay(dev, port);
1573 }
1574 
1575 bool ksz_get_gbit(struct ksz_device *dev, int port)
1576 {
1577     const u8 *bitval = dev->info->xmii_ctrl1;
1578     const u16 *regs = dev->info->regs;
1579     bool gbit = false;
1580     u8 data8;
1581     bool val;
1582 
1583     ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1584 
1585     val = FIELD_GET(P_GMII_1GBIT_M, data8);
1586 
1587     if (val == bitval[P_GMII_1GBIT])
1588         gbit = true;
1589 
1590     return gbit;
1591 }
1592 
1593 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
1594 {
1595     const u8 *bitval = dev->info->xmii_ctrl1;
1596     const u16 *regs = dev->info->regs;
1597     u8 data8;
1598 
1599     ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1600 
1601     data8 &= ~P_GMII_1GBIT_M;
1602 
1603     if (gbit)
1604         data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
1605     else
1606         data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
1607 
1608     /* Write the updated value */
1609     ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
1610 }
1611 
1612 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
1613 {
1614     const u8 *bitval = dev->info->xmii_ctrl0;
1615     const u16 *regs = dev->info->regs;
1616     u8 data8;
1617 
1618     ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
1619 
1620     data8 &= ~P_MII_100MBIT_M;
1621 
1622     if (speed == SPEED_100)
1623         data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
1624     else
1625         data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
1626 
1627     /* Write the updated value */
1628     ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
1629 }
1630 
1631 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
1632 {
1633     if (speed == SPEED_1000)
1634         ksz_set_gbit(dev, port, true);
1635     else
1636         ksz_set_gbit(dev, port, false);
1637 
1638     if (speed == SPEED_100 || speed == SPEED_10)
1639         ksz_set_100_10mbit(dev, port, speed);
1640 }
1641 
1642 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
1643                 bool tx_pause, bool rx_pause)
1644 {
1645     const u8 *bitval = dev->info->xmii_ctrl0;
1646     const u32 *masks = dev->info->masks;
1647     const u16 *regs = dev->info->regs;
1648     u8 mask;
1649     u8 val;
1650 
1651     mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
1652            masks[P_MII_RX_FLOW_CTRL];
1653 
1654     if (duplex == DUPLEX_FULL)
1655         val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
1656     else
1657         val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
1658 
1659     if (tx_pause)
1660         val |= masks[P_MII_TX_FLOW_CTRL];
1661 
1662     if (rx_pause)
1663         val |= masks[P_MII_RX_FLOW_CTRL];
1664 
1665     ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
1666 }
1667 
1668 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
1669                     unsigned int mode,
1670                     phy_interface_t interface,
1671                     struct phy_device *phydev, int speed,
1672                     int duplex, bool tx_pause,
1673                     bool rx_pause)
1674 {
1675     struct ksz_port *p;
1676 
1677     p = &dev->ports[port];
1678 
1679     /* Internal PHYs */
1680     if (dev->info->internal_phy[port])
1681         return;
1682 
1683     p->phydev.speed = speed;
1684 
1685     ksz_port_set_xmii_speed(dev, port, speed);
1686 
1687     ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
1688 }
1689 
1690 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
1691                     unsigned int mode,
1692                     phy_interface_t interface,
1693                     struct phy_device *phydev, int speed,
1694                     int duplex, bool tx_pause, bool rx_pause)
1695 {
1696     struct ksz_device *dev = ds->priv;
1697 
1698     if (dev->dev_ops->phylink_mac_link_up)
1699         dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
1700                           phydev, speed, duplex,
1701                           tx_pause, rx_pause);
1702 }
1703 
1704 static int ksz_switch_detect(struct ksz_device *dev)
1705 {
1706     u8 id1, id2;
1707     u16 id16;
1708     u32 id32;
1709     int ret;
1710 
1711     /* read chip id */
1712     ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1713     if (ret)
1714         return ret;
1715 
1716     id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
1717     id2 = FIELD_GET(SW_CHIP_ID_M, id16);
1718 
1719     switch (id1) {
1720     case KSZ87_FAMILY_ID:
1721         if (id2 == KSZ87_CHIP_ID_95) {
1722             u8 val;
1723 
1724             dev->chip_id = KSZ8795_CHIP_ID;
1725 
1726             ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
1727             if (val & KSZ8_PORT_FIBER_MODE)
1728                 dev->chip_id = KSZ8765_CHIP_ID;
1729         } else if (id2 == KSZ87_CHIP_ID_94) {
1730             dev->chip_id = KSZ8794_CHIP_ID;
1731         } else {
1732             return -ENODEV;
1733         }
1734         break;
1735     case KSZ88_FAMILY_ID:
1736         if (id2 == KSZ88_CHIP_ID_63)
1737             dev->chip_id = KSZ8830_CHIP_ID;
1738         else
1739             return -ENODEV;
1740         break;
1741     default:
1742         ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
1743         if (ret)
1744             return ret;
1745 
1746         dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
1747         id32 &= ~0xFF;
1748 
1749         switch (id32) {
1750         case KSZ9477_CHIP_ID:
1751         case KSZ9897_CHIP_ID:
1752         case KSZ9893_CHIP_ID:
1753         case KSZ9567_CHIP_ID:
1754         case LAN9370_CHIP_ID:
1755         case LAN9371_CHIP_ID:
1756         case LAN9372_CHIP_ID:
1757         case LAN9373_CHIP_ID:
1758         case LAN9374_CHIP_ID:
1759             dev->chip_id = id32;
1760             break;
1761         default:
1762             dev_err(dev->dev,
1763                 "unsupported switch detected %x)\n", id32);
1764             return -ENODEV;
1765         }
1766     }
1767     return 0;
1768 }
1769 
1770 static const struct dsa_switch_ops ksz_switch_ops = {
1771     .get_tag_protocol   = ksz_get_tag_protocol,
1772     .get_phy_flags      = ksz_get_phy_flags,
1773     .setup          = ksz_setup,
1774     .phy_read       = ksz_phy_read16,
1775     .phy_write      = ksz_phy_write16,
1776     .phylink_get_caps   = ksz_phylink_get_caps,
1777     .phylink_mac_config = ksz_phylink_mac_config,
1778     .phylink_mac_link_up    = ksz_phylink_mac_link_up,
1779     .phylink_mac_link_down  = ksz_mac_link_down,
1780     .port_enable        = ksz_enable_port,
1781     .get_strings        = ksz_get_strings,
1782     .get_ethtool_stats  = ksz_get_ethtool_stats,
1783     .get_sset_count     = ksz_sset_count,
1784     .port_bridge_join   = ksz_port_bridge_join,
1785     .port_bridge_leave  = ksz_port_bridge_leave,
1786     .port_stp_state_set = ksz_port_stp_state_set,
1787     .port_pre_bridge_flags  = ksz_port_pre_bridge_flags,
1788     .port_bridge_flags  = ksz_port_bridge_flags,
1789     .port_fast_age      = ksz_port_fast_age,
1790     .port_vlan_filtering    = ksz_port_vlan_filtering,
1791     .port_vlan_add      = ksz_port_vlan_add,
1792     .port_vlan_del      = ksz_port_vlan_del,
1793     .port_fdb_dump      = ksz_port_fdb_dump,
1794     .port_fdb_add       = ksz_port_fdb_add,
1795     .port_fdb_del       = ksz_port_fdb_del,
1796     .port_mdb_add           = ksz_port_mdb_add,
1797     .port_mdb_del           = ksz_port_mdb_del,
1798     .port_mirror_add    = ksz_port_mirror_add,
1799     .port_mirror_del    = ksz_port_mirror_del,
1800     .get_stats64        = ksz_get_stats64,
1801     .get_pause_stats    = ksz_get_pause_stats,
1802     .port_change_mtu    = ksz_change_mtu,
1803     .port_max_mtu       = ksz_max_mtu,
1804 };
1805 
1806 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
1807 {
1808     struct dsa_switch *ds;
1809     struct ksz_device *swdev;
1810 
1811     ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
1812     if (!ds)
1813         return NULL;
1814 
1815     ds->dev = base;
1816     ds->num_ports = DSA_MAX_PORTS;
1817     ds->ops = &ksz_switch_ops;
1818 
1819     swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
1820     if (!swdev)
1821         return NULL;
1822 
1823     ds->priv = swdev;
1824     swdev->dev = base;
1825 
1826     swdev->ds = ds;
1827     swdev->priv = priv;
1828 
1829     return swdev;
1830 }
1831 EXPORT_SYMBOL(ksz_switch_alloc);
1832 
1833 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
1834                   struct device_node *port_dn)
1835 {
1836     phy_interface_t phy_mode = dev->ports[port_num].interface;
1837     int rx_delay = -1, tx_delay = -1;
1838 
1839     if (!phy_interface_mode_is_rgmii(phy_mode))
1840         return;
1841 
1842     of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1843     of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1844 
1845     if (rx_delay == -1 && tx_delay == -1) {
1846         dev_warn(dev->dev,
1847              "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1848              "please update device tree to specify \"rx-internal-delay-ps\" and "
1849              "\"tx-internal-delay-ps\"",
1850              port_num);
1851 
1852         if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1853             phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1854             rx_delay = 2000;
1855 
1856         if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1857             phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1858             tx_delay = 2000;
1859     }
1860 
1861     if (rx_delay < 0)
1862         rx_delay = 0;
1863     if (tx_delay < 0)
1864         tx_delay = 0;
1865 
1866     dev->ports[port_num].rgmii_rx_val = rx_delay;
1867     dev->ports[port_num].rgmii_tx_val = tx_delay;
1868 }
1869 
1870 int ksz_switch_register(struct ksz_device *dev)
1871 {
1872     const struct ksz_chip_data *info;
1873     struct device_node *port, *ports;
1874     phy_interface_t interface;
1875     unsigned int port_num;
1876     int ret;
1877     int i;
1878 
1879     if (dev->pdata)
1880         dev->chip_id = dev->pdata->chip_id;
1881 
1882     dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
1883                           GPIOD_OUT_LOW);
1884     if (IS_ERR(dev->reset_gpio))
1885         return PTR_ERR(dev->reset_gpio);
1886 
1887     if (dev->reset_gpio) {
1888         gpiod_set_value_cansleep(dev->reset_gpio, 1);
1889         usleep_range(10000, 12000);
1890         gpiod_set_value_cansleep(dev->reset_gpio, 0);
1891         msleep(100);
1892     }
1893 
1894     mutex_init(&dev->dev_mutex);
1895     mutex_init(&dev->regmap_mutex);
1896     mutex_init(&dev->alu_mutex);
1897     mutex_init(&dev->vlan_mutex);
1898 
1899     ret = ksz_switch_detect(dev);
1900     if (ret)
1901         return ret;
1902 
1903     info = ksz_lookup_info(dev->chip_id);
1904     if (!info)
1905         return -ENODEV;
1906 
1907     /* Update the compatible info with the probed one */
1908     dev->info = info;
1909 
1910     dev_info(dev->dev, "found switch: %s, rev %i\n",
1911          dev->info->dev_name, dev->chip_rev);
1912 
1913     ret = ksz_check_device_id(dev);
1914     if (ret)
1915         return ret;
1916 
1917     dev->dev_ops = dev->info->ops;
1918 
1919     ret = dev->dev_ops->init(dev);
1920     if (ret)
1921         return ret;
1922 
1923     dev->ports = devm_kzalloc(dev->dev,
1924                   dev->info->port_cnt * sizeof(struct ksz_port),
1925                   GFP_KERNEL);
1926     if (!dev->ports)
1927         return -ENOMEM;
1928 
1929     for (i = 0; i < dev->info->port_cnt; i++) {
1930         spin_lock_init(&dev->ports[i].mib.stats64_lock);
1931         mutex_init(&dev->ports[i].mib.cnt_mutex);
1932         dev->ports[i].mib.counters =
1933             devm_kzalloc(dev->dev,
1934                      sizeof(u64) * (dev->info->mib_cnt + 1),
1935                      GFP_KERNEL);
1936         if (!dev->ports[i].mib.counters)
1937             return -ENOMEM;
1938     }
1939 
1940     /* set the real number of ports */
1941     dev->ds->num_ports = dev->info->port_cnt;
1942 
1943     /* Host port interface will be self detected, or specifically set in
1944      * device tree.
1945      */
1946     for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
1947         dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
1948     if (dev->dev->of_node) {
1949         ret = of_get_phy_mode(dev->dev->of_node, &interface);
1950         if (ret == 0)
1951             dev->compat_interface = interface;
1952         ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
1953         if (!ports)
1954             ports = of_get_child_by_name(dev->dev->of_node, "ports");
1955         if (ports) {
1956             for_each_available_child_of_node(ports, port) {
1957                 if (of_property_read_u32(port, "reg",
1958                              &port_num))
1959                     continue;
1960                 if (!(dev->port_mask & BIT(port_num))) {
1961                     of_node_put(port);
1962                     of_node_put(ports);
1963                     return -EINVAL;
1964                 }
1965                 of_get_phy_mode(port,
1966                         &dev->ports[port_num].interface);
1967 
1968                 ksz_parse_rgmii_delay(dev, port_num, port);
1969             }
1970             of_node_put(ports);
1971         }
1972         dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
1973                              "microchip,synclko-125");
1974         dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
1975                                  "microchip,synclko-disable");
1976         if (dev->synclko_125 && dev->synclko_disable) {
1977             dev_err(dev->dev, "inconsistent synclko settings\n");
1978             return -EINVAL;
1979         }
1980     }
1981 
1982     ret = dsa_register_switch(dev->ds);
1983     if (ret) {
1984         dev->dev_ops->exit(dev);
1985         return ret;
1986     }
1987 
1988     /* Read MIB counters every 30 seconds to avoid overflow. */
1989     dev->mib_read_interval = msecs_to_jiffies(5000);
1990 
1991     /* Start the MIB timer. */
1992     schedule_delayed_work(&dev->mib_read, 0);
1993 
1994     return ret;
1995 }
1996 EXPORT_SYMBOL(ksz_switch_register);
1997 
1998 void ksz_switch_remove(struct ksz_device *dev)
1999 {
2000     /* timer started */
2001     if (dev->mib_read_interval) {
2002         dev->mib_read_interval = 0;
2003         cancel_delayed_work_sync(&dev->mib_read);
2004     }
2005 
2006     dev->dev_ops->exit(dev);
2007     dsa_unregister_switch(dev->ds);
2008 
2009     if (dev->reset_gpio)
2010         gpiod_set_value_cansleep(dev->reset_gpio, 1);
2011 
2012 }
2013 EXPORT_SYMBOL(ksz_switch_remove);
2014 
2015 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
2016 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
2017 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!